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Milton Miller7f853352005-09-06 11:56:02 +10001/*
Lucas De Marchi25985ed2011-03-30 22:57:33 -03002 * udbg for NS16550 compatible serial ports
Milton Miller7f853352005-09-06 11:56:02 +10003 *
4 * Copyright (C) 2001-2005 PPC 64 Team, IBM Corp
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
Milton Miller7f853352005-09-06 11:56:02 +100011#include <linux/types.h>
Milton Miller188d2ce2005-09-06 11:57:00 +100012#include <asm/udbg.h>
Milton Miller7f853352005-09-06 11:56:02 +100013#include <asm/io.h>
Jack Millera0496d42011-04-14 22:32:08 +000014#include <asm/reg_a2.h>
Milton Miller7f853352005-09-06 11:56:02 +100015
16extern u8 real_readb(volatile u8 __iomem *addr);
17extern void real_writeb(u8 data, volatile u8 __iomem *addr);
Olof Johansson39c870d52007-02-04 16:36:49 -060018extern u8 real_205_readb(volatile u8 __iomem *addr);
19extern void real_205_writeb(u8 data, volatile u8 __iomem *addr);
Milton Miller7f853352005-09-06 11:56:02 +100020
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +100021#define UART_RBR 0
22#define UART_IER 1
23#define UART_FCR 2
24#define UART_LCR 3
25#define UART_MCR 4
26#define UART_LSR 5
27#define UART_MSR 6
28#define UART_SCR 7
29#define UART_THR UART_RBR
30#define UART_IIR UART_FCR
31#define UART_DLL UART_RBR
32#define UART_DLM UART_IER
33#define UART_DLAB UART_LCR
Milton Miller7f853352005-09-06 11:56:02 +100034
35#define LSR_DR 0x01 /* Data ready */
36#define LSR_OE 0x02 /* Overrun */
37#define LSR_PE 0x04 /* Parity error */
38#define LSR_FE 0x08 /* Framing error */
39#define LSR_BI 0x10 /* Break */
40#define LSR_THRE 0x20 /* Xmit holding register empty */
41#define LSR_TEMT 0x40 /* Xmitter empty */
42#define LSR_ERR 0x80 /* Error */
43
Benjamin Herrenschmidt463ce0e2005-11-23 17:56:06 +110044#define LCR_DLAB 0x80
45
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +100046static u8 (*udbg_uart_in)(unsigned int reg);
47static void (*udbg_uart_out)(unsigned int reg, u8 data);
Milton Miller7f853352005-09-06 11:56:02 +100048
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +100049static void udbg_uart_flush(void)
Milton Miller7f853352005-09-06 11:56:02 +100050{
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +100051 if (!udbg_uart_in)
52 return;
53
54 /* wait for idle */
55 while ((udbg_uart_in(UART_LSR) & LSR_THRE) == 0)
56 cpu_relax();
Andrew Klossneraf9c7242009-03-09 07:52:41 +000057}
58
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +100059static void udbg_uart_putc(char c)
Andrew Klossneraf9c7242009-03-09 07:52:41 +000060{
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +100061 if (!udbg_uart_out)
62 return;
63
64 if (c == '\n')
65 udbg_uart_putc('\r');
66 udbg_uart_flush();
67 udbg_uart_out(UART_THR, c);
Milton Miller7f853352005-09-06 11:56:02 +100068}
69
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +100070static int udbg_uart_getc_poll(void)
Milton Miller7f853352005-09-06 11:56:02 +100071{
Anton Blanchardcd32e2d2014-11-11 09:12:28 +110072 if (!udbg_uart_in)
73 return -1;
74
75 if (!(udbg_uart_in(UART_LSR) & LSR_DR))
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +100076 return udbg_uart_in(UART_RBR);
Anton Blanchardcd32e2d2014-11-11 09:12:28 +110077
Milton Miller7f853352005-09-06 11:56:02 +100078 return -1;
79}
80
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +100081static int udbg_uart_getc(void)
Milton Miller7f853352005-09-06 11:56:02 +100082{
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +100083 if (!udbg_uart_in)
84 return -1;
85 /* wait for char */
86 while (!(udbg_uart_in(UART_LSR) & LSR_DR))
87 cpu_relax();
88 return udbg_uart_in(UART_RBR);
Milton Miller7f853352005-09-06 11:56:02 +100089}
90
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +100091static void udbg_use_uart(void)
92{
93 udbg_putc = udbg_uart_putc;
94 udbg_flush = udbg_uart_flush;
95 udbg_getc = udbg_uart_getc;
96 udbg_getc_poll = udbg_uart_getc_poll;
97}
98
99void udbg_uart_setup(unsigned int speed, unsigned int clock)
Milton Miller7f853352005-09-06 11:56:02 +1000100{
Benjamin Herrenschmidt171505d2006-07-04 14:11:23 +1000101 unsigned int dll, base_bauds;
Benjamin Herrenschmidt463ce0e2005-11-23 17:56:06 +1100102
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000103 if (!udbg_uart_out)
104 return;
105
Benjamin Herrenschmidt171505d2006-07-04 14:11:23 +1000106 if (clock == 0)
107 clock = 1843200;
Benjamin Herrenschmidt463ce0e2005-11-23 17:56:06 +1100108 if (speed == 0)
109 speed = 9600;
Benjamin Herrenschmidt171505d2006-07-04 14:11:23 +1000110
111 base_bauds = clock / 16;
Benjamin Herrenschmidt463ce0e2005-11-23 17:56:06 +1100112 dll = base_bauds / speed;
Milton Miller7f853352005-09-06 11:56:02 +1000113
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000114 udbg_uart_out(UART_LCR, 0x00);
115 udbg_uart_out(UART_IER, 0xff);
116 udbg_uart_out(UART_IER, 0x00);
117 udbg_uart_out(UART_LCR, LCR_DLAB);
118 udbg_uart_out(UART_DLL, dll & 0xff);
119 udbg_uart_out(UART_DLM, dll >> 8);
120 /* 8 data, 1 stop, no parity */
121 udbg_uart_out(UART_LCR, 0x3);
122 /* RTS/DTR */
123 udbg_uart_out(UART_MCR, 0x3);
124 /* Clear & enable FIFOs */
125 udbg_uart_out(UART_FCR, 0x7);
Milton Miller7f853352005-09-06 11:56:02 +1000126}
127
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000128unsigned int udbg_probe_uart_speed(unsigned int clock)
Benjamin Herrenschmidt463ce0e2005-11-23 17:56:06 +1100129{
130 unsigned int dll, dlm, divisor, prescaler, speed;
131 u8 old_lcr;
Benjamin Herrenschmidt463ce0e2005-11-23 17:56:06 +1100132
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000133 old_lcr = udbg_uart_in(UART_LCR);
Benjamin Herrenschmidt463ce0e2005-11-23 17:56:06 +1100134
135 /* select divisor latch registers. */
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000136 udbg_uart_out(UART_LCR, old_lcr | LCR_DLAB);
Benjamin Herrenschmidt463ce0e2005-11-23 17:56:06 +1100137
138 /* now, read the divisor */
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000139 dll = udbg_uart_in(UART_DLL);
140 dlm = udbg_uart_in(UART_DLM);
Benjamin Herrenschmidt463ce0e2005-11-23 17:56:06 +1100141 divisor = dlm << 8 | dll;
142
143 /* check prescaling */
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000144 if (udbg_uart_in(UART_MCR) & 0x80)
Benjamin Herrenschmidt463ce0e2005-11-23 17:56:06 +1100145 prescaler = 4;
146 else
147 prescaler = 1;
148
149 /* restore the LCR */
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000150 udbg_uart_out(UART_LCR, old_lcr);
Benjamin Herrenschmidt463ce0e2005-11-23 17:56:06 +1100151
152 /* calculate speed */
153 speed = (clock / prescaler) / (divisor * 16);
154
155 /* sanity check */
roel kluinbb5e6492008-10-14 14:36:31 +0000156 if (speed > (clock / 16))
Benjamin Herrenschmidt463ce0e2005-11-23 17:56:06 +1100157 speed = 9600;
158
159 return speed;
160}
161
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000162static union {
163 unsigned char __iomem *mmio_base;
164 unsigned long pio_base;
165} udbg_uart;
166
167static unsigned int udbg_uart_stride = 1;
168
169static u8 udbg_uart_in_pio(unsigned int reg)
Milton Miller7f853352005-09-06 11:56:02 +1000170{
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000171 return inb(udbg_uart.pio_base + (reg * udbg_uart_stride));
Andrew Klossneraf9c7242009-03-09 07:52:41 +0000172}
173
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000174static void udbg_uart_out_pio(unsigned int reg, u8 data)
Andrew Klossneraf9c7242009-03-09 07:52:41 +0000175{
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000176 outb(data, udbg_uart.pio_base + (reg * udbg_uart_stride));
177}
178
179void udbg_uart_init_pio(unsigned long port, unsigned int stride)
180{
181 if (!port)
182 return;
183 udbg_uart.pio_base = port;
184 udbg_uart_stride = stride;
185 udbg_uart_in = udbg_uart_in_pio;
186 udbg_uart_out = udbg_uart_out_pio;
187 udbg_use_uart();
188}
189
190static u8 udbg_uart_in_mmio(unsigned int reg)
191{
192 return in_8(udbg_uart.mmio_base + (reg * udbg_uart_stride));
193}
194
195static void udbg_uart_out_mmio(unsigned int reg, u8 data)
196{
197 out_8(udbg_uart.mmio_base + (reg * udbg_uart_stride), data);
198}
199
200
201void udbg_uart_init_mmio(void __iomem *addr, unsigned int stride)
202{
203 if (!addr)
204 return;
205 udbg_uart.mmio_base = addr;
206 udbg_uart_stride = stride;
207 udbg_uart_in = udbg_uart_in_mmio;
208 udbg_uart_out = udbg_uart_out_mmio;
209 udbg_use_uart();
210}
211
212#ifdef CONFIG_PPC_MAPLE
213
214#define UDBG_UART_MAPLE_ADDR ((void __iomem *)0xf40003f8)
215
216static u8 udbg_uart_in_maple(unsigned int reg)
217{
218 return real_readb(UDBG_UART_MAPLE_ADDR + reg);
219}
220
221static void udbg_uart_out_maple(unsigned int reg, u8 val)
222{
223 real_writeb(val, UDBG_UART_MAPLE_ADDR + reg);
Milton Miller7f853352005-09-06 11:56:02 +1000224}
225
Michael Ellerman296167a2006-01-11 11:54:09 +1100226void __init udbg_init_maple_realmode(void)
Milton Miller7f853352005-09-06 11:56:02 +1000227{
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000228 udbg_uart_in = udbg_uart_in_maple;
229 udbg_uart_out = udbg_uart_out_maple;
230 udbg_use_uart();
Milton Miller7f853352005-09-06 11:56:02 +1000231}
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000232
Milton Miller7f853352005-09-06 11:56:02 +1000233#endif /* CONFIG_PPC_MAPLE */
Olof Johansson39c870d52007-02-04 16:36:49 -0600234
235#ifdef CONFIG_PPC_PASEMI
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000236
237#define UDBG_UART_PAS_ADDR ((void __iomem *)0xfcff03f8UL)
238
239static u8 udbg_uart_in_pas(unsigned int reg)
Olof Johansson39c870d52007-02-04 16:36:49 -0600240{
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000241 return real_205_readb(UDBG_UART_PAS_ADDR + reg);
Andrew Klossneraf9c7242009-03-09 07:52:41 +0000242}
243
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000244static void udbg_uart_out_pas(unsigned int reg, u8 val)
Andrew Klossneraf9c7242009-03-09 07:52:41 +0000245{
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000246 real_205_writeb(val, UDBG_UART_PAS_ADDR + reg);
Olof Johansson39c870d52007-02-04 16:36:49 -0600247}
248
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000249void __init udbg_init_pas_realmode(void)
Olof Johansson39c870d52007-02-04 16:36:49 -0600250{
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000251 udbg_uart_in = udbg_uart_in_pas;
252 udbg_uart_out = udbg_uart_out_pas;
253 udbg_use_uart();
Olof Johansson39c870d52007-02-04 16:36:49 -0600254}
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000255
256#endif /* CONFIG_PPC_PASEMI */
David Gibsond9b55a02007-05-08 12:59:31 +1000257
258#ifdef CONFIG_PPC_EARLY_DEBUG_44x
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000259
David Gibsond9b55a02007-05-08 12:59:31 +1000260#include <platforms/44x/44x.h>
261
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000262static u8 udbg_uart_in_44x_as1(unsigned int reg)
David Gibsond9b55a02007-05-08 12:59:31 +1000263{
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000264 return as1_readb((void __iomem *)PPC44x_EARLY_DEBUG_VIRTADDR + reg);
Andrew Klossneraf9c7242009-03-09 07:52:41 +0000265}
266
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000267static void udbg_uart_out_44x_as1(unsigned int reg, u8 val)
Andrew Klossneraf9c7242009-03-09 07:52:41 +0000268{
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000269 as1_writeb(val, (void __iomem *)PPC44x_EARLY_DEBUG_VIRTADDR + reg);
Hollis Blanchard70dea472007-09-17 05:56:47 -0500270}
271
David Gibsond9b55a02007-05-08 12:59:31 +1000272void __init udbg_init_44x_as1(void)
273{
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000274 udbg_uart_in = udbg_uart_in_44x_as1;
275 udbg_uart_out = udbg_uart_out_44x_as1;
276 udbg_use_uart();
David Gibsond9b55a02007-05-08 12:59:31 +1000277}
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000278
David Gibsond9b55a02007-05-08 12:59:31 +1000279#endif /* CONFIG_PPC_EARLY_DEBUG_44x */
Benjamin Herrenschmidt9dae8af2007-12-21 15:39:26 +1100280
281#ifdef CONFIG_PPC_EARLY_DEBUG_40x
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000282
283static u8 udbg_uart_in_40x(unsigned int reg)
Benjamin Herrenschmidt9dae8af2007-12-21 15:39:26 +1100284{
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000285 return real_readb((void __iomem *)CONFIG_PPC_EARLY_DEBUG_40x_PHYSADDR
286 + reg);
Andrew Klossneraf9c7242009-03-09 07:52:41 +0000287}
288
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000289static void udbg_uart_out_40x(unsigned int reg, u8 val)
Andrew Klossneraf9c7242009-03-09 07:52:41 +0000290{
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000291 real_writeb(val, (void __iomem *)CONFIG_PPC_EARLY_DEBUG_40x_PHYSADDR
292 + reg);
Benjamin Herrenschmidt9dae8af2007-12-21 15:39:26 +1100293}
294
295void __init udbg_init_40x_realmode(void)
296{
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000297 udbg_uart_in = udbg_uart_in_40x;
298 udbg_uart_out = udbg_uart_out_40x;
299 udbg_use_uart();
Benjamin Herrenschmidt9dae8af2007-12-21 15:39:26 +1100300}
Benjamin Herrenschmidt30925742013-07-15 13:03:12 +1000301
Benjamin Herrenschmidt9dae8af2007-12-21 15:39:26 +1100302#endif /* CONFIG_PPC_EARLY_DEBUG_40x */