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Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001/* SPDX-License-Identifier: GPL-2.0 */
H. Peter Anvin1965aae2008-10-22 22:26:29 -07002#ifndef _ASM_X86_MSR_INDEX_H
3#define _ASM_X86_MSR_INDEX_H
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +02004
Thomas Gleixnerd8eabc32019-02-21 12:36:50 +01005#include <linux/bits.h>
6
Borislav Petkov97fa21f2022-11-06 22:24:08 +01007/* CPU model specific register (MSR) numbers. */
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +02008
9/* x86-64 specific MSRs */
10#define MSR_EFER 0xc0000080 /* extended feature register */
11#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
12#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
13#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
14#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
15#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
16#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
17#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
Sheng Yang5df97402009-12-16 13:48:04 +080018#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +020019
20/* EFER bits: */
21#define _EFER_SCE 0 /* SYSCALL/SYSRET */
22#define _EFER_LME 8 /* Long mode enable */
23#define _EFER_LMA 10 /* Long mode active (read-only) */
24#define _EFER_NX 11 /* No execute enable */
Alexander Graf9962d032008-11-25 20:17:02 +010025#define _EFER_SVME 12 /* Enable virtualization */
Joerg Roedeleec4b142010-05-05 16:04:44 +020026#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
Alexander Grafd2062692009-02-02 16:23:50 +010027#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
Kim Phillipse7862ed2023-01-24 10:33:18 -060028#define _EFER_AUTOIBRS 21 /* Enable Automatic IBRS */
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +020029
30#define EFER_SCE (1<<_EFER_SCE)
31#define EFER_LME (1<<_EFER_LME)
32#define EFER_LMA (1<<_EFER_LMA)
33#define EFER_NX (1<<_EFER_NX)
Alexander Graf9962d032008-11-25 20:17:02 +010034#define EFER_SVME (1<<_EFER_SVME)
Joerg Roedeleec4b142010-05-05 16:04:44 +020035#define EFER_LMSLE (1<<_EFER_LMSLE)
Alexander Grafd2062692009-02-02 16:23:50 +010036#define EFER_FFXSR (1<<_EFER_FFXSR)
Kim Phillipse7862ed2023-01-24 10:33:18 -060037#define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS)
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +020038
39/* Intel MSRs. Some also available on other CPUs */
Tony Luck3f5a7892016-11-18 09:48:36 -080040
Peter Zijlstra (Intel)6650cdd2020-01-26 12:05:35 -080041#define MSR_TEST_CTRL 0x00000033
42#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29
43#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)
44
David Woodhouse1e340c62018-01-25 16:14:12 +000045#define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */
Thomas Gleixnerd8eabc32019-02-21 12:36:50 +010046#define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */
Tim Chen5bfbe3a2018-11-25 19:33:46 +010047#define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */
Thomas Gleixnerd8eabc32019-02-21 12:36:50 +010048#define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */
Konrad Rzeszutek Wilk9f65fb22018-05-09 21:41:38 +020049#define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */
Thomas Gleixnerd8eabc32019-02-21 12:36:50 +010050#define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */
Pawan Gupta4ad32782022-07-08 13:36:09 -070051#define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */
52#define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT)
David Woodhouse1e340c62018-01-25 16:14:12 +000053
Breno Leitao0125acd2022-11-28 07:31:48 -080054/* A mask for bits which the kernel toggles when controlling mitigations */
55#define SPEC_CTRL_MITIGATIONS_MASK (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \
56 | SPEC_CTRL_RRSBA_DIS_S)
57
David Woodhouse1e340c62018-01-25 16:14:12 +000058#define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */
Thomas Gleixnerd8eabc32019-02-21 12:36:50 +010059#define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */
Borislav Petkov (AMD)1b5277c2023-06-29 17:43:40 +020060#define PRED_CMD_SBPB BIT(7) /* Selective Branch Prediction Barrier */
David Woodhouse1e340c62018-01-25 16:14:12 +000061
Tony Luck3f5a7892016-11-18 09:48:36 -080062#define MSR_PPIN_CTL 0x0000004e
63#define MSR_PPIN 0x0000004f
64
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +020065#define MSR_IA32_PERFCTR0 0x000000c1
66#define MSR_IA32_PERFCTR1 0x000000c2
67#define MSR_FSB_FREQ 0x000000cd
Len Brown5369a212015-11-12 02:42:32 -050068#define MSR_PLATFORM_INFO 0x000000ce
Kyle Huey90218ac2017-03-20 01:16:25 -070069#define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31
70#define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +020071
Fenghua Yubd688c62019-06-19 18:33:55 -070072#define MSR_IA32_UMWAIT_CONTROL 0xe1
73#define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0)
74#define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1)
75/*
76 * The time field is bit[31:2], but representing a 32bit value with
77 * bit[1:0] zero.
78 */
79#define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U)
80
Peter Zijlstra (Intel)6650cdd2020-01-26 12:05:35 -080081/* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */
82#define MSR_IA32_CORE_CAPS 0x000000cf
Tony Luckdb1af122022-05-06 15:54:00 -070083#define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT 2
84#define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT)
Peter Zijlstra (Intel)6650cdd2020-01-26 12:05:35 -080085#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5
86#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT)
87
Len Brown40496c82017-01-07 23:21:18 -050088#define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
Len Brown14796fc2011-01-18 20:48:27 -050089#define NHM_C3_AUTO_DEMOTE (1UL << 25)
90#define NHM_C1_AUTO_DEMOTE (1UL << 26)
Len Brownbfb53cc2011-02-16 01:32:48 -050091#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
Matt Turnera00072a2018-02-13 11:12:05 -080092#define SNB_C3_AUTO_UNDEMOTE (1UL << 27)
93#define SNB_C1_AUTO_UNDEMOTE (1UL << 28)
Len Brown14796fc2011-01-18 20:48:27 -050094
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +020095#define MSR_MTRRcap 0x000000fe
David Woodhouse1e340c62018-01-25 16:14:12 +000096
97#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a
Thomas Gleixnerd8eabc32019-02-21 12:36:50 +010098#define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */
99#define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */
Peter Zijlstra6ad0ad22022-06-24 13:48:58 +0200100#define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */
Thomas Gleixnerd8eabc32019-02-21 12:36:50 +0100101#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */
102#define ARCH_CAP_SSB_NO BIT(4) /*
103 * Not susceptible to Speculative Store Bypass
104 * attack, so no Speculative Store Bypass
105 * control required.
106 */
Andi Kleened5194c2019-01-18 16:50:16 -0800107#define ARCH_CAP_MDS_NO BIT(5) /*
108 * Not susceptible to
109 * Microarchitectural Data
110 * Sampling (MDS) vulnerabilities.
111 */
Vineela Tummalapallidb4d30f2019-11-04 12:22:01 +0100112#define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /*
113 * The processor is not susceptible to a
114 * machine check error due to modifying the
115 * code page size along with either the
116 * physical address or cache type
117 * without TLB invalidation.
118 */
Pawan Guptac2955f22019-10-23 10:45:50 +0200119#define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */
Pawan Gupta1b42f012019-10-23 11:30:45 +0200120#define ARCH_CAP_TAA_NO BIT(8) /*
121 * Not susceptible to
122 * TSX Async Abort (TAA) vulnerabilities.
123 */
Pawan Gupta51802182022-05-19 20:27:08 -0700124#define ARCH_CAP_SBDR_SSDP_NO BIT(13) /*
125 * Not susceptible to SBDR and SSDP
126 * variants of Processor MMIO stale data
127 * vulnerabilities.
128 */
129#define ARCH_CAP_FBSDP_NO BIT(14) /*
130 * Not susceptible to FBSDP variant of
131 * Processor MMIO stale data
132 * vulnerabilities.
133 */
134#define ARCH_CAP_PSDP_NO BIT(15) /*
135 * Not susceptible to PSDP variant of
136 * Processor MMIO stale data
137 * vulnerabilities.
138 */
139#define ARCH_CAP_FB_CLEAR BIT(17) /*
140 * VERW clears CPU fill buffer
141 * even on MDS_NO CPUs.
142 */
Pawan Gupta027bbb82022-05-19 20:35:15 -0700143#define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /*
144 * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS]
145 * bit available to control VERW
146 * behavior.
147 */
Pawan Gupta4ad32782022-07-08 13:36:09 -0700148#define ARCH_CAP_RRSBA BIT(19) /*
149 * Indicates RET may use predictors
150 * other than the RSB. With eIBRS
151 * enabled predictions in kernel mode
152 * are restricted to targets in
153 * kernel.
154 */
Daniel Sneddon2b129932022-08-02 15:47:01 -0700155#define ARCH_CAP_PBRSB_NO BIT(24) /*
156 * Not susceptible to Post-Barrier
157 * Return Stack Buffer Predictions.
158 */
Daniel Sneddon8974eb52023-07-12 19:43:11 -0700159#define ARCH_CAP_GDS_CTRL BIT(25) /*
160 * CPU is vulnerable to Gather
161 * Data Sampling (GDS) and
162 * has controls for mitigation.
163 */
164#define ARCH_CAP_GDS_NO BIT(26) /*
165 * CPU is not vulnerable to Gather
166 * Data Sampling (GDS).
167 */
David Woodhouse1e340c62018-01-25 16:14:12 +0000168
Daniel Sneddonb8d1d162022-08-16 16:19:42 -0700169#define ARCH_CAP_XAPIC_DISABLE BIT(21) /*
170 * IA32_XAPIC_DISABLE_STATUS MSR
171 * supported
172 */
173
Paolo Bonzini3fa045b2018-07-02 13:03:48 +0200174#define MSR_IA32_FLUSH_CMD 0x0000010b
Thomas Gleixnerd8eabc32019-02-21 12:36:50 +0100175#define L1D_FLUSH BIT(0) /*
176 * Writeback and invalidate the
177 * L1 data cache.
178 */
Paolo Bonzini3fa045b2018-07-02 13:03:48 +0200179
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200180#define MSR_IA32_BBL_CR_CTL 0x00000119
john cooper91c9c3e2011-01-21 00:21:00 -0500181#define MSR_IA32_BBL_CR_CTL3 0x0000011e
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200182
Pawan Guptac2955f22019-10-23 10:45:50 +0200183#define MSR_IA32_TSX_CTRL 0x00000122
184#define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */
185#define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */
186
Mark Gross7e5b3c22020-04-16 17:54:04 +0200187#define MSR_IA32_MCU_OPT_CTRL 0x00000123
Pawan Gupta400331f2022-03-10 14:02:09 -0800188#define RNGDS_MITG_DIS BIT(0) /* SRBDS support */
189#define RTM_ALLOW BIT(1) /* TSX development mode */
Pawan Gupta027bbb82022-05-19 20:35:15 -0700190#define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */
Daniel Sneddon8974eb52023-07-12 19:43:11 -0700191#define GDS_MITG_DIS BIT(4) /* Disable GDS mitigation */
192#define GDS_MITG_LOCKED BIT(5) /* GDS mitigation locked */
Mark Gross7e5b3c22020-04-16 17:54:04 +0200193
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200194#define MSR_IA32_SYSENTER_CS 0x00000174
195#define MSR_IA32_SYSENTER_ESP 0x00000175
196#define MSR_IA32_SYSENTER_EIP 0x00000176
197
198#define MSR_IA32_MCG_CAP 0x00000179
199#define MSR_IA32_MCG_STATUS 0x0000017a
200#define MSR_IA32_MCG_CTL 0x0000017b
Tony Luck68299a42020-10-30 12:04:00 -0700201#define MSR_ERROR_CONTROL 0x0000017f
Ashok Rajbc12edb2015-06-04 18:55:22 +0200202#define MSR_IA32_MCG_EXT_CTL 0x000004d0
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200203
Andi Kleena7e3ed12011-03-03 10:34:47 +0800204#define MSR_OFFCORE_RSP_0 0x000001a6
205#define MSR_OFFCORE_RSP_1 0x000001a7
Len Brownc4d30662015-04-10 00:22:56 -0400206#define MSR_TURBO_RATIO_LIMIT 0x000001ad
207#define MSR_TURBO_RATIO_LIMIT1 0x000001ae
208#define MSR_TURBO_RATIO_LIMIT2 0x000001af
Andi Kleena7e3ed12011-03-03 10:34:47 +0800209
Kan Liang38aaf922023-01-04 12:13:42 -0800210#define MSR_SNOOP_RSP_0 0x00001328
211#define MSR_SNOOP_RSP_1 0x00001329
212
Stephane Eranian225ce532012-02-09 23:20:52 +0100213#define MSR_LBR_SELECT 0x000001c8
214#define MSR_LBR_TOS 0x000001c9
Srinivas Pandruvadaed7bde72020-06-26 11:34:00 -0700215
216#define MSR_IA32_POWER_CTL 0x000001fc
217#define MSR_IA32_POWER_CTL_BIT_EE 19
218
Tony Luckdb1af122022-05-06 15:54:00 -0700219/* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */
220#define MSR_INTEGRITY_CAPS 0x000002d9
Jithu Josephc68e3d42023-03-21 17:33:54 -0700221#define MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT 2
222#define MSR_INTEGRITY_CAPS_ARRAY_BIST BIT(MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT)
Tony Luckdb1af122022-05-06 15:54:00 -0700223#define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4
224#define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT)
Jithu Joseph97a5e802023-10-05 12:51:29 -0700225#define MSR_INTEGRITY_CAPS_SAF_GEN_MASK GENMASK_ULL(10, 9)
Tony Luckdb1af122022-05-06 15:54:00 -0700226
Stephane Eranian225ce532012-02-09 23:20:52 +0100227#define MSR_LBR_NHM_FROM 0x00000680
228#define MSR_LBR_NHM_TO 0x000006c0
229#define MSR_LBR_CORE_FROM 0x00000040
230#define MSR_LBR_CORE_TO 0x00000060
231
Andi Kleenb83ff1c2015-05-10 12:22:41 -0700232#define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */
233#define LBR_INFO_MISPRED BIT_ULL(63)
234#define LBR_INFO_IN_TX BIT_ULL(62)
235#define LBR_INFO_ABORT BIT_ULL(61)
Kan Liangd6a162a2020-07-03 05:49:13 -0700236#define LBR_INFO_CYC_CNT_VALID BIT_ULL(60)
Andi Kleenb83ff1c2015-05-10 12:22:41 -0700237#define LBR_INFO_CYCLES 0xffff
Kan Liangd6a162a2020-07-03 05:49:13 -0700238#define LBR_INFO_BR_TYPE_OFFSET 56
239#define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET)
Kan Liang33744912023-10-25 13:16:23 -0700240#define LBR_INFO_BR_CNTR_OFFSET 32
241#define LBR_INFO_BR_CNTR_NUM 4
242#define LBR_INFO_BR_CNTR_BITS 2
243#define LBR_INFO_BR_CNTR_MASK GENMASK_ULL(LBR_INFO_BR_CNTR_BITS - 1, 0)
244#define LBR_INFO_BR_CNTR_FULL_MASK GENMASK_ULL(LBR_INFO_BR_CNTR_NUM * LBR_INFO_BR_CNTR_BITS - 1, 0)
Kan Liangd6a162a2020-07-03 05:49:13 -0700245
246#define MSR_ARCH_LBR_CTL 0x000014ce
247#define ARCH_LBR_CTL_LBREN BIT(0)
248#define ARCH_LBR_CTL_CPL_OFFSET 1
249#define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET)
250#define ARCH_LBR_CTL_STACK_OFFSET 3
251#define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET)
252#define ARCH_LBR_CTL_FILTER_OFFSET 16
253#define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET)
254#define MSR_ARCH_LBR_DEPTH 0x000014cf
255#define MSR_ARCH_LBR_FROM_0 0x00001500
256#define MSR_ARCH_LBR_TO_0 0x00001600
257#define MSR_ARCH_LBR_INFO_0 0x00001200
Andi Kleenb83ff1c2015-05-10 12:22:41 -0700258
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200259#define MSR_IA32_PEBS_ENABLE 0x000003f1
Kan Liangc22497f2019-04-02 12:45:02 -0700260#define MSR_PEBS_DATA_CFG 0x000003f2
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200261#define MSR_IA32_DS_AREA 0x00000600
262#define MSR_IA32_PERF_CAPABILITIES 0x00000345
Kan Liangd0946a82021-04-12 07:30:44 -0700263#define PERF_CAP_METRICS_IDX 15
264#define PERF_CAP_PT_IDX 16
265
Stephane Eranianf20093e2013-01-24 16:10:32 +0100266#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
Like Xuc59a1f12022-04-11 18:19:36 +0800267#define PERF_CAP_PEBS_TRAP BIT_ULL(6)
268#define PERF_CAP_ARCH_REG BIT_ULL(7)
269#define PERF_CAP_PEBS_FORMAT 0xf00
270#define PERF_CAP_PEBS_BASELINE BIT_ULL(14)
271#define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \
272 PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE)
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200273
Alexander Shishkin52ca9ce2015-01-30 12:39:52 +0200274#define MSR_IA32_RTIT_CTL 0x00000570
Chao Peng887eda12018-10-24 16:05:05 +0800275#define RTIT_CTL_TRACEEN BIT(0)
276#define RTIT_CTL_CYCLEACC BIT(1)
277#define RTIT_CTL_OS BIT(2)
278#define RTIT_CTL_USR BIT(3)
279#define RTIT_CTL_PWR_EVT_EN BIT(4)
280#define RTIT_CTL_FUP_ON_PTW BIT(5)
Luwei Kang69843a92018-10-24 16:05:08 +0800281#define RTIT_CTL_FABRIC_EN BIT(6)
Chao Peng887eda12018-10-24 16:05:05 +0800282#define RTIT_CTL_CR3EN BIT(7)
283#define RTIT_CTL_TOPA BIT(8)
284#define RTIT_CTL_MTC_EN BIT(9)
285#define RTIT_CTL_TSC_EN BIT(10)
286#define RTIT_CTL_DISRETC BIT(11)
287#define RTIT_CTL_PTW_EN BIT(12)
288#define RTIT_CTL_BRANCH_EN BIT(13)
Alexander Shishkin28c24de2022-01-26 12:48:14 +0200289#define RTIT_CTL_EVENT_EN BIT(31)
Alexander Shishkin161a9a32022-01-26 12:48:15 +0200290#define RTIT_CTL_NOTNT BIT_ULL(55)
Chao Peng887eda12018-10-24 16:05:05 +0800291#define RTIT_CTL_MTC_RANGE_OFFSET 14
292#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
293#define RTIT_CTL_CYC_THRESH_OFFSET 19
294#define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
295#define RTIT_CTL_PSB_FREQ_OFFSET 24
296#define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
297#define RTIT_CTL_ADDR0_OFFSET 32
298#define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET)
299#define RTIT_CTL_ADDR1_OFFSET 36
300#define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET)
301#define RTIT_CTL_ADDR2_OFFSET 40
302#define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET)
303#define RTIT_CTL_ADDR3_OFFSET 44
304#define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET)
Alexander Shishkin52ca9ce2015-01-30 12:39:52 +0200305#define MSR_IA32_RTIT_STATUS 0x00000571
Chao Peng887eda12018-10-24 16:05:05 +0800306#define RTIT_STATUS_FILTEREN BIT(0)
307#define RTIT_STATUS_CONTEXTEN BIT(1)
308#define RTIT_STATUS_TRIGGEREN BIT(2)
309#define RTIT_STATUS_BUFFOVF BIT(3)
310#define RTIT_STATUS_ERROR BIT(4)
311#define RTIT_STATUS_STOPPED BIT(5)
Luwei Kang69843a92018-10-24 16:05:08 +0800312#define RTIT_STATUS_BYTECNT_OFFSET 32
313#define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET)
Alexander Shishkinf127fa02016-04-27 18:44:44 +0300314#define MSR_IA32_RTIT_ADDR0_A 0x00000580
315#define MSR_IA32_RTIT_ADDR0_B 0x00000581
316#define MSR_IA32_RTIT_ADDR1_A 0x00000582
317#define MSR_IA32_RTIT_ADDR1_B 0x00000583
318#define MSR_IA32_RTIT_ADDR2_A 0x00000584
319#define MSR_IA32_RTIT_ADDR2_B 0x00000585
320#define MSR_IA32_RTIT_ADDR3_A 0x00000586
321#define MSR_IA32_RTIT_ADDR3_B 0x00000587
Alexander Shishkin52ca9ce2015-01-30 12:39:52 +0200322#define MSR_IA32_RTIT_CR3_MATCH 0x00000572
323#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
324#define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561
325
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200326#define MSR_MTRRfix64K_00000 0x00000250
327#define MSR_MTRRfix16K_80000 0x00000258
328#define MSR_MTRRfix16K_A0000 0x00000259
329#define MSR_MTRRfix4K_C0000 0x00000268
330#define MSR_MTRRfix4K_C8000 0x00000269
331#define MSR_MTRRfix4K_D0000 0x0000026a
332#define MSR_MTRRfix4K_D8000 0x0000026b
333#define MSR_MTRRfix4K_E0000 0x0000026c
334#define MSR_MTRRfix4K_E8000 0x0000026d
335#define MSR_MTRRfix4K_F0000 0x0000026e
336#define MSR_MTRRfix4K_F8000 0x0000026f
337#define MSR_MTRRdefType 0x000002ff
338
venkatesh.pallipadi@intel.com2e5d9c82008-03-18 17:00:14 -0700339#define MSR_IA32_CR_PAT 0x00000277
340
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200341#define MSR_IA32_DEBUGCTLMSR 0x000001d9
342#define MSR_IA32_LASTBRANCHFROMIP 0x000001db
343#define MSR_IA32_LASTBRANCHTOIP 0x000001dc
344#define MSR_IA32_LASTINTFROMIP 0x000001dd
345#define MSR_IA32_LASTINTTOIP 0x000001de
346
Fenghua Yuf0f2f9f2020-09-15 09:30:10 -0700347#define MSR_IA32_PASID 0x00000d93
348#define MSR_IA32_PASID_VALID BIT_ULL(31)
349
Roland McGrathd2499d82008-01-30 13:30:54 +0100350/* DEBUGCTLMSR bits (others vary by model): */
Peter Zijlstra7c5ecaf2010-03-25 14:51:49 +0100351#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
Kyle Hueyb9894a22017-02-14 00:11:03 -0800352#define DEBUGCTLMSR_BTF_SHIFT 1
Peter Zijlstra7c5ecaf2010-03-25 14:51:49 +0100353#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
Fenghua Yuebb10642021-03-22 13:53:24 +0000354#define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2)
Peter Zijlstra7c5ecaf2010-03-25 14:51:49 +0100355#define DEBUGCTLMSR_TR (1UL << 6)
356#define DEBUGCTLMSR_BTS (1UL << 7)
357#define DEBUGCTLMSR_BTINT (1UL << 8)
358#define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9)
359#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
360#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
Andi Kleenaf3bdb92018-08-08 00:12:07 -0700361#define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12)
Kan Liang60893272017-05-12 07:51:13 -0700362#define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14
363#define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT)
Roland McGrathd2499d82008-01-30 13:30:54 +0100364
Andi Kleend0dc8492015-09-09 14:53:59 -0700365#define MSR_PEBS_FRONTEND 0x000003f7
366
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200367#define MSR_IA32_MC0_CTL 0x00000400
368#define MSR_IA32_MC0_STATUS 0x00000401
369#define MSR_IA32_MC0_ADDR 0x00000402
370#define MSR_IA32_MC0_MISC 0x00000403
371
Linus Torvalds6842d982012-12-18 12:34:29 -0800372/* C-state Residency Counters */
373#define MSR_PKG_C3_RESIDENCY 0x000003f8
374#define MSR_PKG_C6_RESIDENCY 0x000003f9
Len Brown0539ba112017-02-10 00:27:20 -0500375#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa
Linus Torvalds6842d982012-12-18 12:34:29 -0800376#define MSR_PKG_C7_RESIDENCY 0x000003fa
377#define MSR_CORE_C3_RESIDENCY 0x000003fc
378#define MSR_CORE_C6_RESIDENCY 0x000003fd
379#define MSR_CORE_C7_RESIDENCY 0x000003fe
Dasaratharaman Chandramoulifb5d4322015-05-20 09:49:34 -0700380#define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff
Linus Torvalds6842d982012-12-18 12:34:29 -0800381#define MSR_PKG_C2_RESIDENCY 0x0000060d
Kristen Carlson Accardica587102012-11-21 05:22:43 -0800382#define MSR_PKG_C8_RESIDENCY 0x00000630
383#define MSR_PKG_C9_RESIDENCY 0x00000631
384#define MSR_PKG_C10_RESIDENCY 0x00000632
Linus Torvalds6842d982012-12-18 12:34:29 -0800385
Len Brown5a634262016-04-06 17:15:55 -0400386/* Interrupt Response Limit */
387#define MSR_PKGC3_IRTL 0x0000060a
388#define MSR_PKGC6_IRTL 0x0000060b
389#define MSR_PKGC7_IRTL 0x0000060c
390#define MSR_PKGC8_IRTL 0x00000633
391#define MSR_PKGC9_IRTL 0x00000634
392#define MSR_PKGC10_IRTL 0x00000635
393
Linus Torvalds6842d982012-12-18 12:34:29 -0800394/* Run Time Average Power Limiting (RAPL) Interface */
395
Sumeet Pawnikarf52ba932021-08-20 17:42:43 +0530396#define MSR_VR_CURRENT_CONFIG 0x00000601
Linus Torvalds6842d982012-12-18 12:34:29 -0800397#define MSR_RAPL_POWER_UNIT 0x00000606
398
399#define MSR_PKG_POWER_LIMIT 0x00000610
400#define MSR_PKG_ENERGY_STATUS 0x00000611
401#define MSR_PKG_PERF_STATUS 0x00000613
402#define MSR_PKG_POWER_INFO 0x00000614
403
404#define MSR_DRAM_POWER_LIMIT 0x00000618
405#define MSR_DRAM_ENERGY_STATUS 0x00000619
406#define MSR_DRAM_PERF_STATUS 0x0000061b
407#define MSR_DRAM_POWER_INFO 0x0000061c
408
409#define MSR_PP0_POWER_LIMIT 0x00000638
410#define MSR_PP0_ENERGY_STATUS 0x00000639
411#define MSR_PP0_POLICY 0x0000063a
412#define MSR_PP0_PERF_STATUS 0x0000063b
413
414#define MSR_PP1_POWER_LIMIT 0x00000640
415#define MSR_PP1_ENERGY_STATUS 0x00000641
416#define MSR_PP1_POLICY 0x00000642
417
Stephane Eranian5cde2652020-05-27 15:46:59 -0700418#define MSR_AMD_RAPL_POWER_UNIT 0xc0010299
Victor Ding43756a22020-10-27 07:23:56 +0000419#define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a
Victor Ding298ed2b2020-10-27 07:23:54 +0000420#define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b
Stephane Eranian5cde2652020-05-27 15:46:59 -0700421
Vladimir Zapolskiy4a6772f2016-03-26 20:47:00 +0200422/* Config TDP MSRs */
Rafael J. Wysocki82bb70c2015-08-24 23:10:02 +0200423#define MSR_CONFIG_TDP_NOMINAL 0x00000648
424#define MSR_CONFIG_TDP_LEVEL_1 0x00000649
425#define MSR_CONFIG_TDP_LEVEL_2 0x0000064A
426#define MSR_CONFIG_TDP_CONTROL 0x0000064B
427#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C
428
Srinivas Pandruvadadcee75b2016-04-17 15:03:00 -0700429#define MSR_PLATFORM_ENERGY_STATUS 0x0000064D
Len Brown4af184e2022-05-31 17:29:13 -1000430#define MSR_SECONDARY_TURBO_RATIO_LIMIT 0x00000650
Srinivas Pandruvadadcee75b2016-04-17 15:03:00 -0700431
Len Brown0b2bb692015-03-26 00:50:30 -0400432#define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
433#define MSR_PKG_ANY_CORE_C0_RES 0x00000659
434#define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
435#define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
436
Len Brown144b44b2013-11-09 00:30:16 -0500437#define MSR_CORE_C1_RES 0x00000660
Len Brown0539ba112017-02-10 00:27:20 -0500438#define MSR_MODULE_C6_RES_MS 0x00000664
Len Brown144b44b2013-11-09 00:30:16 -0500439
Len Brown8c058d532014-07-31 15:21:24 -0400440#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668
441#define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669
442
Len Brown8a34fd02017-01-12 23:22:28 -0500443#define MSR_ATOM_CORE_RATIOS 0x0000066a
444#define MSR_ATOM_CORE_VIDS 0x0000066b
445#define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c
446#define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d
447
Len Brown3a9a9412014-08-15 02:39:52 -0400448#define MSR_CORE_PERF_LIMIT_REASONS 0x00000690
449#define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0
450#define MSR_RING_PERF_LIMIT_REASONS 0x000006B1
451
Peter Zijlstra991625f2022-03-08 16:30:35 +0100452/* Control-flow Enforcement Technology MSRs */
453#define MSR_IA32_U_CET 0x000006a0 /* user mode cet */
454#define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */
455#define CET_SHSTK_EN BIT_ULL(0)
456#define CET_WRSS_EN BIT_ULL(1)
457#define CET_ENDBR_EN BIT_ULL(2)
458#define CET_LEG_IW_EN BIT_ULL(3)
459#define CET_NO_TRACK_EN BIT_ULL(4)
460#define CET_SUPPRESS_DISABLE BIT_ULL(5)
461#define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9))
462#define CET_SUPPRESS BIT_ULL(10)
463#define CET_WAIT_ENDBR BIT_ULL(11)
464
465#define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */
466#define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */
467#define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */
468#define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */
469#define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */
470
Dirk Brandewie2f86dc42014-11-06 09:40:47 -0800471/* Hardware P state interface */
472#define MSR_PPERF 0x0000064e
473#define MSR_PERF_LIMIT_REASONS 0x0000064f
474#define MSR_PM_ENABLE 0x00000770
475#define MSR_HWP_CAPABILITIES 0x00000771
476#define MSR_HWP_REQUEST_PKG 0x00000772
477#define MSR_HWP_INTERRUPT 0x00000773
478#define MSR_HWP_REQUEST 0x00000774
479#define MSR_HWP_STATUS 0x00000777
480
481/* CPUID.6.EAX */
482#define HWP_BASE_BIT (1<<7)
483#define HWP_NOTIFICATIONS_BIT (1<<8)
484#define HWP_ACTIVITY_WINDOW_BIT (1<<9)
485#define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10)
486#define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11)
487
488/* IA32_HWP_CAPABILITIES */
Len Brown670e27d2015-12-01 01:36:39 -0500489#define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff)
490#define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff)
491#define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff)
492#define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff)
Dirk Brandewie2f86dc42014-11-06 09:40:47 -0800493
494/* IA32_HWP_REQUEST */
495#define HWP_MIN_PERF(x) (x & 0xff)
496#define HWP_MAX_PERF(x) ((x & 0xff) << 8)
497#define HWP_DESIRED_PERF(x) ((x & 0xff) << 16)
Len Brown2fc49cb2017-04-29 00:11:46 -0400498#define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24)
Len Brown8d84e902017-02-25 11:56:29 -0500499#define HWP_EPP_PERFORMANCE 0x00
500#define HWP_EPP_BALANCE_PERFORMANCE 0x80
501#define HWP_EPP_BALANCE_POWERSAVE 0xC0
502#define HWP_EPP_POWERSAVE 0xFF
Len Brown2fc49cb2017-04-29 00:11:46 -0400503#define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32)
504#define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42)
Dirk Brandewie2f86dc42014-11-06 09:40:47 -0800505
506/* IA32_HWP_STATUS */
507#define HWP_GUARANTEED_CHANGE(x) (x & 0x1)
508#define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4)
509
510/* IA32_HWP_INTERRUPT */
511#define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1)
512#define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2)
513
Joerg Roedel5bbc0972011-04-15 14:47:40 +0200514#define MSR_AMD64_MC0_MASK 0xc0010044
515
Andi Kleena2d32bc2009-07-09 00:31:44 +0200516#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
517#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
518#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
519#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
520
Joerg Roedel5bbc0972011-04-15 14:47:40 +0200521#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
522
Andi Kleen03195c62009-02-12 13:49:35 +0100523/* These are consecutive and not in the normal 4er MCE bank block */
524#define MSR_IA32_MC0_CTL2 0x00000280
Andi Kleena2d32bc2009-07-09 00:31:44 +0200525#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
526
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200527#define MSR_P6_PERFCTR0 0x000000c1
528#define MSR_P6_PERFCTR1 0x000000c2
529#define MSR_P6_EVNTSEL0 0x00000186
530#define MSR_P6_EVNTSEL1 0x00000187
531
Vince Weavere717bf42012-09-26 14:12:52 -0400532#define MSR_KNC_PERFCTR0 0x00000020
533#define MSR_KNC_PERFCTR1 0x00000021
534#define MSR_KNC_EVNTSEL0 0x00000028
535#define MSR_KNC_EVNTSEL1 0x00000029
536
Andi Kleen069e0c32013-06-25 08:12:33 -0700537/* Alternative perfctr range with full access. */
538#define MSR_IA32_PMC0 0x000004c1
539
Alexander Shishkin42880f72019-08-06 11:46:01 +0300540/* Auto-reload via MSR instead of DS area */
541#define MSR_RELOAD_PMC0 0x000014c1
542#define MSR_RELOAD_FIXED_CTR0 0x00001309
543
Kai Huang765a0542023-12-08 09:07:21 -0800544/* KeyID partitioning between MKTME and TDX */
545#define MSR_IA32_MKTME_KEYID_PARTITIONING 0x00000087
546
Borislav Petkov342061c2019-08-19 09:01:40 +0200547/*
548 * AMD64 MSRs. Not complete. See the architecture manual for a more
549 * complete list.
550 */
Andreas Herrmann29d08872008-12-16 19:16:34 +0100551#define MSR_AMD64_PATCH_LEVEL 0x0000008b
Joerg Roedelfbc0db72011-03-25 09:44:46 +0100552#define MSR_AMD64_TSC_RATIO 0xc0000104
stephane eranian12db6482008-03-07 13:05:39 -0800553#define MSR_AMD64_NB_CFG 0xc001001f
Andreas Herrmann29d08872008-12-16 19:16:34 +0100554#define MSR_AMD64_PATCH_LOADER 0xc0010020
Borislav Petkov342061c2019-08-19 09:01:40 +0200555#define MSR_AMD_PERF_CTL 0xc0010062
556#define MSR_AMD_PERF_STATUS 0xc0010063
557#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
Andreas Herrmann035a02c2010-03-19 12:09:22 +0100558#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
559#define MSR_AMD64_OSVW_STATUS 0xc0010141
Jan Beulich4e3f77d2019-11-11 15:46:26 +0100560#define MSR_AMD_PPIN_CTL 0xc00102f0
561#define MSR_AMD_PPIN 0xc00102f1
Borislav Petkov1068ed42020-06-08 16:19:49 +0200562#define MSR_AMD64_CPUID_FN_1 0xc0011004
Borislav Petkov3b564962014-01-15 00:07:11 +0100563#define MSR_AMD64_LS_CFG 0xc0011020
Joerg Roedel67ec6602010-05-17 14:43:35 +0200564#define MSR_AMD64_DC_CFG 0xc0011022
Maciej S. Szmigiero2770d472023-10-19 18:06:57 +0200565#define MSR_AMD64_TW_CFG 0xc0011023
Borislav Petkov2632dae2022-11-14 12:44:01 +0100566
567#define MSR_AMD64_DE_CFG 0xc0011029
568#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1
569#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
Borislav Petkov (AMD)522b1d62023-07-15 13:41:28 +0200570#define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9
Borislav Petkov2632dae2022-11-14 12:44:01 +0100571
Boris Ostrovskyf0322bd2013-01-29 16:32:49 -0500572#define MSR_AMD64_BU_CFG2 0xc001102a
Stephane Eranian4f8a6b12007-10-19 20:35:03 +0200573#define MSR_AMD64_IBSFETCHCTL 0xc0011030
574#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
575#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
Robert Richterb7074f12011-12-15 17:56:37 +0100576#define MSR_AMD64_IBSFETCH_REG_COUNT 3
577#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
Stephane Eranian4f8a6b12007-10-19 20:35:03 +0200578#define MSR_AMD64_IBSOPCTL 0xc0011033
579#define MSR_AMD64_IBSOPRIP 0xc0011034
580#define MSR_AMD64_IBSOPDATA 0xc0011035
581#define MSR_AMD64_IBSOPDATA2 0xc0011036
582#define MSR_AMD64_IBSOPDATA3 0xc0011037
583#define MSR_AMD64_IBSDCLINAD 0xc0011038
584#define MSR_AMD64_IBSDCPHYSAD 0xc0011039
Robert Richterb7074f12011-12-15 17:56:37 +0100585#define MSR_AMD64_IBSOP_REG_COUNT 7
586#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
Stephane Eranian4f8a6b12007-10-19 20:35:03 +0200587#define MSR_AMD64_IBSCTL 0xc001103a
Robert Richter25da6952010-09-21 15:49:31 +0200588#define MSR_AMD64_IBSBRTARGET 0xc001103b
Kim Phillips36e1be82020-09-08 16:47:38 -0500589#define MSR_AMD64_ICIBSEXTDCTL 0xc001103c
Aravind Gopalakrishnan904cb362014-11-10 14:24:26 -0600590#define MSR_AMD64_IBSOPDATA4 0xc001103d
Robert Richterb7074f12011-12-15 17:56:37 +0100591#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
Maxim Levitsky39150352022-02-07 17:54:26 +0200592#define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b
Tom Lendacky69372cf02020-12-10 11:09:36 -0600593#define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e
Joerg Roedel29dcc602020-09-07 15:15:20 +0200594#define MSR_AMD64_SEV_ES_GHCB 0xc0010130
Tom Lendacky1958b5f2017-10-20 09:30:54 -0500595#define MSR_AMD64_SEV 0xc0010131
596#define MSR_AMD64_SEV_ENABLED_BIT 0
Joerg Roedelb57de6c2020-09-07 15:15:37 +0200597#define MSR_AMD64_SEV_ES_ENABLED_BIT 1
Brijesh Singhf742b902022-02-24 10:55:49 -0600598#define MSR_AMD64_SEV_SNP_ENABLED_BIT 2
Tom Lendacky1958b5f2017-10-20 09:30:54 -0500599#define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)
Joerg Roedelb57de6c2020-09-07 15:15:37 +0200600#define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT)
Brijesh Singhf742b902022-02-24 10:55:49 -0600601#define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT)
Stephane Eranian4f8a6b12007-10-19 20:35:03 +0200602
Nikunj A Dadhania8c29f012023-01-18 11:49:43 +0530603/* SNP feature bits enabled by the hypervisor */
604#define MSR_AMD64_SNP_VTOM BIT_ULL(3)
605#define MSR_AMD64_SNP_REFLECT_VC BIT_ULL(4)
606#define MSR_AMD64_SNP_RESTRICTED_INJ BIT_ULL(5)
607#define MSR_AMD64_SNP_ALT_INJ BIT_ULL(6)
608#define MSR_AMD64_SNP_DEBUG_SWAP BIT_ULL(7)
609#define MSR_AMD64_SNP_PREVENT_HOST_IBS BIT_ULL(8)
610#define MSR_AMD64_SNP_BTB_ISOLATION BIT_ULL(9)
611#define MSR_AMD64_SNP_VMPL_SSS BIT_ULL(10)
612#define MSR_AMD64_SNP_SECURE_TSC BIT_ULL(11)
613#define MSR_AMD64_SNP_VMGEXIT_PARAM BIT_ULL(12)
614#define MSR_AMD64_SNP_IBS_VIRT BIT_ULL(14)
615#define MSR_AMD64_SNP_VMSA_REG_PROTECTION BIT_ULL(16)
616#define MSR_AMD64_SNP_SMT_PROTECTION BIT_ULL(17)
617
618/* SNP feature bits reserved for future use. */
619#define MSR_AMD64_SNP_RESERVED_BIT13 BIT_ULL(13)
620#define MSR_AMD64_SNP_RESERVED_BIT15 BIT_ULL(15)
621#define MSR_AMD64_SNP_RESERVED_MASK GENMASK_ULL(63, 18)
622
Tom Lendacky11fb0682018-05-17 17:09:18 +0200623#define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f
624
Huang Rui89aa94b2021-12-24 09:04:56 +0800625/* AMD Collaborative Processor Performance Control MSRs */
626#define MSR_AMD_CPPC_CAP1 0xc00102b0
627#define MSR_AMD_CPPC_ENABLE 0xc00102b1
628#define MSR_AMD_CPPC_CAP2 0xc00102b2
629#define MSR_AMD_CPPC_REQ 0xc00102b3
630#define MSR_AMD_CPPC_STATUS 0xc00102b4
631
632#define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff)
633#define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff)
634#define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff)
635#define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff)
636
637#define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0)
638#define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8)
639#define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16)
640#define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24)
641
Sandipan Das089be162022-04-21 11:16:54 +0530642/* AMD Performance Counter Global Status and Control MSRs */
643#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300
644#define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301
645#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302
646
Sandipan Dasca5b7c02022-08-11 17:59:54 +0530647/* AMD Last Branch Record MSRs */
648#define MSR_AMD64_LBR_SELECT 0xc000010e
649
Borislav Petkovdeedec02023-10-12 20:01:59 +0200650/* Zen4 */
651#define MSR_ZEN4_BP_CFG 0xc001102e
Borislav Petkov (AMD)f454b182023-10-07 12:57:02 +0200652#define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5
Huang Ruiaaf24882016-01-29 16:29:57 +0800653
Borislav Petkovdeedec02023-10-12 20:01:59 +0200654/* Fam 19h MSRs */
655#define MSR_F19H_UMC_PERF_CTL 0xc0010800
656#define MSR_F19H_UMC_PERF_CTR 0xc0010801
Jacob Shinc43ca502013-04-19 16:34:28 -0500657
Borislav Petkovdeedec02023-10-12 20:01:59 +0200658/* Zen 2 */
659#define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3
660#define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1)
661
662/* Fam 17h MSRs */
663#define MSR_F17H_IRPERF 0xc00000e9
Peter Zijlstrad7caac92022-06-14 23:16:04 +0200664
Jacob Shinc43ca502013-04-19 16:34:28 -0500665/* Fam 16h MSRs */
666#define MSR_F16H_L2I_PERF_CTL 0xc0010230
667#define MSR_F16H_L2I_PERF_CTR 0xc0010231
Jacob Shind6d55f02014-05-29 17:26:50 +0200668#define MSR_F16H_DR1_ADDR_MASK 0xc0011019
669#define MSR_F16H_DR2_ADDR_MASK 0xc001101a
670#define MSR_F16H_DR3_ADDR_MASK 0xc001101b
671#define MSR_F16H_DR0_ADDR_MASK 0xc0011027
Jacob Shinc43ca502013-04-19 16:34:28 -0500672
Robert Richterda169f52010-09-24 15:54:43 +0200673/* Fam 15h MSRs */
Borislav Petkov99e40202020-06-21 12:41:53 +0200674#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
675#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
Robert Richterda169f52010-09-24 15:54:43 +0200676#define MSR_F15H_PERF_CTL 0xc0010200
Janakarajan Natarajane84b7112018-02-05 13:24:51 -0600677#define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL
678#define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2)
679#define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4)
680#define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6)
681#define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8)
682#define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10)
683
Robert Richterda169f52010-09-24 15:54:43 +0200684#define MSR_F15H_PERF_CTR 0xc0010201
Janakarajan Natarajane84b7112018-02-05 13:24:51 -0600685#define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR
686#define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2)
687#define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4)
688#define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6)
689#define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8)
690#define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10)
691
Jacob Shine2595142013-02-06 11:26:29 -0600692#define MSR_F15H_NB_PERF_CTL 0xc0010240
693#define MSR_F15H_NB_PERF_CTR 0xc0010241
Huang Rui8a224262016-01-29 16:29:56 +0800694#define MSR_F15H_PTSC 0xc0010280
Borislav Petkovae8b7872015-11-23 11:12:23 +0100695#define MSR_F15H_IC_CFG 0xc0011021
Eduardo Habkost0e1b8692018-12-17 22:34:18 -0200696#define MSR_F15H_EX_CFG 0xc001102c
Robert Richterda169f52010-09-24 15:54:43 +0200697
Yinghai Lu2274c332008-01-30 13:33:18 +0100698/* Fam 10h MSRs */
699#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
700#define FAM10H_MMIO_CONF_ENABLE (1<<0)
701#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
702#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
Jan Beulich37db6c82010-11-16 08:25:08 +0000703#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
Yinghai Lu2274c332008-01-30 13:33:18 +0100704#define FAM10H_MMIO_CONF_BASE_SHIFT 20
Andreas Herrmann9d260eb2009-12-16 15:43:55 +0100705#define MSR_FAM10H_NODE_ID 0xc001100c
Yinghai Lu2274c332008-01-30 13:33:18 +0100706
Stephane Eranian4f8a6b12007-10-19 20:35:03 +0200707/* K8 MSRs */
708#define MSR_K8_TOP_MEM1 0xc001001a
709#define MSR_K8_TOP_MEM2 0xc001001d
Brijesh Singh059e5c32021-04-27 06:16:36 -0500710#define MSR_AMD64_SYSCFG 0xc0010010
711#define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23
712#define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT)
Thomas Gleixneraa83f3f2008-06-09 17:11:13 +0200713#define MSR_K8_INT_PENDING_MSG 0xc0010055
714/* C1E active bits in int pending message */
715#define K8_INTP_C1E_ACTIVE_MASK 0x18000000
Andi Kleen8346ea12008-03-12 03:53:32 +0100716#define MSR_K8_TSEG_ADDR 0xc0010112
Paolo Bonzini3afb1122015-09-18 17:33:04 +0200717#define MSR_K8_TSEG_MASK 0xc0010113
Stephane Eranian4f8a6b12007-10-19 20:35:03 +0200718#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
719#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
720#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
721
722/* K7 MSRs */
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200723#define MSR_K7_EVNTSEL0 0xc0010000
724#define MSR_K7_PERFCTR0 0xc0010004
725#define MSR_K7_EVNTSEL1 0xc0010001
726#define MSR_K7_PERFCTR1 0xc0010005
727#define MSR_K7_EVNTSEL2 0xc0010002
728#define MSR_K7_PERFCTR2 0xc0010006
729#define MSR_K7_EVNTSEL3 0xc0010003
730#define MSR_K7_PERFCTR3 0xc0010007
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200731#define MSR_K7_CLK_CTL 0xc001001b
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200732#define MSR_K7_HWCR 0xc0010015
Tom Lendacky18c71ce2017-12-04 10:57:23 -0600733#define MSR_K7_HWCR_SMMLOCK_BIT 0
734#define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT)
Kim Phillips21b5ee52020-02-19 18:52:43 +0100735#define MSR_K7_HWCR_IRPERF_EN_BIT 30
736#define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT)
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200737#define MSR_K7_FID_VID_CTL 0xc0010041
738#define MSR_K7_FID_VID_STATUS 0xc0010042
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200739
740/* K6 MSRs */
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200741#define MSR_K6_WHCR 0xc0000082
742#define MSR_K6_UWCCR 0xc0000085
743#define MSR_K6_EPMR 0xc0000086
744#define MSR_K6_PSOR 0xc0000087
745#define MSR_K6_PFIR 0xc0000088
746
747/* Centaur-Hauls/IDT defined MSRs. */
748#define MSR_IDT_FCR1 0x00000107
749#define MSR_IDT_FCR2 0x00000108
750#define MSR_IDT_FCR3 0x00000109
751#define MSR_IDT_FCR4 0x0000010a
752
753#define MSR_IDT_MCR0 0x00000110
754#define MSR_IDT_MCR1 0x00000111
755#define MSR_IDT_MCR2 0x00000112
756#define MSR_IDT_MCR3 0x00000113
757#define MSR_IDT_MCR4 0x00000114
758#define MSR_IDT_MCR5 0x00000115
759#define MSR_IDT_MCR6 0x00000116
760#define MSR_IDT_MCR7 0x00000117
761#define MSR_IDT_MCR_CTRL 0x00000120
762
763/* VIA Cyrix defined MSRs*/
764#define MSR_VIA_FCR 0x00001107
765#define MSR_VIA_LONGHAUL 0x0000110a
766#define MSR_VIA_RNG 0x0000110b
767#define MSR_VIA_BCR2 0x00001147
768
769/* Transmeta defined MSRs */
770#define MSR_TMTA_LONGRUN_CTRL 0x80868010
771#define MSR_TMTA_LONGRUN_FLAGS 0x80868011
772#define MSR_TMTA_LRTI_READOUT 0x80868018
773#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
774
775/* Intel defined MSRs. */
776#define MSR_IA32_P5_MC_ADDR 0x00000000
777#define MSR_IA32_P5_MC_TYPE 0x00000001
778#define MSR_IA32_TSC 0x00000010
779#define MSR_IA32_PLATFORM_ID 0x00000017
780#define MSR_IA32_EBL_CR_POWERON 0x0000002a
Jes Sorensenb9a52c42010-09-09 12:06:45 +0200781#define MSR_EBC_FREQUENCY_ID 0x0000002c
Len Brown1ed51012013-02-10 17:19:24 -0500782#define MSR_SMI_COUNT 0x00000034
Sean Christopherson32ad73d2019-12-20 20:44:55 -0800783
784/* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */
785#define MSR_IA32_FEAT_CTL 0x0000003a
786#define FEAT_CTL_LOCKED BIT(0)
787#define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1)
788#define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2)
Sean Christophersond205e0f2020-11-13 00:01:15 +0200789#define FEAT_CTL_SGX_LC_ENABLED BIT(17)
Sean Christophersone7b63852020-11-13 00:01:14 +0200790#define FEAT_CTL_SGX_ENABLED BIT(18)
Sean Christopherson32ad73d2019-12-20 20:44:55 -0800791#define FEAT_CTL_LMCE_ENABLED BIT(20)
792
Will Auldba904632012-11-29 12:42:50 -0800793#define MSR_IA32_TSC_ADJUST 0x0000003b
Liu, Jinsongda8999d2014-02-24 10:55:46 +0000794#define MSR_IA32_BNDCFGS 0x00000d90
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200795
Jim Mattson45316622017-05-23 11:52:54 -0700796#define MSR_IA32_BNDCFGS_RSVD 0x00000ffc
797
Chang S. Baedae1bd582021-10-21 15:55:17 -0700798#define MSR_IA32_XFD 0x000001c4
799#define MSR_IA32_XFD_ERR 0x000001c5
Fenghua Yu6229ad22014-05-29 11:12:30 -0700800#define MSR_IA32_XSS 0x00000da0
801
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200802#define MSR_IA32_APICBASE 0x0000001b
803#define MSR_IA32_APICBASE_BSP (1<<8)
804#define MSR_IA32_APICBASE_ENABLE (1<<11)
805#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
806
807#define MSR_IA32_UCODE_WRITE 0x00000079
808#define MSR_IA32_UCODE_REV 0x0000008b
809
Sean Christophersond205e0f2020-11-13 00:01:15 +0200810/* Intel SGX Launch Enclave Public Key Hash MSRs */
811#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
812#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
813#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
814#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
815
Eugene Korenevskye9ac0332014-12-11 08:53:27 +0300816#define MSR_IA32_SMM_MONITOR_CTL 0x0000009b
817#define MSR_IA32_SMBASE 0x0000009e
818
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200819#define MSR_IA32_PERF_STATUS 0x00000198
820#define MSR_IA32_PERF_CTL 0x00000199
Srinidhi Kasagare7ddf4b2014-12-19 23:13:51 +0530821#define INTEL_PERF_CTL_MASK 0xffff
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200822
Stephane Eranianada54342022-03-22 15:15:07 -0700823/* AMD Branch Sampling configuration */
824#define MSR_AMD_DBG_EXTN_CFG 0xc000010f
825#define MSR_AMD_SAMP_BR_FROM 0xc0010300
826
Sandipan Dasca5b7c02022-08-11 17:59:54 +0530827#define DBG_EXTN_CFG_LBRV2EN BIT_ULL(6)
828
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200829#define MSR_IA32_MPERF 0x000000e7
830#define MSR_IA32_APERF 0x000000e8
831
832#define MSR_IA32_THERM_CONTROL 0x0000019a
833#define MSR_IA32_THERM_INTERRUPT 0x0000019b
Thomas Gleixnerba2d0f22009-04-08 12:31:24 +0200834
Fenghua Yu9792db62010-07-29 17:13:42 -0700835#define THERM_INT_HIGH_ENABLE (1 << 0)
836#define THERM_INT_LOW_ENABLE (1 << 1)
837#define THERM_INT_PLN_ENABLE (1 << 24)
Thomas Gleixnerba2d0f22009-04-08 12:31:24 +0200838
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200839#define MSR_IA32_THERM_STATUS 0x0000019c
Thomas Gleixnerba2d0f22009-04-08 12:31:24 +0200840
841#define THERM_STATUS_PROCHOT (1 << 0)
Fenghua Yu9792db62010-07-29 17:13:42 -0700842#define THERM_STATUS_POWER_LIMIT (1 << 10)
Thomas Gleixnerba2d0f22009-04-08 12:31:24 +0200843
Bartlomiej Zolnierkiewiczf3a08672009-07-29 00:04:59 +0200844#define MSR_THERM2_CTL 0x0000019d
845
846#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
847
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200848#define MSR_IA32_MISC_ENABLE 0x000001a0
849
Carsten Emdea321ced2010-05-24 14:33:41 -0700850#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
851
Len Brown98af7452017-01-21 01:15:09 -0500852#define MSR_MISC_FEATURE_CONTROL 0x000001a4
Dirk Brandewie2f86dc42014-11-06 09:40:47 -0800853#define MSR_MISC_PWR_MGMT 0x000001aa
854
Venkatesh Pallipadi23016bf2010-06-03 23:22:28 -0400855#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
Len Brownd0117a02017-02-25 18:18:22 -0500856#define ENERGY_PERF_BIAS_PERFORMANCE 0
857#define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4
858#define ENERGY_PERF_BIAS_NORMAL 6
Srinivas Pandruvada7420ae32022-10-27 15:00:56 -0700859#define ENERGY_PERF_BIAS_NORMAL_POWERSAVE 7
Len Brownd0117a02017-02-25 18:18:22 -0500860#define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8
861#define ENERGY_PERF_BIAS_POWERSAVE 15
Venkatesh Pallipadi23016bf2010-06-03 23:22:28 -0400862
Fenghua Yu9792db62010-07-29 17:13:42 -0700863#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
864
865#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
866#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
Ricardo Neri7b8f40b32022-01-27 11:34:49 -0800867#define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26)
Fenghua Yu9792db62010-07-29 17:13:42 -0700868
869#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
870
871#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
872#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
873#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
Ricardo Neri7b8f40b32022-01-27 11:34:49 -0800874#define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25)
Fenghua Yu9792db62010-07-29 17:13:42 -0700875
R, Durgadoss9e76a972011-01-03 17:22:04 +0530876/* Thermal Thresholds Support */
877#define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
878#define THERM_SHIFT_THRESHOLD0 8
879#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
880#define THERM_INT_THRESHOLD1_ENABLE (1 << 23)
881#define THERM_SHIFT_THRESHOLD1 16
882#define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
883#define THERM_STATUS_THRESHOLD0 (1 << 6)
884#define THERM_LOG_THRESHOLD0 (1 << 7)
885#define THERM_STATUS_THRESHOLD1 (1 << 8)
886#define THERM_LOG_THRESHOLD1 (1 << 9)
887
H. Peter Anvinbdf21a42009-01-21 15:01:56 -0800888/* MISC_ENABLE bits: architectural */
H. Peter Anvin0b131be2014-03-13 15:40:52 -0700889#define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0
890#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT)
891#define MSR_IA32_MISC_ENABLE_TCC_BIT 1
892#define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT)
893#define MSR_IA32_MISC_ENABLE_EMON_BIT 7
894#define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT)
895#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11
896#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT)
897#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12
898#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT)
899#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16
900#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT)
901#define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18
902#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT)
903#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22
Andres Freundc45f7732014-05-09 03:29:17 +0200904#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT)
H. Peter Anvin0b131be2014-03-13 15:40:52 -0700905#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23
906#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT)
907#define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34
908#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT)
H. Peter Anvinbdf21a42009-01-21 15:01:56 -0800909
910/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
H. Peter Anvin0b131be2014-03-13 15:40:52 -0700911#define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2
912#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT)
913#define MSR_IA32_MISC_ENABLE_TM1_BIT 3
914#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT)
915#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4
916#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT)
917#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6
918#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT)
919#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8
920#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT)
921#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9
922#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
923#define MSR_IA32_MISC_ENABLE_FERR_BIT 10
924#define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT)
925#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10
926#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT)
927#define MSR_IA32_MISC_ENABLE_TM2_BIT 13
928#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT)
929#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19
930#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT)
931#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20
932#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT)
933#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24
934#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT)
935#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37
936#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT)
937#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38
938#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT)
939#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
940#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
H. Peter Anvinbdf21a42009-01-21 15:01:56 -0800941
Kyle Hueyab6d9462017-03-20 01:16:19 -0700942/* MISC_FEATURES_ENABLES non-architectural features */
943#define MSR_MISC_FEATURES_ENABLES 0x00000140
Grzegorz Andrejczukae47eda2017-01-20 14:22:33 +0100944
Kyle Hueye9ea1e72017-03-20 01:16:26 -0700945#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0
946#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT)
Kyle Hueyab6d9462017-03-20 01:16:19 -0700947#define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1
Grzegorz Andrejczukae47eda2017-01-20 14:22:33 +0100948
Suresh Siddha279f1462012-10-22 14:37:58 -0700949#define MSR_IA32_TSC_DEADLINE 0x000006E0
950
Peter Zijlstra (Intel)52f64902019-03-05 22:23:17 +0100951
952#define MSR_TSX_FORCE_ABORT 0x0000010F
953
954#define MSR_TFA_RTM_FORCE_ABORT_BIT 0
955#define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT)
Pawan Gupta13489242021-06-14 14:12:22 -0700956#define MSR_TFA_TSX_CPUID_CLEAR_BIT 1
957#define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT)
958#define MSR_TFA_SDV_ENABLE_RTM_BIT 2
959#define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT)
Peter Zijlstra (Intel)52f64902019-03-05 22:23:17 +0100960
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +0200961/* P4/Xeon+ specific */
962#define MSR_IA32_MCG_EAX 0x00000180
963#define MSR_IA32_MCG_EBX 0x00000181
964#define MSR_IA32_MCG_ECX 0x00000182
965#define MSR_IA32_MCG_EDX 0x00000183
966#define MSR_IA32_MCG_ESI 0x00000184
967#define MSR_IA32_MCG_EDI 0x00000185
968#define MSR_IA32_MCG_EBP 0x00000186
969#define MSR_IA32_MCG_ESP 0x00000187
970#define MSR_IA32_MCG_EFLAGS 0x00000188
971#define MSR_IA32_MCG_EIP 0x00000189
972#define MSR_IA32_MCG_RESERVED 0x0000018a
973
974/* Pentium IV performance counter MSRs */
975#define MSR_P4_BPU_PERFCTR0 0x00000300
976#define MSR_P4_BPU_PERFCTR1 0x00000301
977#define MSR_P4_BPU_PERFCTR2 0x00000302
978#define MSR_P4_BPU_PERFCTR3 0x00000303
979#define MSR_P4_MS_PERFCTR0 0x00000304
980#define MSR_P4_MS_PERFCTR1 0x00000305
981#define MSR_P4_MS_PERFCTR2 0x00000306
982#define MSR_P4_MS_PERFCTR3 0x00000307
983#define MSR_P4_FLAME_PERFCTR0 0x00000308
984#define MSR_P4_FLAME_PERFCTR1 0x00000309
985#define MSR_P4_FLAME_PERFCTR2 0x0000030a
986#define MSR_P4_FLAME_PERFCTR3 0x0000030b
987#define MSR_P4_IQ_PERFCTR0 0x0000030c
988#define MSR_P4_IQ_PERFCTR1 0x0000030d
989#define MSR_P4_IQ_PERFCTR2 0x0000030e
990#define MSR_P4_IQ_PERFCTR3 0x0000030f
991#define MSR_P4_IQ_PERFCTR4 0x00000310
992#define MSR_P4_IQ_PERFCTR5 0x00000311
993#define MSR_P4_BPU_CCCR0 0x00000360
994#define MSR_P4_BPU_CCCR1 0x00000361
995#define MSR_P4_BPU_CCCR2 0x00000362
996#define MSR_P4_BPU_CCCR3 0x00000363
997#define MSR_P4_MS_CCCR0 0x00000364
998#define MSR_P4_MS_CCCR1 0x00000365
999#define MSR_P4_MS_CCCR2 0x00000366
1000#define MSR_P4_MS_CCCR3 0x00000367
1001#define MSR_P4_FLAME_CCCR0 0x00000368
1002#define MSR_P4_FLAME_CCCR1 0x00000369
1003#define MSR_P4_FLAME_CCCR2 0x0000036a
1004#define MSR_P4_FLAME_CCCR3 0x0000036b
1005#define MSR_P4_IQ_CCCR0 0x0000036c
1006#define MSR_P4_IQ_CCCR1 0x0000036d
1007#define MSR_P4_IQ_CCCR2 0x0000036e
1008#define MSR_P4_IQ_CCCR3 0x0000036f
1009#define MSR_P4_IQ_CCCR4 0x00000370
1010#define MSR_P4_IQ_CCCR5 0x00000371
1011#define MSR_P4_ALF_ESCR0 0x000003ca
1012#define MSR_P4_ALF_ESCR1 0x000003cb
1013#define MSR_P4_BPU_ESCR0 0x000003b2
1014#define MSR_P4_BPU_ESCR1 0x000003b3
1015#define MSR_P4_BSU_ESCR0 0x000003a0
1016#define MSR_P4_BSU_ESCR1 0x000003a1
1017#define MSR_P4_CRU_ESCR0 0x000003b8
1018#define MSR_P4_CRU_ESCR1 0x000003b9
1019#define MSR_P4_CRU_ESCR2 0x000003cc
1020#define MSR_P4_CRU_ESCR3 0x000003cd
1021#define MSR_P4_CRU_ESCR4 0x000003e0
1022#define MSR_P4_CRU_ESCR5 0x000003e1
1023#define MSR_P4_DAC_ESCR0 0x000003a8
1024#define MSR_P4_DAC_ESCR1 0x000003a9
1025#define MSR_P4_FIRM_ESCR0 0x000003a4
1026#define MSR_P4_FIRM_ESCR1 0x000003a5
1027#define MSR_P4_FLAME_ESCR0 0x000003a6
1028#define MSR_P4_FLAME_ESCR1 0x000003a7
1029#define MSR_P4_FSB_ESCR0 0x000003a2
1030#define MSR_P4_FSB_ESCR1 0x000003a3
1031#define MSR_P4_IQ_ESCR0 0x000003ba
1032#define MSR_P4_IQ_ESCR1 0x000003bb
1033#define MSR_P4_IS_ESCR0 0x000003b4
1034#define MSR_P4_IS_ESCR1 0x000003b5
1035#define MSR_P4_ITLB_ESCR0 0x000003b6
1036#define MSR_P4_ITLB_ESCR1 0x000003b7
1037#define MSR_P4_IX_ESCR0 0x000003c8
1038#define MSR_P4_IX_ESCR1 0x000003c9
1039#define MSR_P4_MOB_ESCR0 0x000003aa
1040#define MSR_P4_MOB_ESCR1 0x000003ab
1041#define MSR_P4_MS_ESCR0 0x000003c0
1042#define MSR_P4_MS_ESCR1 0x000003c1
1043#define MSR_P4_PMH_ESCR0 0x000003ac
1044#define MSR_P4_PMH_ESCR1 0x000003ad
1045#define MSR_P4_RAT_ESCR0 0x000003bc
1046#define MSR_P4_RAT_ESCR1 0x000003bd
1047#define MSR_P4_SAAT_ESCR0 0x000003ae
1048#define MSR_P4_SAAT_ESCR1 0x000003af
1049#define MSR_P4_SSU_ESCR0 0x000003be
1050#define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
1051
1052#define MSR_P4_TBPU_ESCR0 0x000003c2
1053#define MSR_P4_TBPU_ESCR1 0x000003c3
1054#define MSR_P4_TC_ESCR0 0x000003c4
1055#define MSR_P4_TC_ESCR1 0x000003c5
1056#define MSR_P4_U2L_ESCR0 0x000003b0
1057#define MSR_P4_U2L_ESCR1 0x000003b1
1058
Lin Mingcb7d6b52010-03-18 18:33:12 +08001059#define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
1060
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +02001061/* Intel Core-based CPU performance counters */
1062#define MSR_CORE_PERF_FIXED_CTR0 0x00000309
1063#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
1064#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
Kan Liang7b2c05a2020-07-23 10:11:11 -07001065#define MSR_CORE_PERF_FIXED_CTR3 0x0000030c
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +02001066#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
1067#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
1068#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
1069#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
1070
Kan Liang59a854e2020-07-23 10:11:13 -07001071#define MSR_PERF_METRICS 0x00000329
1072
Luwei Kang8479e042019-02-18 19:26:07 -05001073/* PERF_GLOBAL_OVF_CTL bits */
1074#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55
1075#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT)
Luwei Kangc715eb92019-02-18 19:26:08 -05001076#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62
1077#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT)
1078#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63
1079#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT)
Luwei Kang8479e042019-02-18 19:26:07 -05001080
H. Peter Anvin4bc5aa92007-05-02 19:27:12 +02001081/* Geode defined MSRs */
1082#define MSR_GEODE_BUSCONT_CONF0 0x00001900
1083
Sheng Yang315a6552008-09-09 14:54:53 +08001084/* Intel VT MSRs */
1085#define MSR_IA32_VMX_BASIC 0x00000480
1086#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
1087#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
1088#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
1089#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
1090#define MSR_IA32_VMX_MISC 0x00000485
1091#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
1092#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
1093#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
1094#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
1095#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
1096#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
1097#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03001098#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
1099#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
1100#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
1101#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
Jan Kiszkacae50132014-01-04 18:47:22 +01001102#define MSR_IA32_VMX_VMFUNC 0x00000491
Robert Hoo465932d2022-04-19 23:32:40 +08001103#define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03001104
1105/* VMX_BASIC bits and bitmasks */
1106#define VMX_BASIC_VMCS_SIZE_SHIFT 32
Jan Kiszka3dbcd8d2014-06-16 13:59:40 +02001107#define VMX_BASIC_TRUE_CTLS (1ULL << 55)
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03001108#define VMX_BASIC_64 0x0001000000000000LLU
1109#define VMX_BASIC_MEM_TYPE_SHIFT 50
1110#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
1111#define VMX_BASIC_MEM_TYPE_WB 6LLU
1112#define VMX_BASIC_INOUT 0x0040000000000000LLU
Sheng Yang315a6552008-09-09 14:54:53 +08001113
Borislav Petkov97fa21f2022-11-06 22:24:08 +01001114/* Resctrl MSRs: */
1115/* - Intel: */
1116#define MSR_IA32_L3_QOS_CFG 0xc81
1117#define MSR_IA32_L2_QOS_CFG 0xc82
1118#define MSR_IA32_QM_EVTSEL 0xc8d
1119#define MSR_IA32_QM_CTR 0xc8e
1120#define MSR_IA32_PQR_ASSOC 0xc8f
1121#define MSR_IA32_L3_CBM_BASE 0xc90
1122#define MSR_IA32_L2_CBM_BASE 0xd10
1123#define MSR_IA32_MBA_THRTL_BASE 0xd50
1124
1125/* - AMD: */
1126#define MSR_IA32_MBA_BW_BASE 0xc0000200
Babu Moger5b6fac32023-01-13 09:20:32 -06001127#define MSR_IA32_SMBA_BW_BASE 0xc0000280
Babu Mogerdc2a3e82023-01-13 09:20:35 -06001128#define MSR_IA32_EVT_CFG_BASE 0xc0000400
Borislav Petkov97fa21f2022-11-06 22:24:08 +01001129
Abel Gordon89662e52013-04-18 14:34:55 +03001130/* MSR_IA32_VMX_MISC bits */
Chao Pengf99e3da2018-10-24 16:05:10 +08001131#define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14)
Abel Gordon89662e52013-04-18 14:34:55 +03001132#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
Arthur Chunqi Li7854cbc2013-09-16 16:11:44 +08001133#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
Alexander Graf9962d032008-11-25 20:17:02 +01001134
Paolo Bonzini7deda2c2023-09-21 07:49:40 -04001135/* AMD-V MSRs */
Alexander Graf9962d032008-11-25 20:17:02 +01001136#define MSR_VM_CR 0xc0010114
Alexander Graf0367b432009-06-15 15:21:22 +02001137#define MSR_VM_IGNNE 0xc0010115
Alexander Graf9962d032008-11-25 20:17:02 +01001138#define MSR_VM_HSAVE_PA 0xc0010117
1139
Paolo Bonzini7deda2c2023-09-21 07:49:40 -04001140#define SVM_VM_CR_VALID_MASK 0x001fULL
1141#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
1142#define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
1143
Ricardo Neri7b8f40b32022-01-27 11:34:49 -08001144/* Hardware Feedback Interface */
1145#define MSR_IA32_HW_FEEDBACK_PTR 0x17d0
1146#define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1
1147
Daniel Sneddonb8d1d162022-08-16 16:19:42 -07001148/* x2APIC locked status */
1149#define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD
1150#define LEGACY_XAPIC_DISABLED BIT(0) /*
1151 * x2APIC mode is locked and
1152 * disabling x2APIC will cause
1153 * a #GP
1154 */
1155
H. Peter Anvin1965aae2008-10-22 22:26:29 -07001156#endif /* _ASM_X86_MSR_INDEX_H */