Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 2 | #ifndef _ASM_X86_MSR_INDEX_H |
| 3 | #define _ASM_X86_MSR_INDEX_H |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 4 | |
Thomas Gleixner | d8eabc3 | 2019-02-21 12:36:50 +0100 | [diff] [blame] | 5 | #include <linux/bits.h> |
| 6 | |
Borislav Petkov | 97fa21f | 2022-11-06 22:24:08 +0100 | [diff] [blame] | 7 | /* CPU model specific register (MSR) numbers. */ |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 8 | |
| 9 | /* x86-64 specific MSRs */ |
| 10 | #define MSR_EFER 0xc0000080 /* extended feature register */ |
| 11 | #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ |
| 12 | #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ |
| 13 | #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ |
| 14 | #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ |
| 15 | #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ |
| 16 | #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ |
| 17 | #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ |
Sheng Yang | 5df9740 | 2009-12-16 13:48:04 +0800 | [diff] [blame] | 18 | #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 19 | |
| 20 | /* EFER bits: */ |
| 21 | #define _EFER_SCE 0 /* SYSCALL/SYSRET */ |
| 22 | #define _EFER_LME 8 /* Long mode enable */ |
| 23 | #define _EFER_LMA 10 /* Long mode active (read-only) */ |
| 24 | #define _EFER_NX 11 /* No execute enable */ |
Alexander Graf | 9962d03 | 2008-11-25 20:17:02 +0100 | [diff] [blame] | 25 | #define _EFER_SVME 12 /* Enable virtualization */ |
Joerg Roedel | eec4b14 | 2010-05-05 16:04:44 +0200 | [diff] [blame] | 26 | #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ |
Alexander Graf | d206269 | 2009-02-02 16:23:50 +0100 | [diff] [blame] | 27 | #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ |
Kim Phillips | e7862ed | 2023-01-24 10:33:18 -0600 | [diff] [blame] | 28 | #define _EFER_AUTOIBRS 21 /* Enable Automatic IBRS */ |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 29 | |
| 30 | #define EFER_SCE (1<<_EFER_SCE) |
| 31 | #define EFER_LME (1<<_EFER_LME) |
| 32 | #define EFER_LMA (1<<_EFER_LMA) |
| 33 | #define EFER_NX (1<<_EFER_NX) |
Alexander Graf | 9962d03 | 2008-11-25 20:17:02 +0100 | [diff] [blame] | 34 | #define EFER_SVME (1<<_EFER_SVME) |
Joerg Roedel | eec4b14 | 2010-05-05 16:04:44 +0200 | [diff] [blame] | 35 | #define EFER_LMSLE (1<<_EFER_LMSLE) |
Alexander Graf | d206269 | 2009-02-02 16:23:50 +0100 | [diff] [blame] | 36 | #define EFER_FFXSR (1<<_EFER_FFXSR) |
Kim Phillips | e7862ed | 2023-01-24 10:33:18 -0600 | [diff] [blame] | 37 | #define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 38 | |
| 39 | /* Intel MSRs. Some also available on other CPUs */ |
Tony Luck | 3f5a789 | 2016-11-18 09:48:36 -0800 | [diff] [blame] | 40 | |
Peter Zijlstra (Intel) | 6650cdd | 2020-01-26 12:05:35 -0800 | [diff] [blame] | 41 | #define MSR_TEST_CTRL 0x00000033 |
| 42 | #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 |
| 43 | #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) |
| 44 | |
David Woodhouse | 1e340c6 | 2018-01-25 16:14:12 +0000 | [diff] [blame] | 45 | #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ |
Thomas Gleixner | d8eabc3 | 2019-02-21 12:36:50 +0100 | [diff] [blame] | 46 | #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ |
Tim Chen | 5bfbe3a | 2018-11-25 19:33:46 +0100 | [diff] [blame] | 47 | #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ |
Thomas Gleixner | d8eabc3 | 2019-02-21 12:36:50 +0100 | [diff] [blame] | 48 | #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ |
Konrad Rzeszutek Wilk | 9f65fb2 | 2018-05-09 21:41:38 +0200 | [diff] [blame] | 49 | #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ |
Thomas Gleixner | d8eabc3 | 2019-02-21 12:36:50 +0100 | [diff] [blame] | 50 | #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ |
Pawan Gupta | 4ad3278 | 2022-07-08 13:36:09 -0700 | [diff] [blame] | 51 | #define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */ |
| 52 | #define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT) |
David Woodhouse | 1e340c6 | 2018-01-25 16:14:12 +0000 | [diff] [blame] | 53 | |
Breno Leitao | 0125acd | 2022-11-28 07:31:48 -0800 | [diff] [blame] | 54 | /* A mask for bits which the kernel toggles when controlling mitigations */ |
| 55 | #define SPEC_CTRL_MITIGATIONS_MASK (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \ |
| 56 | | SPEC_CTRL_RRSBA_DIS_S) |
| 57 | |
David Woodhouse | 1e340c6 | 2018-01-25 16:14:12 +0000 | [diff] [blame] | 58 | #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ |
Thomas Gleixner | d8eabc3 | 2019-02-21 12:36:50 +0100 | [diff] [blame] | 59 | #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ |
Borislav Petkov (AMD) | 1b5277c | 2023-06-29 17:43:40 +0200 | [diff] [blame] | 60 | #define PRED_CMD_SBPB BIT(7) /* Selective Branch Prediction Barrier */ |
David Woodhouse | 1e340c6 | 2018-01-25 16:14:12 +0000 | [diff] [blame] | 61 | |
Tony Luck | 3f5a789 | 2016-11-18 09:48:36 -0800 | [diff] [blame] | 62 | #define MSR_PPIN_CTL 0x0000004e |
| 63 | #define MSR_PPIN 0x0000004f |
| 64 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 65 | #define MSR_IA32_PERFCTR0 0x000000c1 |
| 66 | #define MSR_IA32_PERFCTR1 0x000000c2 |
| 67 | #define MSR_FSB_FREQ 0x000000cd |
Len Brown | 5369a21 | 2015-11-12 02:42:32 -0500 | [diff] [blame] | 68 | #define MSR_PLATFORM_INFO 0x000000ce |
Kyle Huey | 90218ac | 2017-03-20 01:16:25 -0700 | [diff] [blame] | 69 | #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 |
| 70 | #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 71 | |
Fenghua Yu | bd688c6 | 2019-06-19 18:33:55 -0700 | [diff] [blame] | 72 | #define MSR_IA32_UMWAIT_CONTROL 0xe1 |
| 73 | #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) |
| 74 | #define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) |
| 75 | /* |
| 76 | * The time field is bit[31:2], but representing a 32bit value with |
| 77 | * bit[1:0] zero. |
| 78 | */ |
| 79 | #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) |
| 80 | |
Peter Zijlstra (Intel) | 6650cdd | 2020-01-26 12:05:35 -0800 | [diff] [blame] | 81 | /* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */ |
| 82 | #define MSR_IA32_CORE_CAPS 0x000000cf |
Tony Luck | db1af12 | 2022-05-06 15:54:00 -0700 | [diff] [blame] | 83 | #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT 2 |
| 84 | #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT) |
Peter Zijlstra (Intel) | 6650cdd | 2020-01-26 12:05:35 -0800 | [diff] [blame] | 85 | #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 |
| 86 | #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT) |
| 87 | |
Len Brown | 40496c8 | 2017-01-07 23:21:18 -0500 | [diff] [blame] | 88 | #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 |
Len Brown | 14796fc | 2011-01-18 20:48:27 -0500 | [diff] [blame] | 89 | #define NHM_C3_AUTO_DEMOTE (1UL << 25) |
| 90 | #define NHM_C1_AUTO_DEMOTE (1UL << 26) |
Len Brown | bfb53cc | 2011-02-16 01:32:48 -0500 | [diff] [blame] | 91 | #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) |
Matt Turner | a00072a | 2018-02-13 11:12:05 -0800 | [diff] [blame] | 92 | #define SNB_C3_AUTO_UNDEMOTE (1UL << 27) |
| 93 | #define SNB_C1_AUTO_UNDEMOTE (1UL << 28) |
Len Brown | 14796fc | 2011-01-18 20:48:27 -0500 | [diff] [blame] | 94 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 95 | #define MSR_MTRRcap 0x000000fe |
David Woodhouse | 1e340c6 | 2018-01-25 16:14:12 +0000 | [diff] [blame] | 96 | |
| 97 | #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a |
Thomas Gleixner | d8eabc3 | 2019-02-21 12:36:50 +0100 | [diff] [blame] | 98 | #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ |
| 99 | #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ |
Peter Zijlstra | 6ad0ad2 | 2022-06-24 13:48:58 +0200 | [diff] [blame] | 100 | #define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */ |
Thomas Gleixner | d8eabc3 | 2019-02-21 12:36:50 +0100 | [diff] [blame] | 101 | #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ |
| 102 | #define ARCH_CAP_SSB_NO BIT(4) /* |
| 103 | * Not susceptible to Speculative Store Bypass |
| 104 | * attack, so no Speculative Store Bypass |
| 105 | * control required. |
| 106 | */ |
Andi Kleen | ed5194c | 2019-01-18 16:50:16 -0800 | [diff] [blame] | 107 | #define ARCH_CAP_MDS_NO BIT(5) /* |
| 108 | * Not susceptible to |
| 109 | * Microarchitectural Data |
| 110 | * Sampling (MDS) vulnerabilities. |
| 111 | */ |
Vineela Tummalapalli | db4d30f | 2019-11-04 12:22:01 +0100 | [diff] [blame] | 112 | #define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* |
| 113 | * The processor is not susceptible to a |
| 114 | * machine check error due to modifying the |
| 115 | * code page size along with either the |
| 116 | * physical address or cache type |
| 117 | * without TLB invalidation. |
| 118 | */ |
Pawan Gupta | c2955f2 | 2019-10-23 10:45:50 +0200 | [diff] [blame] | 119 | #define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ |
Pawan Gupta | 1b42f01 | 2019-10-23 11:30:45 +0200 | [diff] [blame] | 120 | #define ARCH_CAP_TAA_NO BIT(8) /* |
| 121 | * Not susceptible to |
| 122 | * TSX Async Abort (TAA) vulnerabilities. |
| 123 | */ |
Pawan Gupta | 5180218 | 2022-05-19 20:27:08 -0700 | [diff] [blame] | 124 | #define ARCH_CAP_SBDR_SSDP_NO BIT(13) /* |
| 125 | * Not susceptible to SBDR and SSDP |
| 126 | * variants of Processor MMIO stale data |
| 127 | * vulnerabilities. |
| 128 | */ |
| 129 | #define ARCH_CAP_FBSDP_NO BIT(14) /* |
| 130 | * Not susceptible to FBSDP variant of |
| 131 | * Processor MMIO stale data |
| 132 | * vulnerabilities. |
| 133 | */ |
| 134 | #define ARCH_CAP_PSDP_NO BIT(15) /* |
| 135 | * Not susceptible to PSDP variant of |
| 136 | * Processor MMIO stale data |
| 137 | * vulnerabilities. |
| 138 | */ |
| 139 | #define ARCH_CAP_FB_CLEAR BIT(17) /* |
| 140 | * VERW clears CPU fill buffer |
| 141 | * even on MDS_NO CPUs. |
| 142 | */ |
Pawan Gupta | 027bbb8 | 2022-05-19 20:35:15 -0700 | [diff] [blame] | 143 | #define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /* |
| 144 | * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS] |
| 145 | * bit available to control VERW |
| 146 | * behavior. |
| 147 | */ |
Pawan Gupta | 4ad3278 | 2022-07-08 13:36:09 -0700 | [diff] [blame] | 148 | #define ARCH_CAP_RRSBA BIT(19) /* |
| 149 | * Indicates RET may use predictors |
| 150 | * other than the RSB. With eIBRS |
| 151 | * enabled predictions in kernel mode |
| 152 | * are restricted to targets in |
| 153 | * kernel. |
| 154 | */ |
Daniel Sneddon | 2b12993 | 2022-08-02 15:47:01 -0700 | [diff] [blame] | 155 | #define ARCH_CAP_PBRSB_NO BIT(24) /* |
| 156 | * Not susceptible to Post-Barrier |
| 157 | * Return Stack Buffer Predictions. |
| 158 | */ |
Daniel Sneddon | 8974eb5 | 2023-07-12 19:43:11 -0700 | [diff] [blame] | 159 | #define ARCH_CAP_GDS_CTRL BIT(25) /* |
| 160 | * CPU is vulnerable to Gather |
| 161 | * Data Sampling (GDS) and |
| 162 | * has controls for mitigation. |
| 163 | */ |
| 164 | #define ARCH_CAP_GDS_NO BIT(26) /* |
| 165 | * CPU is not vulnerable to Gather |
| 166 | * Data Sampling (GDS). |
| 167 | */ |
David Woodhouse | 1e340c6 | 2018-01-25 16:14:12 +0000 | [diff] [blame] | 168 | |
Daniel Sneddon | b8d1d16 | 2022-08-16 16:19:42 -0700 | [diff] [blame] | 169 | #define ARCH_CAP_XAPIC_DISABLE BIT(21) /* |
| 170 | * IA32_XAPIC_DISABLE_STATUS MSR |
| 171 | * supported |
| 172 | */ |
| 173 | |
Paolo Bonzini | 3fa045b | 2018-07-02 13:03:48 +0200 | [diff] [blame] | 174 | #define MSR_IA32_FLUSH_CMD 0x0000010b |
Thomas Gleixner | d8eabc3 | 2019-02-21 12:36:50 +0100 | [diff] [blame] | 175 | #define L1D_FLUSH BIT(0) /* |
| 176 | * Writeback and invalidate the |
| 177 | * L1 data cache. |
| 178 | */ |
Paolo Bonzini | 3fa045b | 2018-07-02 13:03:48 +0200 | [diff] [blame] | 179 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 180 | #define MSR_IA32_BBL_CR_CTL 0x00000119 |
john cooper | 91c9c3e | 2011-01-21 00:21:00 -0500 | [diff] [blame] | 181 | #define MSR_IA32_BBL_CR_CTL3 0x0000011e |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 182 | |
Pawan Gupta | c2955f2 | 2019-10-23 10:45:50 +0200 | [diff] [blame] | 183 | #define MSR_IA32_TSX_CTRL 0x00000122 |
| 184 | #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ |
| 185 | #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ |
| 186 | |
Mark Gross | 7e5b3c2 | 2020-04-16 17:54:04 +0200 | [diff] [blame] | 187 | #define MSR_IA32_MCU_OPT_CTRL 0x00000123 |
Pawan Gupta | 400331f | 2022-03-10 14:02:09 -0800 | [diff] [blame] | 188 | #define RNGDS_MITG_DIS BIT(0) /* SRBDS support */ |
| 189 | #define RTM_ALLOW BIT(1) /* TSX development mode */ |
Pawan Gupta | 027bbb8 | 2022-05-19 20:35:15 -0700 | [diff] [blame] | 190 | #define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */ |
Daniel Sneddon | 8974eb5 | 2023-07-12 19:43:11 -0700 | [diff] [blame] | 191 | #define GDS_MITG_DIS BIT(4) /* Disable GDS mitigation */ |
| 192 | #define GDS_MITG_LOCKED BIT(5) /* GDS mitigation locked */ |
Mark Gross | 7e5b3c2 | 2020-04-16 17:54:04 +0200 | [diff] [blame] | 193 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 194 | #define MSR_IA32_SYSENTER_CS 0x00000174 |
| 195 | #define MSR_IA32_SYSENTER_ESP 0x00000175 |
| 196 | #define MSR_IA32_SYSENTER_EIP 0x00000176 |
| 197 | |
| 198 | #define MSR_IA32_MCG_CAP 0x00000179 |
| 199 | #define MSR_IA32_MCG_STATUS 0x0000017a |
| 200 | #define MSR_IA32_MCG_CTL 0x0000017b |
Tony Luck | 68299a4 | 2020-10-30 12:04:00 -0700 | [diff] [blame] | 201 | #define MSR_ERROR_CONTROL 0x0000017f |
Ashok Raj | bc12edb | 2015-06-04 18:55:22 +0200 | [diff] [blame] | 202 | #define MSR_IA32_MCG_EXT_CTL 0x000004d0 |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 203 | |
Andi Kleen | a7e3ed1 | 2011-03-03 10:34:47 +0800 | [diff] [blame] | 204 | #define MSR_OFFCORE_RSP_0 0x000001a6 |
| 205 | #define MSR_OFFCORE_RSP_1 0x000001a7 |
Len Brown | c4d3066 | 2015-04-10 00:22:56 -0400 | [diff] [blame] | 206 | #define MSR_TURBO_RATIO_LIMIT 0x000001ad |
| 207 | #define MSR_TURBO_RATIO_LIMIT1 0x000001ae |
| 208 | #define MSR_TURBO_RATIO_LIMIT2 0x000001af |
Andi Kleen | a7e3ed1 | 2011-03-03 10:34:47 +0800 | [diff] [blame] | 209 | |
Kan Liang | 38aaf92 | 2023-01-04 12:13:42 -0800 | [diff] [blame] | 210 | #define MSR_SNOOP_RSP_0 0x00001328 |
| 211 | #define MSR_SNOOP_RSP_1 0x00001329 |
| 212 | |
Stephane Eranian | 225ce53 | 2012-02-09 23:20:52 +0100 | [diff] [blame] | 213 | #define MSR_LBR_SELECT 0x000001c8 |
| 214 | #define MSR_LBR_TOS 0x000001c9 |
Srinivas Pandruvada | ed7bde7 | 2020-06-26 11:34:00 -0700 | [diff] [blame] | 215 | |
| 216 | #define MSR_IA32_POWER_CTL 0x000001fc |
| 217 | #define MSR_IA32_POWER_CTL_BIT_EE 19 |
| 218 | |
Tony Luck | db1af12 | 2022-05-06 15:54:00 -0700 | [diff] [blame] | 219 | /* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */ |
| 220 | #define MSR_INTEGRITY_CAPS 0x000002d9 |
Jithu Joseph | c68e3d4 | 2023-03-21 17:33:54 -0700 | [diff] [blame] | 221 | #define MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT 2 |
| 222 | #define MSR_INTEGRITY_CAPS_ARRAY_BIST BIT(MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT) |
Tony Luck | db1af12 | 2022-05-06 15:54:00 -0700 | [diff] [blame] | 223 | #define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4 |
| 224 | #define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT) |
Jithu Joseph | 97a5e80 | 2023-10-05 12:51:29 -0700 | [diff] [blame] | 225 | #define MSR_INTEGRITY_CAPS_SAF_GEN_MASK GENMASK_ULL(10, 9) |
Tony Luck | db1af12 | 2022-05-06 15:54:00 -0700 | [diff] [blame] | 226 | |
Stephane Eranian | 225ce53 | 2012-02-09 23:20:52 +0100 | [diff] [blame] | 227 | #define MSR_LBR_NHM_FROM 0x00000680 |
| 228 | #define MSR_LBR_NHM_TO 0x000006c0 |
| 229 | #define MSR_LBR_CORE_FROM 0x00000040 |
| 230 | #define MSR_LBR_CORE_TO 0x00000060 |
| 231 | |
Andi Kleen | b83ff1c | 2015-05-10 12:22:41 -0700 | [diff] [blame] | 232 | #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ |
| 233 | #define LBR_INFO_MISPRED BIT_ULL(63) |
| 234 | #define LBR_INFO_IN_TX BIT_ULL(62) |
| 235 | #define LBR_INFO_ABORT BIT_ULL(61) |
Kan Liang | d6a162a | 2020-07-03 05:49:13 -0700 | [diff] [blame] | 236 | #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60) |
Andi Kleen | b83ff1c | 2015-05-10 12:22:41 -0700 | [diff] [blame] | 237 | #define LBR_INFO_CYCLES 0xffff |
Kan Liang | d6a162a | 2020-07-03 05:49:13 -0700 | [diff] [blame] | 238 | #define LBR_INFO_BR_TYPE_OFFSET 56 |
| 239 | #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) |
Kan Liang | 3374491 | 2023-10-25 13:16:23 -0700 | [diff] [blame] | 240 | #define LBR_INFO_BR_CNTR_OFFSET 32 |
| 241 | #define LBR_INFO_BR_CNTR_NUM 4 |
| 242 | #define LBR_INFO_BR_CNTR_BITS 2 |
| 243 | #define LBR_INFO_BR_CNTR_MASK GENMASK_ULL(LBR_INFO_BR_CNTR_BITS - 1, 0) |
| 244 | #define LBR_INFO_BR_CNTR_FULL_MASK GENMASK_ULL(LBR_INFO_BR_CNTR_NUM * LBR_INFO_BR_CNTR_BITS - 1, 0) |
Kan Liang | d6a162a | 2020-07-03 05:49:13 -0700 | [diff] [blame] | 245 | |
| 246 | #define MSR_ARCH_LBR_CTL 0x000014ce |
| 247 | #define ARCH_LBR_CTL_LBREN BIT(0) |
| 248 | #define ARCH_LBR_CTL_CPL_OFFSET 1 |
| 249 | #define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET) |
| 250 | #define ARCH_LBR_CTL_STACK_OFFSET 3 |
| 251 | #define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET) |
| 252 | #define ARCH_LBR_CTL_FILTER_OFFSET 16 |
| 253 | #define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET) |
| 254 | #define MSR_ARCH_LBR_DEPTH 0x000014cf |
| 255 | #define MSR_ARCH_LBR_FROM_0 0x00001500 |
| 256 | #define MSR_ARCH_LBR_TO_0 0x00001600 |
| 257 | #define MSR_ARCH_LBR_INFO_0 0x00001200 |
Andi Kleen | b83ff1c | 2015-05-10 12:22:41 -0700 | [diff] [blame] | 258 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 259 | #define MSR_IA32_PEBS_ENABLE 0x000003f1 |
Kan Liang | c22497f | 2019-04-02 12:45:02 -0700 | [diff] [blame] | 260 | #define MSR_PEBS_DATA_CFG 0x000003f2 |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 261 | #define MSR_IA32_DS_AREA 0x00000600 |
| 262 | #define MSR_IA32_PERF_CAPABILITIES 0x00000345 |
Kan Liang | d0946a8 | 2021-04-12 07:30:44 -0700 | [diff] [blame] | 263 | #define PERF_CAP_METRICS_IDX 15 |
| 264 | #define PERF_CAP_PT_IDX 16 |
| 265 | |
Stephane Eranian | f20093e | 2013-01-24 16:10:32 +0100 | [diff] [blame] | 266 | #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 |
Like Xu | c59a1f1 | 2022-04-11 18:19:36 +0800 | [diff] [blame] | 267 | #define PERF_CAP_PEBS_TRAP BIT_ULL(6) |
| 268 | #define PERF_CAP_ARCH_REG BIT_ULL(7) |
| 269 | #define PERF_CAP_PEBS_FORMAT 0xf00 |
| 270 | #define PERF_CAP_PEBS_BASELINE BIT_ULL(14) |
| 271 | #define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ |
| 272 | PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE) |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 273 | |
Alexander Shishkin | 52ca9ce | 2015-01-30 12:39:52 +0200 | [diff] [blame] | 274 | #define MSR_IA32_RTIT_CTL 0x00000570 |
Chao Peng | 887eda1 | 2018-10-24 16:05:05 +0800 | [diff] [blame] | 275 | #define RTIT_CTL_TRACEEN BIT(0) |
| 276 | #define RTIT_CTL_CYCLEACC BIT(1) |
| 277 | #define RTIT_CTL_OS BIT(2) |
| 278 | #define RTIT_CTL_USR BIT(3) |
| 279 | #define RTIT_CTL_PWR_EVT_EN BIT(4) |
| 280 | #define RTIT_CTL_FUP_ON_PTW BIT(5) |
Luwei Kang | 69843a9 | 2018-10-24 16:05:08 +0800 | [diff] [blame] | 281 | #define RTIT_CTL_FABRIC_EN BIT(6) |
Chao Peng | 887eda1 | 2018-10-24 16:05:05 +0800 | [diff] [blame] | 282 | #define RTIT_CTL_CR3EN BIT(7) |
| 283 | #define RTIT_CTL_TOPA BIT(8) |
| 284 | #define RTIT_CTL_MTC_EN BIT(9) |
| 285 | #define RTIT_CTL_TSC_EN BIT(10) |
| 286 | #define RTIT_CTL_DISRETC BIT(11) |
| 287 | #define RTIT_CTL_PTW_EN BIT(12) |
| 288 | #define RTIT_CTL_BRANCH_EN BIT(13) |
Alexander Shishkin | 28c24de | 2022-01-26 12:48:14 +0200 | [diff] [blame] | 289 | #define RTIT_CTL_EVENT_EN BIT(31) |
Alexander Shishkin | 161a9a3 | 2022-01-26 12:48:15 +0200 | [diff] [blame] | 290 | #define RTIT_CTL_NOTNT BIT_ULL(55) |
Chao Peng | 887eda1 | 2018-10-24 16:05:05 +0800 | [diff] [blame] | 291 | #define RTIT_CTL_MTC_RANGE_OFFSET 14 |
| 292 | #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) |
| 293 | #define RTIT_CTL_CYC_THRESH_OFFSET 19 |
| 294 | #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) |
| 295 | #define RTIT_CTL_PSB_FREQ_OFFSET 24 |
| 296 | #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) |
| 297 | #define RTIT_CTL_ADDR0_OFFSET 32 |
| 298 | #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) |
| 299 | #define RTIT_CTL_ADDR1_OFFSET 36 |
| 300 | #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) |
| 301 | #define RTIT_CTL_ADDR2_OFFSET 40 |
| 302 | #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) |
| 303 | #define RTIT_CTL_ADDR3_OFFSET 44 |
| 304 | #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) |
Alexander Shishkin | 52ca9ce | 2015-01-30 12:39:52 +0200 | [diff] [blame] | 305 | #define MSR_IA32_RTIT_STATUS 0x00000571 |
Chao Peng | 887eda1 | 2018-10-24 16:05:05 +0800 | [diff] [blame] | 306 | #define RTIT_STATUS_FILTEREN BIT(0) |
| 307 | #define RTIT_STATUS_CONTEXTEN BIT(1) |
| 308 | #define RTIT_STATUS_TRIGGEREN BIT(2) |
| 309 | #define RTIT_STATUS_BUFFOVF BIT(3) |
| 310 | #define RTIT_STATUS_ERROR BIT(4) |
| 311 | #define RTIT_STATUS_STOPPED BIT(5) |
Luwei Kang | 69843a9 | 2018-10-24 16:05:08 +0800 | [diff] [blame] | 312 | #define RTIT_STATUS_BYTECNT_OFFSET 32 |
| 313 | #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) |
Alexander Shishkin | f127fa0 | 2016-04-27 18:44:44 +0300 | [diff] [blame] | 314 | #define MSR_IA32_RTIT_ADDR0_A 0x00000580 |
| 315 | #define MSR_IA32_RTIT_ADDR0_B 0x00000581 |
| 316 | #define MSR_IA32_RTIT_ADDR1_A 0x00000582 |
| 317 | #define MSR_IA32_RTIT_ADDR1_B 0x00000583 |
| 318 | #define MSR_IA32_RTIT_ADDR2_A 0x00000584 |
| 319 | #define MSR_IA32_RTIT_ADDR2_B 0x00000585 |
| 320 | #define MSR_IA32_RTIT_ADDR3_A 0x00000586 |
| 321 | #define MSR_IA32_RTIT_ADDR3_B 0x00000587 |
Alexander Shishkin | 52ca9ce | 2015-01-30 12:39:52 +0200 | [diff] [blame] | 322 | #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 |
| 323 | #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 |
| 324 | #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 |
| 325 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 326 | #define MSR_MTRRfix64K_00000 0x00000250 |
| 327 | #define MSR_MTRRfix16K_80000 0x00000258 |
| 328 | #define MSR_MTRRfix16K_A0000 0x00000259 |
| 329 | #define MSR_MTRRfix4K_C0000 0x00000268 |
| 330 | #define MSR_MTRRfix4K_C8000 0x00000269 |
| 331 | #define MSR_MTRRfix4K_D0000 0x0000026a |
| 332 | #define MSR_MTRRfix4K_D8000 0x0000026b |
| 333 | #define MSR_MTRRfix4K_E0000 0x0000026c |
| 334 | #define MSR_MTRRfix4K_E8000 0x0000026d |
| 335 | #define MSR_MTRRfix4K_F0000 0x0000026e |
| 336 | #define MSR_MTRRfix4K_F8000 0x0000026f |
| 337 | #define MSR_MTRRdefType 0x000002ff |
| 338 | |
venkatesh.pallipadi@intel.com | 2e5d9c8 | 2008-03-18 17:00:14 -0700 | [diff] [blame] | 339 | #define MSR_IA32_CR_PAT 0x00000277 |
| 340 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 341 | #define MSR_IA32_DEBUGCTLMSR 0x000001d9 |
| 342 | #define MSR_IA32_LASTBRANCHFROMIP 0x000001db |
| 343 | #define MSR_IA32_LASTBRANCHTOIP 0x000001dc |
| 344 | #define MSR_IA32_LASTINTFROMIP 0x000001dd |
| 345 | #define MSR_IA32_LASTINTTOIP 0x000001de |
| 346 | |
Fenghua Yu | f0f2f9f | 2020-09-15 09:30:10 -0700 | [diff] [blame] | 347 | #define MSR_IA32_PASID 0x00000d93 |
| 348 | #define MSR_IA32_PASID_VALID BIT_ULL(31) |
| 349 | |
Roland McGrath | d2499d8 | 2008-01-30 13:30:54 +0100 | [diff] [blame] | 350 | /* DEBUGCTLMSR bits (others vary by model): */ |
Peter Zijlstra | 7c5ecaf | 2010-03-25 14:51:49 +0100 | [diff] [blame] | 351 | #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ |
Kyle Huey | b9894a2 | 2017-02-14 00:11:03 -0800 | [diff] [blame] | 352 | #define DEBUGCTLMSR_BTF_SHIFT 1 |
Peter Zijlstra | 7c5ecaf | 2010-03-25 14:51:49 +0100 | [diff] [blame] | 353 | #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ |
Fenghua Yu | ebb1064 | 2021-03-22 13:53:24 +0000 | [diff] [blame] | 354 | #define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2) |
Peter Zijlstra | 7c5ecaf | 2010-03-25 14:51:49 +0100 | [diff] [blame] | 355 | #define DEBUGCTLMSR_TR (1UL << 6) |
| 356 | #define DEBUGCTLMSR_BTS (1UL << 7) |
| 357 | #define DEBUGCTLMSR_BTINT (1UL << 8) |
| 358 | #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) |
| 359 | #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) |
| 360 | #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) |
Andi Kleen | af3bdb9 | 2018-08-08 00:12:07 -0700 | [diff] [blame] | 361 | #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) |
Kan Liang | 6089327 | 2017-05-12 07:51:13 -0700 | [diff] [blame] | 362 | #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 |
| 363 | #define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) |
Roland McGrath | d2499d8 | 2008-01-30 13:30:54 +0100 | [diff] [blame] | 364 | |
Andi Kleen | d0dc849 | 2015-09-09 14:53:59 -0700 | [diff] [blame] | 365 | #define MSR_PEBS_FRONTEND 0x000003f7 |
| 366 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 367 | #define MSR_IA32_MC0_CTL 0x00000400 |
| 368 | #define MSR_IA32_MC0_STATUS 0x00000401 |
| 369 | #define MSR_IA32_MC0_ADDR 0x00000402 |
| 370 | #define MSR_IA32_MC0_MISC 0x00000403 |
| 371 | |
Linus Torvalds | 6842d98 | 2012-12-18 12:34:29 -0800 | [diff] [blame] | 372 | /* C-state Residency Counters */ |
| 373 | #define MSR_PKG_C3_RESIDENCY 0x000003f8 |
| 374 | #define MSR_PKG_C6_RESIDENCY 0x000003f9 |
Len Brown | 0539ba11 | 2017-02-10 00:27:20 -0500 | [diff] [blame] | 375 | #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa |
Linus Torvalds | 6842d98 | 2012-12-18 12:34:29 -0800 | [diff] [blame] | 376 | #define MSR_PKG_C7_RESIDENCY 0x000003fa |
| 377 | #define MSR_CORE_C3_RESIDENCY 0x000003fc |
| 378 | #define MSR_CORE_C6_RESIDENCY 0x000003fd |
| 379 | #define MSR_CORE_C7_RESIDENCY 0x000003fe |
Dasaratharaman Chandramouli | fb5d432 | 2015-05-20 09:49:34 -0700 | [diff] [blame] | 380 | #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff |
Linus Torvalds | 6842d98 | 2012-12-18 12:34:29 -0800 | [diff] [blame] | 381 | #define MSR_PKG_C2_RESIDENCY 0x0000060d |
Kristen Carlson Accardi | ca58710 | 2012-11-21 05:22:43 -0800 | [diff] [blame] | 382 | #define MSR_PKG_C8_RESIDENCY 0x00000630 |
| 383 | #define MSR_PKG_C9_RESIDENCY 0x00000631 |
| 384 | #define MSR_PKG_C10_RESIDENCY 0x00000632 |
Linus Torvalds | 6842d98 | 2012-12-18 12:34:29 -0800 | [diff] [blame] | 385 | |
Len Brown | 5a63426 | 2016-04-06 17:15:55 -0400 | [diff] [blame] | 386 | /* Interrupt Response Limit */ |
| 387 | #define MSR_PKGC3_IRTL 0x0000060a |
| 388 | #define MSR_PKGC6_IRTL 0x0000060b |
| 389 | #define MSR_PKGC7_IRTL 0x0000060c |
| 390 | #define MSR_PKGC8_IRTL 0x00000633 |
| 391 | #define MSR_PKGC9_IRTL 0x00000634 |
| 392 | #define MSR_PKGC10_IRTL 0x00000635 |
| 393 | |
Linus Torvalds | 6842d98 | 2012-12-18 12:34:29 -0800 | [diff] [blame] | 394 | /* Run Time Average Power Limiting (RAPL) Interface */ |
| 395 | |
Sumeet Pawnikar | f52ba93 | 2021-08-20 17:42:43 +0530 | [diff] [blame] | 396 | #define MSR_VR_CURRENT_CONFIG 0x00000601 |
Linus Torvalds | 6842d98 | 2012-12-18 12:34:29 -0800 | [diff] [blame] | 397 | #define MSR_RAPL_POWER_UNIT 0x00000606 |
| 398 | |
| 399 | #define MSR_PKG_POWER_LIMIT 0x00000610 |
| 400 | #define MSR_PKG_ENERGY_STATUS 0x00000611 |
| 401 | #define MSR_PKG_PERF_STATUS 0x00000613 |
| 402 | #define MSR_PKG_POWER_INFO 0x00000614 |
| 403 | |
| 404 | #define MSR_DRAM_POWER_LIMIT 0x00000618 |
| 405 | #define MSR_DRAM_ENERGY_STATUS 0x00000619 |
| 406 | #define MSR_DRAM_PERF_STATUS 0x0000061b |
| 407 | #define MSR_DRAM_POWER_INFO 0x0000061c |
| 408 | |
| 409 | #define MSR_PP0_POWER_LIMIT 0x00000638 |
| 410 | #define MSR_PP0_ENERGY_STATUS 0x00000639 |
| 411 | #define MSR_PP0_POLICY 0x0000063a |
| 412 | #define MSR_PP0_PERF_STATUS 0x0000063b |
| 413 | |
| 414 | #define MSR_PP1_POWER_LIMIT 0x00000640 |
| 415 | #define MSR_PP1_ENERGY_STATUS 0x00000641 |
| 416 | #define MSR_PP1_POLICY 0x00000642 |
| 417 | |
Stephane Eranian | 5cde265 | 2020-05-27 15:46:59 -0700 | [diff] [blame] | 418 | #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 |
Victor Ding | 43756a2 | 2020-10-27 07:23:56 +0000 | [diff] [blame] | 419 | #define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a |
Victor Ding | 298ed2b | 2020-10-27 07:23:54 +0000 | [diff] [blame] | 420 | #define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b |
Stephane Eranian | 5cde265 | 2020-05-27 15:46:59 -0700 | [diff] [blame] | 421 | |
Vladimir Zapolskiy | 4a6772f | 2016-03-26 20:47:00 +0200 | [diff] [blame] | 422 | /* Config TDP MSRs */ |
Rafael J. Wysocki | 82bb70c | 2015-08-24 23:10:02 +0200 | [diff] [blame] | 423 | #define MSR_CONFIG_TDP_NOMINAL 0x00000648 |
| 424 | #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 |
| 425 | #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A |
| 426 | #define MSR_CONFIG_TDP_CONTROL 0x0000064B |
| 427 | #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C |
| 428 | |
Srinivas Pandruvada | dcee75b | 2016-04-17 15:03:00 -0700 | [diff] [blame] | 429 | #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D |
Len Brown | 4af184e | 2022-05-31 17:29:13 -1000 | [diff] [blame] | 430 | #define MSR_SECONDARY_TURBO_RATIO_LIMIT 0x00000650 |
Srinivas Pandruvada | dcee75b | 2016-04-17 15:03:00 -0700 | [diff] [blame] | 431 | |
Len Brown | 0b2bb69 | 2015-03-26 00:50:30 -0400 | [diff] [blame] | 432 | #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 |
| 433 | #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 |
| 434 | #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A |
| 435 | #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B |
| 436 | |
Len Brown | 144b44b | 2013-11-09 00:30:16 -0500 | [diff] [blame] | 437 | #define MSR_CORE_C1_RES 0x00000660 |
Len Brown | 0539ba11 | 2017-02-10 00:27:20 -0500 | [diff] [blame] | 438 | #define MSR_MODULE_C6_RES_MS 0x00000664 |
Len Brown | 144b44b | 2013-11-09 00:30:16 -0500 | [diff] [blame] | 439 | |
Len Brown | 8c058d53 | 2014-07-31 15:21:24 -0400 | [diff] [blame] | 440 | #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 |
| 441 | #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 |
| 442 | |
Len Brown | 8a34fd0 | 2017-01-12 23:22:28 -0500 | [diff] [blame] | 443 | #define MSR_ATOM_CORE_RATIOS 0x0000066a |
| 444 | #define MSR_ATOM_CORE_VIDS 0x0000066b |
| 445 | #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c |
| 446 | #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d |
| 447 | |
Len Brown | 3a9a941 | 2014-08-15 02:39:52 -0400 | [diff] [blame] | 448 | #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 |
| 449 | #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 |
| 450 | #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 |
| 451 | |
Peter Zijlstra | 991625f | 2022-03-08 16:30:35 +0100 | [diff] [blame] | 452 | /* Control-flow Enforcement Technology MSRs */ |
| 453 | #define MSR_IA32_U_CET 0x000006a0 /* user mode cet */ |
| 454 | #define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */ |
| 455 | #define CET_SHSTK_EN BIT_ULL(0) |
| 456 | #define CET_WRSS_EN BIT_ULL(1) |
| 457 | #define CET_ENDBR_EN BIT_ULL(2) |
| 458 | #define CET_LEG_IW_EN BIT_ULL(3) |
| 459 | #define CET_NO_TRACK_EN BIT_ULL(4) |
| 460 | #define CET_SUPPRESS_DISABLE BIT_ULL(5) |
| 461 | #define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9)) |
| 462 | #define CET_SUPPRESS BIT_ULL(10) |
| 463 | #define CET_WAIT_ENDBR BIT_ULL(11) |
| 464 | |
| 465 | #define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */ |
| 466 | #define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */ |
| 467 | #define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */ |
| 468 | #define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */ |
| 469 | #define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */ |
| 470 | |
Dirk Brandewie | 2f86dc4 | 2014-11-06 09:40:47 -0800 | [diff] [blame] | 471 | /* Hardware P state interface */ |
| 472 | #define MSR_PPERF 0x0000064e |
| 473 | #define MSR_PERF_LIMIT_REASONS 0x0000064f |
| 474 | #define MSR_PM_ENABLE 0x00000770 |
| 475 | #define MSR_HWP_CAPABILITIES 0x00000771 |
| 476 | #define MSR_HWP_REQUEST_PKG 0x00000772 |
| 477 | #define MSR_HWP_INTERRUPT 0x00000773 |
| 478 | #define MSR_HWP_REQUEST 0x00000774 |
| 479 | #define MSR_HWP_STATUS 0x00000777 |
| 480 | |
| 481 | /* CPUID.6.EAX */ |
| 482 | #define HWP_BASE_BIT (1<<7) |
| 483 | #define HWP_NOTIFICATIONS_BIT (1<<8) |
| 484 | #define HWP_ACTIVITY_WINDOW_BIT (1<<9) |
| 485 | #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) |
| 486 | #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) |
| 487 | |
| 488 | /* IA32_HWP_CAPABILITIES */ |
Len Brown | 670e27d | 2015-12-01 01:36:39 -0500 | [diff] [blame] | 489 | #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) |
| 490 | #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) |
| 491 | #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) |
| 492 | #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) |
Dirk Brandewie | 2f86dc4 | 2014-11-06 09:40:47 -0800 | [diff] [blame] | 493 | |
| 494 | /* IA32_HWP_REQUEST */ |
| 495 | #define HWP_MIN_PERF(x) (x & 0xff) |
| 496 | #define HWP_MAX_PERF(x) ((x & 0xff) << 8) |
| 497 | #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) |
Len Brown | 2fc49cb | 2017-04-29 00:11:46 -0400 | [diff] [blame] | 498 | #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) |
Len Brown | 8d84e90 | 2017-02-25 11:56:29 -0500 | [diff] [blame] | 499 | #define HWP_EPP_PERFORMANCE 0x00 |
| 500 | #define HWP_EPP_BALANCE_PERFORMANCE 0x80 |
| 501 | #define HWP_EPP_BALANCE_POWERSAVE 0xC0 |
| 502 | #define HWP_EPP_POWERSAVE 0xFF |
Len Brown | 2fc49cb | 2017-04-29 00:11:46 -0400 | [diff] [blame] | 503 | #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) |
| 504 | #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) |
Dirk Brandewie | 2f86dc4 | 2014-11-06 09:40:47 -0800 | [diff] [blame] | 505 | |
| 506 | /* IA32_HWP_STATUS */ |
| 507 | #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) |
| 508 | #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) |
| 509 | |
| 510 | /* IA32_HWP_INTERRUPT */ |
| 511 | #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) |
| 512 | #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) |
| 513 | |
Joerg Roedel | 5bbc097 | 2011-04-15 14:47:40 +0200 | [diff] [blame] | 514 | #define MSR_AMD64_MC0_MASK 0xc0010044 |
| 515 | |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 516 | #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) |
| 517 | #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) |
| 518 | #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) |
| 519 | #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) |
| 520 | |
Joerg Roedel | 5bbc097 | 2011-04-15 14:47:40 +0200 | [diff] [blame] | 521 | #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) |
| 522 | |
Andi Kleen | 03195c6 | 2009-02-12 13:49:35 +0100 | [diff] [blame] | 523 | /* These are consecutive and not in the normal 4er MCE bank block */ |
| 524 | #define MSR_IA32_MC0_CTL2 0x00000280 |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 525 | #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) |
| 526 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 527 | #define MSR_P6_PERFCTR0 0x000000c1 |
| 528 | #define MSR_P6_PERFCTR1 0x000000c2 |
| 529 | #define MSR_P6_EVNTSEL0 0x00000186 |
| 530 | #define MSR_P6_EVNTSEL1 0x00000187 |
| 531 | |
Vince Weaver | e717bf4 | 2012-09-26 14:12:52 -0400 | [diff] [blame] | 532 | #define MSR_KNC_PERFCTR0 0x00000020 |
| 533 | #define MSR_KNC_PERFCTR1 0x00000021 |
| 534 | #define MSR_KNC_EVNTSEL0 0x00000028 |
| 535 | #define MSR_KNC_EVNTSEL1 0x00000029 |
| 536 | |
Andi Kleen | 069e0c3 | 2013-06-25 08:12:33 -0700 | [diff] [blame] | 537 | /* Alternative perfctr range with full access. */ |
| 538 | #define MSR_IA32_PMC0 0x000004c1 |
| 539 | |
Alexander Shishkin | 42880f7 | 2019-08-06 11:46:01 +0300 | [diff] [blame] | 540 | /* Auto-reload via MSR instead of DS area */ |
| 541 | #define MSR_RELOAD_PMC0 0x000014c1 |
| 542 | #define MSR_RELOAD_FIXED_CTR0 0x00001309 |
| 543 | |
Kai Huang | 765a054 | 2023-12-08 09:07:21 -0800 | [diff] [blame] | 544 | /* KeyID partitioning between MKTME and TDX */ |
| 545 | #define MSR_IA32_MKTME_KEYID_PARTITIONING 0x00000087 |
| 546 | |
Borislav Petkov | 342061c | 2019-08-19 09:01:40 +0200 | [diff] [blame] | 547 | /* |
| 548 | * AMD64 MSRs. Not complete. See the architecture manual for a more |
| 549 | * complete list. |
| 550 | */ |
Andreas Herrmann | 29d0887 | 2008-12-16 19:16:34 +0100 | [diff] [blame] | 551 | #define MSR_AMD64_PATCH_LEVEL 0x0000008b |
Joerg Roedel | fbc0db7 | 2011-03-25 09:44:46 +0100 | [diff] [blame] | 552 | #define MSR_AMD64_TSC_RATIO 0xc0000104 |
stephane eranian | 12db648 | 2008-03-07 13:05:39 -0800 | [diff] [blame] | 553 | #define MSR_AMD64_NB_CFG 0xc001001f |
Andreas Herrmann | 29d0887 | 2008-12-16 19:16:34 +0100 | [diff] [blame] | 554 | #define MSR_AMD64_PATCH_LOADER 0xc0010020 |
Borislav Petkov | 342061c | 2019-08-19 09:01:40 +0200 | [diff] [blame] | 555 | #define MSR_AMD_PERF_CTL 0xc0010062 |
| 556 | #define MSR_AMD_PERF_STATUS 0xc0010063 |
| 557 | #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 |
Andreas Herrmann | 035a02c | 2010-03-19 12:09:22 +0100 | [diff] [blame] | 558 | #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 |
| 559 | #define MSR_AMD64_OSVW_STATUS 0xc0010141 |
Jan Beulich | 4e3f77d | 2019-11-11 15:46:26 +0100 | [diff] [blame] | 560 | #define MSR_AMD_PPIN_CTL 0xc00102f0 |
| 561 | #define MSR_AMD_PPIN 0xc00102f1 |
Borislav Petkov | 1068ed4 | 2020-06-08 16:19:49 +0200 | [diff] [blame] | 562 | #define MSR_AMD64_CPUID_FN_1 0xc0011004 |
Borislav Petkov | 3b56496 | 2014-01-15 00:07:11 +0100 | [diff] [blame] | 563 | #define MSR_AMD64_LS_CFG 0xc0011020 |
Joerg Roedel | 67ec660 | 2010-05-17 14:43:35 +0200 | [diff] [blame] | 564 | #define MSR_AMD64_DC_CFG 0xc0011022 |
Maciej S. Szmigiero | 2770d47 | 2023-10-19 18:06:57 +0200 | [diff] [blame] | 565 | #define MSR_AMD64_TW_CFG 0xc0011023 |
Borislav Petkov | 2632dae | 2022-11-14 12:44:01 +0100 | [diff] [blame] | 566 | |
| 567 | #define MSR_AMD64_DE_CFG 0xc0011029 |
| 568 | #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1 |
| 569 | #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT) |
Borislav Petkov (AMD) | 522b1d6 | 2023-07-15 13:41:28 +0200 | [diff] [blame] | 570 | #define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9 |
Borislav Petkov | 2632dae | 2022-11-14 12:44:01 +0100 | [diff] [blame] | 571 | |
Boris Ostrovsky | f0322bd | 2013-01-29 16:32:49 -0500 | [diff] [blame] | 572 | #define MSR_AMD64_BU_CFG2 0xc001102a |
Stephane Eranian | 4f8a6b1 | 2007-10-19 20:35:03 +0200 | [diff] [blame] | 573 | #define MSR_AMD64_IBSFETCHCTL 0xc0011030 |
| 574 | #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 |
| 575 | #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 |
Robert Richter | b7074f1 | 2011-12-15 17:56:37 +0100 | [diff] [blame] | 576 | #define MSR_AMD64_IBSFETCH_REG_COUNT 3 |
| 577 | #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) |
Stephane Eranian | 4f8a6b1 | 2007-10-19 20:35:03 +0200 | [diff] [blame] | 578 | #define MSR_AMD64_IBSOPCTL 0xc0011033 |
| 579 | #define MSR_AMD64_IBSOPRIP 0xc0011034 |
| 580 | #define MSR_AMD64_IBSOPDATA 0xc0011035 |
| 581 | #define MSR_AMD64_IBSOPDATA2 0xc0011036 |
| 582 | #define MSR_AMD64_IBSOPDATA3 0xc0011037 |
| 583 | #define MSR_AMD64_IBSDCLINAD 0xc0011038 |
| 584 | #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 |
Robert Richter | b7074f1 | 2011-12-15 17:56:37 +0100 | [diff] [blame] | 585 | #define MSR_AMD64_IBSOP_REG_COUNT 7 |
| 586 | #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) |
Stephane Eranian | 4f8a6b1 | 2007-10-19 20:35:03 +0200 | [diff] [blame] | 587 | #define MSR_AMD64_IBSCTL 0xc001103a |
Robert Richter | 25da695 | 2010-09-21 15:49:31 +0200 | [diff] [blame] | 588 | #define MSR_AMD64_IBSBRTARGET 0xc001103b |
Kim Phillips | 36e1be8 | 2020-09-08 16:47:38 -0500 | [diff] [blame] | 589 | #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c |
Aravind Gopalakrishnan | 904cb36 | 2014-11-10 14:24:26 -0600 | [diff] [blame] | 590 | #define MSR_AMD64_IBSOPDATA4 0xc001103d |
Robert Richter | b7074f1 | 2011-12-15 17:56:37 +0100 | [diff] [blame] | 591 | #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ |
Maxim Levitsky | 3915035 | 2022-02-07 17:54:26 +0200 | [diff] [blame] | 592 | #define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b |
Tom Lendacky | 69372cf0 | 2020-12-10 11:09:36 -0600 | [diff] [blame] | 593 | #define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e |
Joerg Roedel | 29dcc60 | 2020-09-07 15:15:20 +0200 | [diff] [blame] | 594 | #define MSR_AMD64_SEV_ES_GHCB 0xc0010130 |
Tom Lendacky | 1958b5f | 2017-10-20 09:30:54 -0500 | [diff] [blame] | 595 | #define MSR_AMD64_SEV 0xc0010131 |
| 596 | #define MSR_AMD64_SEV_ENABLED_BIT 0 |
Joerg Roedel | b57de6c | 2020-09-07 15:15:37 +0200 | [diff] [blame] | 597 | #define MSR_AMD64_SEV_ES_ENABLED_BIT 1 |
Brijesh Singh | f742b90 | 2022-02-24 10:55:49 -0600 | [diff] [blame] | 598 | #define MSR_AMD64_SEV_SNP_ENABLED_BIT 2 |
Tom Lendacky | 1958b5f | 2017-10-20 09:30:54 -0500 | [diff] [blame] | 599 | #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) |
Joerg Roedel | b57de6c | 2020-09-07 15:15:37 +0200 | [diff] [blame] | 600 | #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) |
Brijesh Singh | f742b90 | 2022-02-24 10:55:49 -0600 | [diff] [blame] | 601 | #define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) |
Stephane Eranian | 4f8a6b1 | 2007-10-19 20:35:03 +0200 | [diff] [blame] | 602 | |
Nikunj A Dadhania | 8c29f01 | 2023-01-18 11:49:43 +0530 | [diff] [blame] | 603 | /* SNP feature bits enabled by the hypervisor */ |
| 604 | #define MSR_AMD64_SNP_VTOM BIT_ULL(3) |
| 605 | #define MSR_AMD64_SNP_REFLECT_VC BIT_ULL(4) |
| 606 | #define MSR_AMD64_SNP_RESTRICTED_INJ BIT_ULL(5) |
| 607 | #define MSR_AMD64_SNP_ALT_INJ BIT_ULL(6) |
| 608 | #define MSR_AMD64_SNP_DEBUG_SWAP BIT_ULL(7) |
| 609 | #define MSR_AMD64_SNP_PREVENT_HOST_IBS BIT_ULL(8) |
| 610 | #define MSR_AMD64_SNP_BTB_ISOLATION BIT_ULL(9) |
| 611 | #define MSR_AMD64_SNP_VMPL_SSS BIT_ULL(10) |
| 612 | #define MSR_AMD64_SNP_SECURE_TSC BIT_ULL(11) |
| 613 | #define MSR_AMD64_SNP_VMGEXIT_PARAM BIT_ULL(12) |
| 614 | #define MSR_AMD64_SNP_IBS_VIRT BIT_ULL(14) |
| 615 | #define MSR_AMD64_SNP_VMSA_REG_PROTECTION BIT_ULL(16) |
| 616 | #define MSR_AMD64_SNP_SMT_PROTECTION BIT_ULL(17) |
| 617 | |
| 618 | /* SNP feature bits reserved for future use. */ |
| 619 | #define MSR_AMD64_SNP_RESERVED_BIT13 BIT_ULL(13) |
| 620 | #define MSR_AMD64_SNP_RESERVED_BIT15 BIT_ULL(15) |
| 621 | #define MSR_AMD64_SNP_RESERVED_MASK GENMASK_ULL(63, 18) |
| 622 | |
Tom Lendacky | 11fb068 | 2018-05-17 17:09:18 +0200 | [diff] [blame] | 623 | #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f |
| 624 | |
Huang Rui | 89aa94b | 2021-12-24 09:04:56 +0800 | [diff] [blame] | 625 | /* AMD Collaborative Processor Performance Control MSRs */ |
| 626 | #define MSR_AMD_CPPC_CAP1 0xc00102b0 |
| 627 | #define MSR_AMD_CPPC_ENABLE 0xc00102b1 |
| 628 | #define MSR_AMD_CPPC_CAP2 0xc00102b2 |
| 629 | #define MSR_AMD_CPPC_REQ 0xc00102b3 |
| 630 | #define MSR_AMD_CPPC_STATUS 0xc00102b4 |
| 631 | |
| 632 | #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) |
| 633 | #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) |
| 634 | #define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff) |
| 635 | #define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff) |
| 636 | |
| 637 | #define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0) |
| 638 | #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) |
| 639 | #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) |
| 640 | #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) |
| 641 | |
Sandipan Das | 089be16 | 2022-04-21 11:16:54 +0530 | [diff] [blame] | 642 | /* AMD Performance Counter Global Status and Control MSRs */ |
| 643 | #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 |
| 644 | #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 |
| 645 | #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 |
| 646 | |
Sandipan Das | ca5b7c0 | 2022-08-11 17:59:54 +0530 | [diff] [blame] | 647 | /* AMD Last Branch Record MSRs */ |
| 648 | #define MSR_AMD64_LBR_SELECT 0xc000010e |
| 649 | |
Borislav Petkov | deedec0 | 2023-10-12 20:01:59 +0200 | [diff] [blame] | 650 | /* Zen4 */ |
| 651 | #define MSR_ZEN4_BP_CFG 0xc001102e |
Borislav Petkov (AMD) | f454b18 | 2023-10-07 12:57:02 +0200 | [diff] [blame] | 652 | #define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5 |
Huang Rui | aaf2488 | 2016-01-29 16:29:57 +0800 | [diff] [blame] | 653 | |
Borislav Petkov | deedec0 | 2023-10-12 20:01:59 +0200 | [diff] [blame] | 654 | /* Fam 19h MSRs */ |
| 655 | #define MSR_F19H_UMC_PERF_CTL 0xc0010800 |
| 656 | #define MSR_F19H_UMC_PERF_CTR 0xc0010801 |
Jacob Shin | c43ca50 | 2013-04-19 16:34:28 -0500 | [diff] [blame] | 657 | |
Borislav Petkov | deedec0 | 2023-10-12 20:01:59 +0200 | [diff] [blame] | 658 | /* Zen 2 */ |
| 659 | #define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 |
| 660 | #define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1) |
| 661 | |
| 662 | /* Fam 17h MSRs */ |
| 663 | #define MSR_F17H_IRPERF 0xc00000e9 |
Peter Zijlstra | d7caac9 | 2022-06-14 23:16:04 +0200 | [diff] [blame] | 664 | |
Jacob Shin | c43ca50 | 2013-04-19 16:34:28 -0500 | [diff] [blame] | 665 | /* Fam 16h MSRs */ |
| 666 | #define MSR_F16H_L2I_PERF_CTL 0xc0010230 |
| 667 | #define MSR_F16H_L2I_PERF_CTR 0xc0010231 |
Jacob Shin | d6d55f0 | 2014-05-29 17:26:50 +0200 | [diff] [blame] | 668 | #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 |
| 669 | #define MSR_F16H_DR2_ADDR_MASK 0xc001101a |
| 670 | #define MSR_F16H_DR3_ADDR_MASK 0xc001101b |
| 671 | #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 |
Jacob Shin | c43ca50 | 2013-04-19 16:34:28 -0500 | [diff] [blame] | 672 | |
Robert Richter | da169f5 | 2010-09-24 15:54:43 +0200 | [diff] [blame] | 673 | /* Fam 15h MSRs */ |
Borislav Petkov | 99e4020 | 2020-06-21 12:41:53 +0200 | [diff] [blame] | 674 | #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a |
| 675 | #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b |
Robert Richter | da169f5 | 2010-09-24 15:54:43 +0200 | [diff] [blame] | 676 | #define MSR_F15H_PERF_CTL 0xc0010200 |
Janakarajan Natarajan | e84b711 | 2018-02-05 13:24:51 -0600 | [diff] [blame] | 677 | #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL |
| 678 | #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) |
| 679 | #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) |
| 680 | #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) |
| 681 | #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) |
| 682 | #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) |
| 683 | |
Robert Richter | da169f5 | 2010-09-24 15:54:43 +0200 | [diff] [blame] | 684 | #define MSR_F15H_PERF_CTR 0xc0010201 |
Janakarajan Natarajan | e84b711 | 2018-02-05 13:24:51 -0600 | [diff] [blame] | 685 | #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR |
| 686 | #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) |
| 687 | #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) |
| 688 | #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) |
| 689 | #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) |
| 690 | #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) |
| 691 | |
Jacob Shin | e259514 | 2013-02-06 11:26:29 -0600 | [diff] [blame] | 692 | #define MSR_F15H_NB_PERF_CTL 0xc0010240 |
| 693 | #define MSR_F15H_NB_PERF_CTR 0xc0010241 |
Huang Rui | 8a22426 | 2016-01-29 16:29:56 +0800 | [diff] [blame] | 694 | #define MSR_F15H_PTSC 0xc0010280 |
Borislav Petkov | ae8b787 | 2015-11-23 11:12:23 +0100 | [diff] [blame] | 695 | #define MSR_F15H_IC_CFG 0xc0011021 |
Eduardo Habkost | 0e1b869 | 2018-12-17 22:34:18 -0200 | [diff] [blame] | 696 | #define MSR_F15H_EX_CFG 0xc001102c |
Robert Richter | da169f5 | 2010-09-24 15:54:43 +0200 | [diff] [blame] | 697 | |
Yinghai Lu | 2274c33 | 2008-01-30 13:33:18 +0100 | [diff] [blame] | 698 | /* Fam 10h MSRs */ |
| 699 | #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 |
| 700 | #define FAM10H_MMIO_CONF_ENABLE (1<<0) |
| 701 | #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf |
| 702 | #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 |
Jan Beulich | 37db6c8 | 2010-11-16 08:25:08 +0000 | [diff] [blame] | 703 | #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL |
Yinghai Lu | 2274c33 | 2008-01-30 13:33:18 +0100 | [diff] [blame] | 704 | #define FAM10H_MMIO_CONF_BASE_SHIFT 20 |
Andreas Herrmann | 9d260eb | 2009-12-16 15:43:55 +0100 | [diff] [blame] | 705 | #define MSR_FAM10H_NODE_ID 0xc001100c |
Yinghai Lu | 2274c33 | 2008-01-30 13:33:18 +0100 | [diff] [blame] | 706 | |
Stephane Eranian | 4f8a6b1 | 2007-10-19 20:35:03 +0200 | [diff] [blame] | 707 | /* K8 MSRs */ |
| 708 | #define MSR_K8_TOP_MEM1 0xc001001a |
| 709 | #define MSR_K8_TOP_MEM2 0xc001001d |
Brijesh Singh | 059e5c3 | 2021-04-27 06:16:36 -0500 | [diff] [blame] | 710 | #define MSR_AMD64_SYSCFG 0xc0010010 |
| 711 | #define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23 |
| 712 | #define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT) |
Thomas Gleixner | aa83f3f | 2008-06-09 17:11:13 +0200 | [diff] [blame] | 713 | #define MSR_K8_INT_PENDING_MSG 0xc0010055 |
| 714 | /* C1E active bits in int pending message */ |
| 715 | #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 |
Andi Kleen | 8346ea1 | 2008-03-12 03:53:32 +0100 | [diff] [blame] | 716 | #define MSR_K8_TSEG_ADDR 0xc0010112 |
Paolo Bonzini | 3afb112 | 2015-09-18 17:33:04 +0200 | [diff] [blame] | 717 | #define MSR_K8_TSEG_MASK 0xc0010113 |
Stephane Eranian | 4f8a6b1 | 2007-10-19 20:35:03 +0200 | [diff] [blame] | 718 | #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ |
| 719 | #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ |
| 720 | #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ |
| 721 | |
| 722 | /* K7 MSRs */ |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 723 | #define MSR_K7_EVNTSEL0 0xc0010000 |
| 724 | #define MSR_K7_PERFCTR0 0xc0010004 |
| 725 | #define MSR_K7_EVNTSEL1 0xc0010001 |
| 726 | #define MSR_K7_PERFCTR1 0xc0010005 |
| 727 | #define MSR_K7_EVNTSEL2 0xc0010002 |
| 728 | #define MSR_K7_PERFCTR2 0xc0010006 |
| 729 | #define MSR_K7_EVNTSEL3 0xc0010003 |
| 730 | #define MSR_K7_PERFCTR3 0xc0010007 |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 731 | #define MSR_K7_CLK_CTL 0xc001001b |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 732 | #define MSR_K7_HWCR 0xc0010015 |
Tom Lendacky | 18c71ce | 2017-12-04 10:57:23 -0600 | [diff] [blame] | 733 | #define MSR_K7_HWCR_SMMLOCK_BIT 0 |
| 734 | #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) |
Kim Phillips | 21b5ee5 | 2020-02-19 18:52:43 +0100 | [diff] [blame] | 735 | #define MSR_K7_HWCR_IRPERF_EN_BIT 30 |
| 736 | #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 737 | #define MSR_K7_FID_VID_CTL 0xc0010041 |
| 738 | #define MSR_K7_FID_VID_STATUS 0xc0010042 |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 739 | |
| 740 | /* K6 MSRs */ |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 741 | #define MSR_K6_WHCR 0xc0000082 |
| 742 | #define MSR_K6_UWCCR 0xc0000085 |
| 743 | #define MSR_K6_EPMR 0xc0000086 |
| 744 | #define MSR_K6_PSOR 0xc0000087 |
| 745 | #define MSR_K6_PFIR 0xc0000088 |
| 746 | |
| 747 | /* Centaur-Hauls/IDT defined MSRs. */ |
| 748 | #define MSR_IDT_FCR1 0x00000107 |
| 749 | #define MSR_IDT_FCR2 0x00000108 |
| 750 | #define MSR_IDT_FCR3 0x00000109 |
| 751 | #define MSR_IDT_FCR4 0x0000010a |
| 752 | |
| 753 | #define MSR_IDT_MCR0 0x00000110 |
| 754 | #define MSR_IDT_MCR1 0x00000111 |
| 755 | #define MSR_IDT_MCR2 0x00000112 |
| 756 | #define MSR_IDT_MCR3 0x00000113 |
| 757 | #define MSR_IDT_MCR4 0x00000114 |
| 758 | #define MSR_IDT_MCR5 0x00000115 |
| 759 | #define MSR_IDT_MCR6 0x00000116 |
| 760 | #define MSR_IDT_MCR7 0x00000117 |
| 761 | #define MSR_IDT_MCR_CTRL 0x00000120 |
| 762 | |
| 763 | /* VIA Cyrix defined MSRs*/ |
| 764 | #define MSR_VIA_FCR 0x00001107 |
| 765 | #define MSR_VIA_LONGHAUL 0x0000110a |
| 766 | #define MSR_VIA_RNG 0x0000110b |
| 767 | #define MSR_VIA_BCR2 0x00001147 |
| 768 | |
| 769 | /* Transmeta defined MSRs */ |
| 770 | #define MSR_TMTA_LONGRUN_CTRL 0x80868010 |
| 771 | #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 |
| 772 | #define MSR_TMTA_LRTI_READOUT 0x80868018 |
| 773 | #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a |
| 774 | |
| 775 | /* Intel defined MSRs. */ |
| 776 | #define MSR_IA32_P5_MC_ADDR 0x00000000 |
| 777 | #define MSR_IA32_P5_MC_TYPE 0x00000001 |
| 778 | #define MSR_IA32_TSC 0x00000010 |
| 779 | #define MSR_IA32_PLATFORM_ID 0x00000017 |
| 780 | #define MSR_IA32_EBL_CR_POWERON 0x0000002a |
Jes Sorensen | b9a52c4 | 2010-09-09 12:06:45 +0200 | [diff] [blame] | 781 | #define MSR_EBC_FREQUENCY_ID 0x0000002c |
Len Brown | 1ed5101 | 2013-02-10 17:19:24 -0500 | [diff] [blame] | 782 | #define MSR_SMI_COUNT 0x00000034 |
Sean Christopherson | 32ad73d | 2019-12-20 20:44:55 -0800 | [diff] [blame] | 783 | |
| 784 | /* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ |
| 785 | #define MSR_IA32_FEAT_CTL 0x0000003a |
| 786 | #define FEAT_CTL_LOCKED BIT(0) |
| 787 | #define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) |
| 788 | #define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) |
Sean Christopherson | d205e0f | 2020-11-13 00:01:15 +0200 | [diff] [blame] | 789 | #define FEAT_CTL_SGX_LC_ENABLED BIT(17) |
Sean Christopherson | e7b6385 | 2020-11-13 00:01:14 +0200 | [diff] [blame] | 790 | #define FEAT_CTL_SGX_ENABLED BIT(18) |
Sean Christopherson | 32ad73d | 2019-12-20 20:44:55 -0800 | [diff] [blame] | 791 | #define FEAT_CTL_LMCE_ENABLED BIT(20) |
| 792 | |
Will Auld | ba90463 | 2012-11-29 12:42:50 -0800 | [diff] [blame] | 793 | #define MSR_IA32_TSC_ADJUST 0x0000003b |
Liu, Jinsong | da8999d | 2014-02-24 10:55:46 +0000 | [diff] [blame] | 794 | #define MSR_IA32_BNDCFGS 0x00000d90 |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 795 | |
Jim Mattson | 4531662 | 2017-05-23 11:52:54 -0700 | [diff] [blame] | 796 | #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc |
| 797 | |
Chang S. Bae | dae1bd58 | 2021-10-21 15:55:17 -0700 | [diff] [blame] | 798 | #define MSR_IA32_XFD 0x000001c4 |
| 799 | #define MSR_IA32_XFD_ERR 0x000001c5 |
Fenghua Yu | 6229ad2 | 2014-05-29 11:12:30 -0700 | [diff] [blame] | 800 | #define MSR_IA32_XSS 0x00000da0 |
| 801 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 802 | #define MSR_IA32_APICBASE 0x0000001b |
| 803 | #define MSR_IA32_APICBASE_BSP (1<<8) |
| 804 | #define MSR_IA32_APICBASE_ENABLE (1<<11) |
| 805 | #define MSR_IA32_APICBASE_BASE (0xfffff<<12) |
| 806 | |
| 807 | #define MSR_IA32_UCODE_WRITE 0x00000079 |
| 808 | #define MSR_IA32_UCODE_REV 0x0000008b |
| 809 | |
Sean Christopherson | d205e0f | 2020-11-13 00:01:15 +0200 | [diff] [blame] | 810 | /* Intel SGX Launch Enclave Public Key Hash MSRs */ |
| 811 | #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C |
| 812 | #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D |
| 813 | #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E |
| 814 | #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F |
| 815 | |
Eugene Korenevsky | e9ac033 | 2014-12-11 08:53:27 +0300 | [diff] [blame] | 816 | #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b |
| 817 | #define MSR_IA32_SMBASE 0x0000009e |
| 818 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 819 | #define MSR_IA32_PERF_STATUS 0x00000198 |
| 820 | #define MSR_IA32_PERF_CTL 0x00000199 |
Srinidhi Kasagar | e7ddf4b | 2014-12-19 23:13:51 +0530 | [diff] [blame] | 821 | #define INTEL_PERF_CTL_MASK 0xffff |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 822 | |
Stephane Eranian | ada5434 | 2022-03-22 15:15:07 -0700 | [diff] [blame] | 823 | /* AMD Branch Sampling configuration */ |
| 824 | #define MSR_AMD_DBG_EXTN_CFG 0xc000010f |
| 825 | #define MSR_AMD_SAMP_BR_FROM 0xc0010300 |
| 826 | |
Sandipan Das | ca5b7c0 | 2022-08-11 17:59:54 +0530 | [diff] [blame] | 827 | #define DBG_EXTN_CFG_LBRV2EN BIT_ULL(6) |
| 828 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 829 | #define MSR_IA32_MPERF 0x000000e7 |
| 830 | #define MSR_IA32_APERF 0x000000e8 |
| 831 | |
| 832 | #define MSR_IA32_THERM_CONTROL 0x0000019a |
| 833 | #define MSR_IA32_THERM_INTERRUPT 0x0000019b |
Thomas Gleixner | ba2d0f2 | 2009-04-08 12:31:24 +0200 | [diff] [blame] | 834 | |
Fenghua Yu | 9792db6 | 2010-07-29 17:13:42 -0700 | [diff] [blame] | 835 | #define THERM_INT_HIGH_ENABLE (1 << 0) |
| 836 | #define THERM_INT_LOW_ENABLE (1 << 1) |
| 837 | #define THERM_INT_PLN_ENABLE (1 << 24) |
Thomas Gleixner | ba2d0f2 | 2009-04-08 12:31:24 +0200 | [diff] [blame] | 838 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 839 | #define MSR_IA32_THERM_STATUS 0x0000019c |
Thomas Gleixner | ba2d0f2 | 2009-04-08 12:31:24 +0200 | [diff] [blame] | 840 | |
| 841 | #define THERM_STATUS_PROCHOT (1 << 0) |
Fenghua Yu | 9792db6 | 2010-07-29 17:13:42 -0700 | [diff] [blame] | 842 | #define THERM_STATUS_POWER_LIMIT (1 << 10) |
Thomas Gleixner | ba2d0f2 | 2009-04-08 12:31:24 +0200 | [diff] [blame] | 843 | |
Bartlomiej Zolnierkiewicz | f3a0867 | 2009-07-29 00:04:59 +0200 | [diff] [blame] | 844 | #define MSR_THERM2_CTL 0x0000019d |
| 845 | |
| 846 | #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) |
| 847 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 848 | #define MSR_IA32_MISC_ENABLE 0x000001a0 |
| 849 | |
Carsten Emde | a321ced | 2010-05-24 14:33:41 -0700 | [diff] [blame] | 850 | #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 |
| 851 | |
Len Brown | 98af745 | 2017-01-21 01:15:09 -0500 | [diff] [blame] | 852 | #define MSR_MISC_FEATURE_CONTROL 0x000001a4 |
Dirk Brandewie | 2f86dc4 | 2014-11-06 09:40:47 -0800 | [diff] [blame] | 853 | #define MSR_MISC_PWR_MGMT 0x000001aa |
| 854 | |
Venkatesh Pallipadi | 23016bf | 2010-06-03 23:22:28 -0400 | [diff] [blame] | 855 | #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 |
Len Brown | d0117a0 | 2017-02-25 18:18:22 -0500 | [diff] [blame] | 856 | #define ENERGY_PERF_BIAS_PERFORMANCE 0 |
| 857 | #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 |
| 858 | #define ENERGY_PERF_BIAS_NORMAL 6 |
Srinivas Pandruvada | 7420ae3 | 2022-10-27 15:00:56 -0700 | [diff] [blame] | 859 | #define ENERGY_PERF_BIAS_NORMAL_POWERSAVE 7 |
Len Brown | d0117a0 | 2017-02-25 18:18:22 -0500 | [diff] [blame] | 860 | #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 |
| 861 | #define ENERGY_PERF_BIAS_POWERSAVE 15 |
Venkatesh Pallipadi | 23016bf | 2010-06-03 23:22:28 -0400 | [diff] [blame] | 862 | |
Fenghua Yu | 9792db6 | 2010-07-29 17:13:42 -0700 | [diff] [blame] | 863 | #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 |
| 864 | |
| 865 | #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) |
| 866 | #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) |
Ricardo Neri | 7b8f40b3 | 2022-01-27 11:34:49 -0800 | [diff] [blame] | 867 | #define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26) |
Fenghua Yu | 9792db6 | 2010-07-29 17:13:42 -0700 | [diff] [blame] | 868 | |
| 869 | #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 |
| 870 | |
| 871 | #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) |
| 872 | #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) |
| 873 | #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) |
Ricardo Neri | 7b8f40b3 | 2022-01-27 11:34:49 -0800 | [diff] [blame] | 874 | #define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25) |
Fenghua Yu | 9792db6 | 2010-07-29 17:13:42 -0700 | [diff] [blame] | 875 | |
R, Durgadoss | 9e76a97 | 2011-01-03 17:22:04 +0530 | [diff] [blame] | 876 | /* Thermal Thresholds Support */ |
| 877 | #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) |
| 878 | #define THERM_SHIFT_THRESHOLD0 8 |
| 879 | #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) |
| 880 | #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) |
| 881 | #define THERM_SHIFT_THRESHOLD1 16 |
| 882 | #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) |
| 883 | #define THERM_STATUS_THRESHOLD0 (1 << 6) |
| 884 | #define THERM_LOG_THRESHOLD0 (1 << 7) |
| 885 | #define THERM_STATUS_THRESHOLD1 (1 << 8) |
| 886 | #define THERM_LOG_THRESHOLD1 (1 << 9) |
| 887 | |
H. Peter Anvin | bdf21a4 | 2009-01-21 15:01:56 -0800 | [diff] [blame] | 888 | /* MISC_ENABLE bits: architectural */ |
H. Peter Anvin | 0b131be | 2014-03-13 15:40:52 -0700 | [diff] [blame] | 889 | #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 |
| 890 | #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) |
| 891 | #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 |
| 892 | #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) |
| 893 | #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 |
| 894 | #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) |
| 895 | #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 |
| 896 | #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) |
| 897 | #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 |
| 898 | #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) |
| 899 | #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 |
| 900 | #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) |
| 901 | #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 |
| 902 | #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) |
| 903 | #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 |
Andres Freund | c45f773 | 2014-05-09 03:29:17 +0200 | [diff] [blame] | 904 | #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) |
H. Peter Anvin | 0b131be | 2014-03-13 15:40:52 -0700 | [diff] [blame] | 905 | #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 |
| 906 | #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) |
| 907 | #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 |
| 908 | #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) |
H. Peter Anvin | bdf21a4 | 2009-01-21 15:01:56 -0800 | [diff] [blame] | 909 | |
| 910 | /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ |
H. Peter Anvin | 0b131be | 2014-03-13 15:40:52 -0700 | [diff] [blame] | 911 | #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 |
| 912 | #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) |
| 913 | #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 |
| 914 | #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) |
| 915 | #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 |
| 916 | #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) |
| 917 | #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 |
| 918 | #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) |
| 919 | #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 |
| 920 | #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) |
| 921 | #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 |
| 922 | #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) |
| 923 | #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 |
| 924 | #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) |
| 925 | #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 |
| 926 | #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) |
| 927 | #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 |
| 928 | #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) |
| 929 | #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 |
| 930 | #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) |
| 931 | #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 |
| 932 | #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) |
| 933 | #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 |
| 934 | #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) |
| 935 | #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 |
| 936 | #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) |
| 937 | #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 |
| 938 | #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) |
| 939 | #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 |
| 940 | #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) |
H. Peter Anvin | bdf21a4 | 2009-01-21 15:01:56 -0800 | [diff] [blame] | 941 | |
Kyle Huey | ab6d946 | 2017-03-20 01:16:19 -0700 | [diff] [blame] | 942 | /* MISC_FEATURES_ENABLES non-architectural features */ |
| 943 | #define MSR_MISC_FEATURES_ENABLES 0x00000140 |
Grzegorz Andrejczuk | ae47eda | 2017-01-20 14:22:33 +0100 | [diff] [blame] | 944 | |
Kyle Huey | e9ea1e7 | 2017-03-20 01:16:26 -0700 | [diff] [blame] | 945 | #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 |
| 946 | #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) |
Kyle Huey | ab6d946 | 2017-03-20 01:16:19 -0700 | [diff] [blame] | 947 | #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 |
Grzegorz Andrejczuk | ae47eda | 2017-01-20 14:22:33 +0100 | [diff] [blame] | 948 | |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 949 | #define MSR_IA32_TSC_DEADLINE 0x000006E0 |
| 950 | |
Peter Zijlstra (Intel) | 52f6490 | 2019-03-05 22:23:17 +0100 | [diff] [blame] | 951 | |
| 952 | #define MSR_TSX_FORCE_ABORT 0x0000010F |
| 953 | |
| 954 | #define MSR_TFA_RTM_FORCE_ABORT_BIT 0 |
| 955 | #define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) |
Pawan Gupta | 1348924 | 2021-06-14 14:12:22 -0700 | [diff] [blame] | 956 | #define MSR_TFA_TSX_CPUID_CLEAR_BIT 1 |
| 957 | #define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT) |
| 958 | #define MSR_TFA_SDV_ENABLE_RTM_BIT 2 |
| 959 | #define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT) |
Peter Zijlstra (Intel) | 52f6490 | 2019-03-05 22:23:17 +0100 | [diff] [blame] | 960 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 961 | /* P4/Xeon+ specific */ |
| 962 | #define MSR_IA32_MCG_EAX 0x00000180 |
| 963 | #define MSR_IA32_MCG_EBX 0x00000181 |
| 964 | #define MSR_IA32_MCG_ECX 0x00000182 |
| 965 | #define MSR_IA32_MCG_EDX 0x00000183 |
| 966 | #define MSR_IA32_MCG_ESI 0x00000184 |
| 967 | #define MSR_IA32_MCG_EDI 0x00000185 |
| 968 | #define MSR_IA32_MCG_EBP 0x00000186 |
| 969 | #define MSR_IA32_MCG_ESP 0x00000187 |
| 970 | #define MSR_IA32_MCG_EFLAGS 0x00000188 |
| 971 | #define MSR_IA32_MCG_EIP 0x00000189 |
| 972 | #define MSR_IA32_MCG_RESERVED 0x0000018a |
| 973 | |
| 974 | /* Pentium IV performance counter MSRs */ |
| 975 | #define MSR_P4_BPU_PERFCTR0 0x00000300 |
| 976 | #define MSR_P4_BPU_PERFCTR1 0x00000301 |
| 977 | #define MSR_P4_BPU_PERFCTR2 0x00000302 |
| 978 | #define MSR_P4_BPU_PERFCTR3 0x00000303 |
| 979 | #define MSR_P4_MS_PERFCTR0 0x00000304 |
| 980 | #define MSR_P4_MS_PERFCTR1 0x00000305 |
| 981 | #define MSR_P4_MS_PERFCTR2 0x00000306 |
| 982 | #define MSR_P4_MS_PERFCTR3 0x00000307 |
| 983 | #define MSR_P4_FLAME_PERFCTR0 0x00000308 |
| 984 | #define MSR_P4_FLAME_PERFCTR1 0x00000309 |
| 985 | #define MSR_P4_FLAME_PERFCTR2 0x0000030a |
| 986 | #define MSR_P4_FLAME_PERFCTR3 0x0000030b |
| 987 | #define MSR_P4_IQ_PERFCTR0 0x0000030c |
| 988 | #define MSR_P4_IQ_PERFCTR1 0x0000030d |
| 989 | #define MSR_P4_IQ_PERFCTR2 0x0000030e |
| 990 | #define MSR_P4_IQ_PERFCTR3 0x0000030f |
| 991 | #define MSR_P4_IQ_PERFCTR4 0x00000310 |
| 992 | #define MSR_P4_IQ_PERFCTR5 0x00000311 |
| 993 | #define MSR_P4_BPU_CCCR0 0x00000360 |
| 994 | #define MSR_P4_BPU_CCCR1 0x00000361 |
| 995 | #define MSR_P4_BPU_CCCR2 0x00000362 |
| 996 | #define MSR_P4_BPU_CCCR3 0x00000363 |
| 997 | #define MSR_P4_MS_CCCR0 0x00000364 |
| 998 | #define MSR_P4_MS_CCCR1 0x00000365 |
| 999 | #define MSR_P4_MS_CCCR2 0x00000366 |
| 1000 | #define MSR_P4_MS_CCCR3 0x00000367 |
| 1001 | #define MSR_P4_FLAME_CCCR0 0x00000368 |
| 1002 | #define MSR_P4_FLAME_CCCR1 0x00000369 |
| 1003 | #define MSR_P4_FLAME_CCCR2 0x0000036a |
| 1004 | #define MSR_P4_FLAME_CCCR3 0x0000036b |
| 1005 | #define MSR_P4_IQ_CCCR0 0x0000036c |
| 1006 | #define MSR_P4_IQ_CCCR1 0x0000036d |
| 1007 | #define MSR_P4_IQ_CCCR2 0x0000036e |
| 1008 | #define MSR_P4_IQ_CCCR3 0x0000036f |
| 1009 | #define MSR_P4_IQ_CCCR4 0x00000370 |
| 1010 | #define MSR_P4_IQ_CCCR5 0x00000371 |
| 1011 | #define MSR_P4_ALF_ESCR0 0x000003ca |
| 1012 | #define MSR_P4_ALF_ESCR1 0x000003cb |
| 1013 | #define MSR_P4_BPU_ESCR0 0x000003b2 |
| 1014 | #define MSR_P4_BPU_ESCR1 0x000003b3 |
| 1015 | #define MSR_P4_BSU_ESCR0 0x000003a0 |
| 1016 | #define MSR_P4_BSU_ESCR1 0x000003a1 |
| 1017 | #define MSR_P4_CRU_ESCR0 0x000003b8 |
| 1018 | #define MSR_P4_CRU_ESCR1 0x000003b9 |
| 1019 | #define MSR_P4_CRU_ESCR2 0x000003cc |
| 1020 | #define MSR_P4_CRU_ESCR3 0x000003cd |
| 1021 | #define MSR_P4_CRU_ESCR4 0x000003e0 |
| 1022 | #define MSR_P4_CRU_ESCR5 0x000003e1 |
| 1023 | #define MSR_P4_DAC_ESCR0 0x000003a8 |
| 1024 | #define MSR_P4_DAC_ESCR1 0x000003a9 |
| 1025 | #define MSR_P4_FIRM_ESCR0 0x000003a4 |
| 1026 | #define MSR_P4_FIRM_ESCR1 0x000003a5 |
| 1027 | #define MSR_P4_FLAME_ESCR0 0x000003a6 |
| 1028 | #define MSR_P4_FLAME_ESCR1 0x000003a7 |
| 1029 | #define MSR_P4_FSB_ESCR0 0x000003a2 |
| 1030 | #define MSR_P4_FSB_ESCR1 0x000003a3 |
| 1031 | #define MSR_P4_IQ_ESCR0 0x000003ba |
| 1032 | #define MSR_P4_IQ_ESCR1 0x000003bb |
| 1033 | #define MSR_P4_IS_ESCR0 0x000003b4 |
| 1034 | #define MSR_P4_IS_ESCR1 0x000003b5 |
| 1035 | #define MSR_P4_ITLB_ESCR0 0x000003b6 |
| 1036 | #define MSR_P4_ITLB_ESCR1 0x000003b7 |
| 1037 | #define MSR_P4_IX_ESCR0 0x000003c8 |
| 1038 | #define MSR_P4_IX_ESCR1 0x000003c9 |
| 1039 | #define MSR_P4_MOB_ESCR0 0x000003aa |
| 1040 | #define MSR_P4_MOB_ESCR1 0x000003ab |
| 1041 | #define MSR_P4_MS_ESCR0 0x000003c0 |
| 1042 | #define MSR_P4_MS_ESCR1 0x000003c1 |
| 1043 | #define MSR_P4_PMH_ESCR0 0x000003ac |
| 1044 | #define MSR_P4_PMH_ESCR1 0x000003ad |
| 1045 | #define MSR_P4_RAT_ESCR0 0x000003bc |
| 1046 | #define MSR_P4_RAT_ESCR1 0x000003bd |
| 1047 | #define MSR_P4_SAAT_ESCR0 0x000003ae |
| 1048 | #define MSR_P4_SAAT_ESCR1 0x000003af |
| 1049 | #define MSR_P4_SSU_ESCR0 0x000003be |
| 1050 | #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ |
| 1051 | |
| 1052 | #define MSR_P4_TBPU_ESCR0 0x000003c2 |
| 1053 | #define MSR_P4_TBPU_ESCR1 0x000003c3 |
| 1054 | #define MSR_P4_TC_ESCR0 0x000003c4 |
| 1055 | #define MSR_P4_TC_ESCR1 0x000003c5 |
| 1056 | #define MSR_P4_U2L_ESCR0 0x000003b0 |
| 1057 | #define MSR_P4_U2L_ESCR1 0x000003b1 |
| 1058 | |
Lin Ming | cb7d6b5 | 2010-03-18 18:33:12 +0800 | [diff] [blame] | 1059 | #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 |
| 1060 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 1061 | /* Intel Core-based CPU performance counters */ |
| 1062 | #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 |
| 1063 | #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a |
| 1064 | #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b |
Kan Liang | 7b2c05a | 2020-07-23 10:11:11 -0700 | [diff] [blame] | 1065 | #define MSR_CORE_PERF_FIXED_CTR3 0x0000030c |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 1066 | #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d |
| 1067 | #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e |
| 1068 | #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f |
| 1069 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 |
| 1070 | |
Kan Liang | 59a854e | 2020-07-23 10:11:13 -0700 | [diff] [blame] | 1071 | #define MSR_PERF_METRICS 0x00000329 |
| 1072 | |
Luwei Kang | 8479e04 | 2019-02-18 19:26:07 -0500 | [diff] [blame] | 1073 | /* PERF_GLOBAL_OVF_CTL bits */ |
| 1074 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55 |
| 1075 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT) |
Luwei Kang | c715eb9 | 2019-02-18 19:26:08 -0500 | [diff] [blame] | 1076 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62 |
| 1077 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT) |
| 1078 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 |
| 1079 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) |
Luwei Kang | 8479e04 | 2019-02-18 19:26:07 -0500 | [diff] [blame] | 1080 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 1081 | /* Geode defined MSRs */ |
| 1082 | #define MSR_GEODE_BUSCONT_CONF0 0x00001900 |
| 1083 | |
Sheng Yang | 315a655 | 2008-09-09 14:54:53 +0800 | [diff] [blame] | 1084 | /* Intel VT MSRs */ |
| 1085 | #define MSR_IA32_VMX_BASIC 0x00000480 |
| 1086 | #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 |
| 1087 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 |
| 1088 | #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 |
| 1089 | #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 |
| 1090 | #define MSR_IA32_VMX_MISC 0x00000485 |
| 1091 | #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 |
| 1092 | #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 |
| 1093 | #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 |
| 1094 | #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 |
| 1095 | #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a |
| 1096 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b |
| 1097 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c |
Nadav Har'El | b87a51a | 2011-05-25 23:04:25 +0300 | [diff] [blame] | 1098 | #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d |
| 1099 | #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e |
| 1100 | #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f |
| 1101 | #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 |
Jan Kiszka | cae5013 | 2014-01-04 18:47:22 +0100 | [diff] [blame] | 1102 | #define MSR_IA32_VMX_VMFUNC 0x00000491 |
Robert Hoo | 465932d | 2022-04-19 23:32:40 +0800 | [diff] [blame] | 1103 | #define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492 |
Nadav Har'El | b87a51a | 2011-05-25 23:04:25 +0300 | [diff] [blame] | 1104 | |
| 1105 | /* VMX_BASIC bits and bitmasks */ |
| 1106 | #define VMX_BASIC_VMCS_SIZE_SHIFT 32 |
Jan Kiszka | 3dbcd8d | 2014-06-16 13:59:40 +0200 | [diff] [blame] | 1107 | #define VMX_BASIC_TRUE_CTLS (1ULL << 55) |
Nadav Har'El | b87a51a | 2011-05-25 23:04:25 +0300 | [diff] [blame] | 1108 | #define VMX_BASIC_64 0x0001000000000000LLU |
| 1109 | #define VMX_BASIC_MEM_TYPE_SHIFT 50 |
| 1110 | #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU |
| 1111 | #define VMX_BASIC_MEM_TYPE_WB 6LLU |
| 1112 | #define VMX_BASIC_INOUT 0x0040000000000000LLU |
Sheng Yang | 315a655 | 2008-09-09 14:54:53 +0800 | [diff] [blame] | 1113 | |
Borislav Petkov | 97fa21f | 2022-11-06 22:24:08 +0100 | [diff] [blame] | 1114 | /* Resctrl MSRs: */ |
| 1115 | /* - Intel: */ |
| 1116 | #define MSR_IA32_L3_QOS_CFG 0xc81 |
| 1117 | #define MSR_IA32_L2_QOS_CFG 0xc82 |
| 1118 | #define MSR_IA32_QM_EVTSEL 0xc8d |
| 1119 | #define MSR_IA32_QM_CTR 0xc8e |
| 1120 | #define MSR_IA32_PQR_ASSOC 0xc8f |
| 1121 | #define MSR_IA32_L3_CBM_BASE 0xc90 |
| 1122 | #define MSR_IA32_L2_CBM_BASE 0xd10 |
| 1123 | #define MSR_IA32_MBA_THRTL_BASE 0xd50 |
| 1124 | |
| 1125 | /* - AMD: */ |
| 1126 | #define MSR_IA32_MBA_BW_BASE 0xc0000200 |
Babu Moger | 5b6fac3 | 2023-01-13 09:20:32 -0600 | [diff] [blame] | 1127 | #define MSR_IA32_SMBA_BW_BASE 0xc0000280 |
Babu Moger | dc2a3e8 | 2023-01-13 09:20:35 -0600 | [diff] [blame] | 1128 | #define MSR_IA32_EVT_CFG_BASE 0xc0000400 |
Borislav Petkov | 97fa21f | 2022-11-06 22:24:08 +0100 | [diff] [blame] | 1129 | |
Abel Gordon | 89662e5 | 2013-04-18 14:34:55 +0300 | [diff] [blame] | 1130 | /* MSR_IA32_VMX_MISC bits */ |
Chao Peng | f99e3da | 2018-10-24 16:05:10 +0800 | [diff] [blame] | 1131 | #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) |
Abel Gordon | 89662e5 | 2013-04-18 14:34:55 +0300 | [diff] [blame] | 1132 | #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) |
Arthur Chunqi Li | 7854cbc | 2013-09-16 16:11:44 +0800 | [diff] [blame] | 1133 | #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F |
Alexander Graf | 9962d03 | 2008-11-25 20:17:02 +0100 | [diff] [blame] | 1134 | |
Paolo Bonzini | 7deda2c | 2023-09-21 07:49:40 -0400 | [diff] [blame] | 1135 | /* AMD-V MSRs */ |
Alexander Graf | 9962d03 | 2008-11-25 20:17:02 +0100 | [diff] [blame] | 1136 | #define MSR_VM_CR 0xc0010114 |
Alexander Graf | 0367b43 | 2009-06-15 15:21:22 +0200 | [diff] [blame] | 1137 | #define MSR_VM_IGNNE 0xc0010115 |
Alexander Graf | 9962d03 | 2008-11-25 20:17:02 +0100 | [diff] [blame] | 1138 | #define MSR_VM_HSAVE_PA 0xc0010117 |
| 1139 | |
Paolo Bonzini | 7deda2c | 2023-09-21 07:49:40 -0400 | [diff] [blame] | 1140 | #define SVM_VM_CR_VALID_MASK 0x001fULL |
| 1141 | #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL |
| 1142 | #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL |
| 1143 | |
Ricardo Neri | 7b8f40b3 | 2022-01-27 11:34:49 -0800 | [diff] [blame] | 1144 | /* Hardware Feedback Interface */ |
| 1145 | #define MSR_IA32_HW_FEEDBACK_PTR 0x17d0 |
| 1146 | #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 |
| 1147 | |
Daniel Sneddon | b8d1d16 | 2022-08-16 16:19:42 -0700 | [diff] [blame] | 1148 | /* x2APIC locked status */ |
| 1149 | #define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD |
| 1150 | #define LEGACY_XAPIC_DISABLED BIT(0) /* |
| 1151 | * x2APIC mode is locked and |
| 1152 | * disabling x2APIC will cause |
| 1153 | * a #GP |
| 1154 | */ |
| 1155 | |
H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 1156 | #endif /* _ASM_X86_MSR_INDEX_H */ |