blob: 2d2a321d82f8169c3370f93bb859f19c3019bf64 [file] [log] [blame]
Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001// SPDX-License-Identifier: GPL-2.0
eric miaob1d907f2008-01-28 23:00:02 +00002/*
3 * Static Memory Controller
4 */
5
6#include <linux/module.h>
7#include <linux/kernel.h>
8#include <linux/init.h>
9#include <linux/io.h>
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +020010#include <linux/syscore_ops.h>
Arnd Bergmann08d3df82019-09-01 22:26:10 +020011#include <linux/soc/pxa/cpu.h>
eric miaob1d907f2008-01-28 23:00:02 +000012
Arnd Bergmanne6acc402022-04-04 22:37:04 +020013#include "smemc.h"
Arnd Bergmannfd13f812019-09-18 17:42:52 +020014#include <linux/soc/pxa/smemc.h>
eric miaob1d907f2008-01-28 23:00:02 +000015
16#ifdef CONFIG_PM
eric miaob1d907f2008-01-28 23:00:02 +000017static unsigned long msc[2];
18static unsigned long sxcnfg, memclkcfg;
19static unsigned long csadrcfg[4];
20
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +020021static int pxa3xx_smemc_suspend(void)
eric miaob1d907f2008-01-28 23:00:02 +000022{
Marek Vasutad68bb92010-11-03 16:29:35 +010023 msc[0] = __raw_readl(MSC0);
24 msc[1] = __raw_readl(MSC1);
25 sxcnfg = __raw_readl(SXCNFG);
26 memclkcfg = __raw_readl(MEMCLKCFG);
27 csadrcfg[0] = __raw_readl(CSADRCFG0);
28 csadrcfg[1] = __raw_readl(CSADRCFG1);
29 csadrcfg[2] = __raw_readl(CSADRCFG2);
30 csadrcfg[3] = __raw_readl(CSADRCFG3);
eric miaob1d907f2008-01-28 23:00:02 +000031
32 return 0;
33}
34
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +020035static void pxa3xx_smemc_resume(void)
eric miaob1d907f2008-01-28 23:00:02 +000036{
Marek Vasutad68bb92010-11-03 16:29:35 +010037 __raw_writel(msc[0], MSC0);
38 __raw_writel(msc[1], MSC1);
39 __raw_writel(sxcnfg, SXCNFG);
40 __raw_writel(memclkcfg, MEMCLKCFG);
41 __raw_writel(csadrcfg[0], CSADRCFG0);
42 __raw_writel(csadrcfg[1], CSADRCFG1);
43 __raw_writel(csadrcfg[2], CSADRCFG2);
44 __raw_writel(csadrcfg[3], CSADRCFG3);
Igor Grinbergd107a202013-01-13 13:49:47 +020045 /* CSMSADRCFG wakes up in its default state (0), so we need to set it */
46 __raw_writel(0x2, CSMSADRCFG);
eric miaob1d907f2008-01-28 23:00:02 +000047}
48
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +020049static struct syscore_ops smemc_syscore_ops = {
eric miaob1d907f2008-01-28 23:00:02 +000050 .suspend = pxa3xx_smemc_suspend,
51 .resume = pxa3xx_smemc_resume,
52};
53
eric miaob1d907f2008-01-28 23:00:02 +000054static int __init smemc_init(void)
55{
Igor Grinbergd107a202013-01-13 13:49:47 +020056 if (cpu_is_pxa3xx()) {
57 /*
58 * The only documentation we have on the
59 * Chip Select Configuration Register (CSMSADRCFG) is that
60 * it must be programmed to 0x2.
61 * Moreover, in the bit definitions, the second bit
62 * (CSMSADRCFG[1]) is called "SETALWAYS".
63 * Other bits are reserved in this register.
64 */
65 __raw_writel(0x2, CSMSADRCFG);
66
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +020067 register_syscore_ops(&smemc_syscore_ops);
Igor Grinbergd107a202013-01-13 13:49:47 +020068 }
eric miaob1d907f2008-01-28 23:00:02 +000069
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +020070 return 0;
eric miaob1d907f2008-01-28 23:00:02 +000071}
72subsys_initcall(smemc_init);
73#endif
Arnd Bergmannfd13f812019-09-18 17:42:52 +020074
75static const unsigned int df_clkdiv[4] = { 1, 2, 4, 1 };
76unsigned int pxa3xx_smemc_get_memclkdiv(void)
77{
78 unsigned long memclkcfg = __raw_readl(MEMCLKCFG);
79
80 return df_clkdiv[(memclkcfg >> 16) & 0x3];
81}