Linus Walleij | 130a990 | 2018-09-12 14:32:07 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2003-2015 Broadcom Corporation |
| 4 | * All Rights Reserved |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
Linus Walleij | 121111d | 2018-09-12 14:30:59 +0200 | [diff] [blame] | 7 | #include <linux/gpio/driver.h> |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 8 | #include <linux/platform_device.h> |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 9 | #include <linux/module.h> |
| 10 | #include <linux/irq.h> |
| 11 | #include <linux/interrupt.h> |
Kamlakant Patel | 83ea24f | 2015-10-15 18:23:32 +0530 | [diff] [blame] | 12 | #include <linux/irqchip/chained_irq.h> |
Kamlakant Patel | baa1b92 | 2016-06-05 14:00:44 +0530 | [diff] [blame] | 13 | #include <linux/acpi.h> |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 14 | |
| 15 | /* |
| 16 | * XLP GPIO has multiple 32 bit registers for each feature where each register |
| 17 | * controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96 |
| 18 | * require 3 32-bit registers for each feature. |
| 19 | * Here we only define offset of the first register for each feature. Offset of |
| 20 | * the registers for pins greater than 32 can be calculated as following(Use |
| 21 | * GPIO_INT_STAT as example): |
| 22 | * |
| 23 | * offset = (gpio / XLP_GPIO_REGSZ) * 4; |
| 24 | * reg_addr = addr + offset; |
| 25 | * |
| 26 | * where addr is base address of the that feature register and gpio is the pin. |
| 27 | */ |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 28 | #define GPIO_9XX_BYTESWAP 0X00 |
| 29 | #define GPIO_9XX_CTRL 0X04 |
| 30 | #define GPIO_9XX_OUTPUT_EN 0x14 |
| 31 | #define GPIO_9XX_PADDRV 0x24 |
| 32 | /* |
| 33 | * Only for 4 interrupt enable reg are defined for now, |
| 34 | * total reg available are 12. |
| 35 | */ |
| 36 | #define GPIO_9XX_INT_EN00 0x44 |
| 37 | #define GPIO_9XX_INT_EN10 0x54 |
| 38 | #define GPIO_9XX_INT_EN20 0x64 |
| 39 | #define GPIO_9XX_INT_EN30 0x74 |
| 40 | #define GPIO_9XX_INT_POL 0x104 |
| 41 | #define GPIO_9XX_INT_TYPE 0x114 |
| 42 | #define GPIO_9XX_INT_STAT 0x124 |
| 43 | |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 44 | /* Interrupt type register mask */ |
| 45 | #define XLP_GPIO_IRQ_TYPE_LVL 0x0 |
| 46 | #define XLP_GPIO_IRQ_TYPE_EDGE 0x1 |
| 47 | |
| 48 | /* Interrupt polarity register mask */ |
| 49 | #define XLP_GPIO_IRQ_POL_HIGH 0x0 |
| 50 | #define XLP_GPIO_IRQ_POL_LOW 0x1 |
| 51 | |
| 52 | #define XLP_GPIO_REGSZ 32 |
| 53 | #define XLP_GPIO_IRQ_BASE 768 |
| 54 | #define XLP_MAX_NR_GPIO 96 |
| 55 | |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 56 | struct xlp_gpio_priv { |
| 57 | struct gpio_chip chip; |
| 58 | DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO); |
| 59 | void __iomem *gpio_intr_en; /* pointer to first intr enable reg */ |
| 60 | void __iomem *gpio_intr_stat; /* pointer to first intr status reg */ |
| 61 | void __iomem *gpio_intr_type; /* pointer to first intr type reg */ |
| 62 | void __iomem *gpio_intr_pol; /* pointer to first intr polarity reg */ |
| 63 | void __iomem *gpio_out_en; /* pointer to first output enable reg */ |
| 64 | void __iomem *gpio_paddrv; /* pointer to first pad drive reg */ |
| 65 | spinlock_t lock; |
| 66 | }; |
| 67 | |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 68 | static int xlp_gpio_get_reg(void __iomem *addr, unsigned gpio) |
| 69 | { |
| 70 | u32 pos, regset; |
| 71 | |
| 72 | pos = gpio % XLP_GPIO_REGSZ; |
| 73 | regset = (gpio / XLP_GPIO_REGSZ) * 4; |
| 74 | return !!(readl(addr + regset) & BIT(pos)); |
| 75 | } |
| 76 | |
| 77 | static void xlp_gpio_set_reg(void __iomem *addr, unsigned gpio, int state) |
| 78 | { |
| 79 | u32 value, pos, regset; |
| 80 | |
| 81 | pos = gpio % XLP_GPIO_REGSZ; |
| 82 | regset = (gpio / XLP_GPIO_REGSZ) * 4; |
| 83 | value = readl(addr + regset); |
| 84 | |
| 85 | if (state) |
| 86 | value |= BIT(pos); |
| 87 | else |
| 88 | value &= ~BIT(pos); |
| 89 | |
| 90 | writel(value, addr + regset); |
| 91 | } |
| 92 | |
| 93 | static void xlp_gpio_irq_disable(struct irq_data *d) |
| 94 | { |
| 95 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
Linus Walleij | e730a59 | 2015-12-07 15:22:31 +0100 | [diff] [blame] | 96 | struct xlp_gpio_priv *priv = gpiochip_get_data(gc); |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 97 | unsigned long flags; |
| 98 | |
| 99 | spin_lock_irqsave(&priv->lock, flags); |
| 100 | xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0); |
| 101 | __clear_bit(d->hwirq, priv->gpio_enabled_mask); |
| 102 | spin_unlock_irqrestore(&priv->lock, flags); |
| 103 | } |
| 104 | |
| 105 | static void xlp_gpio_irq_mask_ack(struct irq_data *d) |
| 106 | { |
| 107 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
Linus Walleij | e730a59 | 2015-12-07 15:22:31 +0100 | [diff] [blame] | 108 | struct xlp_gpio_priv *priv = gpiochip_get_data(gc); |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 109 | unsigned long flags; |
| 110 | |
| 111 | spin_lock_irqsave(&priv->lock, flags); |
| 112 | xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0); |
| 113 | xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1); |
| 114 | __clear_bit(d->hwirq, priv->gpio_enabled_mask); |
| 115 | spin_unlock_irqrestore(&priv->lock, flags); |
| 116 | } |
| 117 | |
| 118 | static void xlp_gpio_irq_unmask(struct irq_data *d) |
| 119 | { |
| 120 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
Linus Walleij | e730a59 | 2015-12-07 15:22:31 +0100 | [diff] [blame] | 121 | struct xlp_gpio_priv *priv = gpiochip_get_data(gc); |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 122 | unsigned long flags; |
| 123 | |
| 124 | spin_lock_irqsave(&priv->lock, flags); |
| 125 | xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1); |
| 126 | __set_bit(d->hwirq, priv->gpio_enabled_mask); |
| 127 | spin_unlock_irqrestore(&priv->lock, flags); |
| 128 | } |
| 129 | |
| 130 | static int xlp_gpio_set_irq_type(struct irq_data *d, unsigned int type) |
| 131 | { |
| 132 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
Linus Walleij | e730a59 | 2015-12-07 15:22:31 +0100 | [diff] [blame] | 133 | struct xlp_gpio_priv *priv = gpiochip_get_data(gc); |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 134 | int pol, irq_type; |
| 135 | |
| 136 | switch (type) { |
| 137 | case IRQ_TYPE_EDGE_RISING: |
| 138 | irq_type = XLP_GPIO_IRQ_TYPE_EDGE; |
| 139 | pol = XLP_GPIO_IRQ_POL_HIGH; |
| 140 | break; |
| 141 | case IRQ_TYPE_EDGE_FALLING: |
| 142 | irq_type = XLP_GPIO_IRQ_TYPE_EDGE; |
| 143 | pol = XLP_GPIO_IRQ_POL_LOW; |
| 144 | break; |
| 145 | case IRQ_TYPE_LEVEL_HIGH: |
| 146 | irq_type = XLP_GPIO_IRQ_TYPE_LVL; |
| 147 | pol = XLP_GPIO_IRQ_POL_HIGH; |
| 148 | break; |
| 149 | case IRQ_TYPE_LEVEL_LOW: |
| 150 | irq_type = XLP_GPIO_IRQ_TYPE_LVL; |
| 151 | pol = XLP_GPIO_IRQ_POL_LOW; |
| 152 | break; |
| 153 | default: |
| 154 | return -EINVAL; |
| 155 | } |
| 156 | |
| 157 | xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type); |
| 158 | xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol); |
| 159 | |
| 160 | return 0; |
| 161 | } |
| 162 | |
| 163 | static struct irq_chip xlp_gpio_irq_chip = { |
| 164 | .name = "XLP-GPIO", |
| 165 | .irq_mask_ack = xlp_gpio_irq_mask_ack, |
| 166 | .irq_disable = xlp_gpio_irq_disable, |
| 167 | .irq_set_type = xlp_gpio_set_irq_type, |
| 168 | .irq_unmask = xlp_gpio_irq_unmask, |
| 169 | .flags = IRQCHIP_ONESHOT_SAFE, |
| 170 | }; |
| 171 | |
Kamlakant Patel | 83ea24f | 2015-10-15 18:23:32 +0530 | [diff] [blame] | 172 | static void xlp_gpio_generic_handler(struct irq_desc *desc) |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 173 | { |
Kamlakant Patel | 83ea24f | 2015-10-15 18:23:32 +0530 | [diff] [blame] | 174 | struct xlp_gpio_priv *priv = irq_desc_get_handler_data(desc); |
| 175 | struct irq_chip *irqchip = irq_desc_get_chip(desc); |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 176 | int gpio, regoff; |
| 177 | u32 gpio_stat; |
| 178 | |
| 179 | regoff = -1; |
| 180 | gpio_stat = 0; |
Kamlakant Patel | 83ea24f | 2015-10-15 18:23:32 +0530 | [diff] [blame] | 181 | |
| 182 | chained_irq_enter(irqchip, desc); |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 183 | for_each_set_bit(gpio, priv->gpio_enabled_mask, XLP_MAX_NR_GPIO) { |
| 184 | if (regoff != gpio / XLP_GPIO_REGSZ) { |
| 185 | regoff = gpio / XLP_GPIO_REGSZ; |
| 186 | gpio_stat = readl(priv->gpio_intr_stat + regoff * 4); |
| 187 | } |
Kamlakant Patel | 83ea24f | 2015-10-15 18:23:32 +0530 | [diff] [blame] | 188 | |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 189 | if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ)) |
Marc Zyngier | dbd1c54 | 2021-05-04 17:42:18 +0100 | [diff] [blame] | 190 | generic_handle_domain_irq(priv->chip.irq.domain, gpio); |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 191 | } |
Kamlakant Patel | 83ea24f | 2015-10-15 18:23:32 +0530 | [diff] [blame] | 192 | chained_irq_exit(irqchip, desc); |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 193 | } |
| 194 | |
| 195 | static int xlp_gpio_dir_output(struct gpio_chip *gc, unsigned gpio, int state) |
| 196 | { |
Linus Walleij | e730a59 | 2015-12-07 15:22:31 +0100 | [diff] [blame] | 197 | struct xlp_gpio_priv *priv = gpiochip_get_data(gc); |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 198 | |
| 199 | BUG_ON(gpio >= gc->ngpio); |
| 200 | xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1); |
| 201 | |
| 202 | return 0; |
| 203 | } |
| 204 | |
| 205 | static int xlp_gpio_dir_input(struct gpio_chip *gc, unsigned gpio) |
| 206 | { |
Linus Walleij | e730a59 | 2015-12-07 15:22:31 +0100 | [diff] [blame] | 207 | struct xlp_gpio_priv *priv = gpiochip_get_data(gc); |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 208 | |
| 209 | BUG_ON(gpio >= gc->ngpio); |
| 210 | xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0); |
| 211 | |
| 212 | return 0; |
| 213 | } |
| 214 | |
| 215 | static int xlp_gpio_get(struct gpio_chip *gc, unsigned gpio) |
| 216 | { |
Linus Walleij | e730a59 | 2015-12-07 15:22:31 +0100 | [diff] [blame] | 217 | struct xlp_gpio_priv *priv = gpiochip_get_data(gc); |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 218 | |
| 219 | BUG_ON(gpio >= gc->ngpio); |
| 220 | return xlp_gpio_get_reg(priv->gpio_paddrv, gpio); |
| 221 | } |
| 222 | |
| 223 | static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state) |
| 224 | { |
Linus Walleij | e730a59 | 2015-12-07 15:22:31 +0100 | [diff] [blame] | 225 | struct xlp_gpio_priv *priv = gpiochip_get_data(gc); |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 226 | |
| 227 | BUG_ON(gpio >= gc->ngpio); |
| 228 | xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state); |
| 229 | } |
| 230 | |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 231 | static int xlp_gpio_probe(struct platform_device *pdev) |
| 232 | { |
| 233 | struct gpio_chip *gc; |
Linus Walleij | c7e66e4 | 2019-08-09 15:51:19 +0200 | [diff] [blame] | 234 | struct gpio_irq_chip *girq; |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 235 | struct xlp_gpio_priv *priv; |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 236 | void __iomem *gpio_base; |
Rob Herring | ea708ac5 | 2021-11-09 10:12:53 -0600 | [diff] [blame] | 237 | int irq, err; |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 238 | |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 239 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
| 240 | if (!priv) |
| 241 | return -ENOMEM; |
| 242 | |
Enrico Weigelt, metux IT consult | 3883de0 | 2019-03-11 19:55:20 +0100 | [diff] [blame] | 243 | gpio_base = devm_platform_ioremap_resource(pdev, 0); |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 244 | if (IS_ERR(gpio_base)) |
| 245 | return PTR_ERR(gpio_base); |
| 246 | |
| 247 | irq = platform_get_irq(pdev, 0); |
| 248 | if (irq < 0) |
| 249 | return irq; |
| 250 | |
Rob Herring | ea708ac5 | 2021-11-09 10:12:53 -0600 | [diff] [blame] | 251 | priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN; |
| 252 | priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV; |
| 253 | priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT; |
| 254 | priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE; |
| 255 | priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL; |
| 256 | priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00; |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 257 | |
| 258 | bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO); |
| 259 | |
| 260 | gc = &priv->chip; |
| 261 | |
Axel Lin | b8a3f52 | 2015-05-07 15:34:37 +0800 | [diff] [blame] | 262 | gc->owner = THIS_MODULE; |
| 263 | gc->label = dev_name(&pdev->dev); |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 264 | gc->base = 0; |
Linus Walleij | 58383c78 | 2015-11-04 09:56:26 +0100 | [diff] [blame] | 265 | gc->parent = &pdev->dev; |
Rob Herring | ea708ac5 | 2021-11-09 10:12:53 -0600 | [diff] [blame] | 266 | gc->ngpio = 70; |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 267 | gc->direction_output = xlp_gpio_dir_output; |
| 268 | gc->direction_input = xlp_gpio_dir_input; |
| 269 | gc->set = xlp_gpio_set; |
| 270 | gc->get = xlp_gpio_get; |
| 271 | |
| 272 | spin_lock_init(&priv->lock); |
Kamlakant Patel | 1630a06 | 2016-06-05 14:00:43 +0530 | [diff] [blame] | 273 | |
Linus Walleij | c7e66e4 | 2019-08-09 15:51:19 +0200 | [diff] [blame] | 274 | girq = &gc->irq; |
| 275 | girq->chip = &xlp_gpio_irq_chip; |
| 276 | girq->parent_handler = xlp_gpio_generic_handler; |
| 277 | girq->num_parents = 1; |
| 278 | girq->parents = devm_kcalloc(&pdev->dev, 1, |
| 279 | sizeof(*girq->parents), |
| 280 | GFP_KERNEL); |
| 281 | if (!girq->parents) |
| 282 | return -ENOMEM; |
| 283 | girq->parents[0] = irq; |
Rob Herring | ea708ac5 | 2021-11-09 10:12:53 -0600 | [diff] [blame] | 284 | girq->first = 0; |
Linus Walleij | c7e66e4 | 2019-08-09 15:51:19 +0200 | [diff] [blame] | 285 | girq->default_type = IRQ_TYPE_NONE; |
| 286 | girq->handler = handle_level_irq; |
| 287 | |
Linus Walleij | e730a59 | 2015-12-07 15:22:31 +0100 | [diff] [blame] | 288 | err = gpiochip_add_data(gc, priv); |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 289 | if (err < 0) |
Bartosz Golaszewski | 31bd86d | 2017-03-04 17:23:34 +0100 | [diff] [blame] | 290 | return err; |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 291 | |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 292 | dev_info(&pdev->dev, "registered %d GPIOs\n", gc->ngpio); |
| 293 | |
| 294 | return 0; |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 295 | } |
| 296 | |
Kamlakant Patel | baa1b92 | 2016-06-05 14:00:44 +0530 | [diff] [blame] | 297 | #ifdef CONFIG_ACPI |
| 298 | static const struct acpi_device_id xlp_gpio_acpi_match[] = { |
Rob Herring | e320d9c | 2021-12-01 15:43:05 -0600 | [diff] [blame] | 299 | { "BRCM9006" }, |
| 300 | { "CAV9006" }, |
Kamlakant Patel | baa1b92 | 2016-06-05 14:00:44 +0530 | [diff] [blame] | 301 | {}, |
| 302 | }; |
| 303 | MODULE_DEVICE_TABLE(acpi, xlp_gpio_acpi_match); |
| 304 | #endif |
| 305 | |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 306 | static struct platform_driver xlp_gpio_driver = { |
| 307 | .driver = { |
| 308 | .name = "xlp-gpio", |
Kamlakant Patel | baa1b92 | 2016-06-05 14:00:44 +0530 | [diff] [blame] | 309 | .acpi_match_table = ACPI_PTR(xlp_gpio_acpi_match), |
Kamlakant Patel | ff71880 | 2015-04-28 20:10:45 +0530 | [diff] [blame] | 310 | }, |
| 311 | .probe = xlp_gpio_probe, |
| 312 | }; |
| 313 | module_platform_driver(xlp_gpio_driver); |
| 314 | |
| 315 | MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>"); |
| 316 | MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>"); |
| 317 | MODULE_DESCRIPTION("Netlogic XLP GPIO Driver"); |
| 318 | MODULE_LICENSE("GPL v2"); |