blob: 514dd056c2c84b58cec5a2353c87ebc1917eb2fd [file] [log] [blame]
Thomas Gleixner1a59d1b82019-05-27 08:55:05 +02001/* SPDX-License-Identifier: GPL-2.0-or-later */
Linas Vepstas172ca922005-11-03 18:50:04 -06002/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 * Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation.
Gavin Shancb3bc9d2012-02-27 20:03:51 +00004 * Copyright 2001-2012 IBM Corporation.
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 */
6
Benjamin Herrenschmidt8b8da352008-10-27 19:48:37 +00007#ifndef _POWERPC_EEH_H
8#define _POWERPC_EEH_H
Arnd Bergmann88ced032005-12-16 22:43:46 +01009#ifdef __KERNEL__
Linus Torvalds1da177e2005-04-16 15:20:36 -070010
Linus Torvalds1da177e2005-04-16 15:20:36 -070011#include <linux/init.h>
12#include <linux/list.h>
13#include <linux/string.h>
Gavin Shan5a719782013-06-20 13:21:01 +080014#include <linux/time.h>
Gavin Shan05ec4242014-06-10 11:41:55 +100015#include <linux/atomic.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070016
Gavin Shaned3e81f2015-03-26 16:42:07 +110017#include <uapi/asm/eeh.h>
18
Linus Torvalds1da177e2005-04-16 15:20:36 -070019struct pci_dev;
John Rose827c1a62006-02-24 11:34:23 -060020struct pci_bus;
Gavin Shane8e9b342015-03-17 16:15:05 +110021struct pci_dn;
Linus Torvalds1da177e2005-04-16 15:20:36 -070022
23#ifdef CONFIG_EEH
24
Gavin Shan8a5ad352014-04-24 18:00:17 +100025/* EEH subsystem flags */
Mauro S. M. Rodriguesee8c4462018-03-22 23:10:52 -030026#define EEH_ENABLED 0x01 /* EEH enabled */
27#define EEH_FORCE_DISABLED 0x02 /* EEH disabled */
28#define EEH_PROBE_MODE_DEV 0x04 /* From PCI device */
29#define EEH_PROBE_MODE_DEVTREE 0x08 /* From device tree */
Mauro S. M. Rodriguesee8c4462018-03-22 23:10:52 -030030#define EEH_ENABLE_IO_FOR_LOG 0x20 /* Enable IO for log */
31#define EEH_EARLY_DUMP_LOG 0x40 /* Dump log immediately */
Gavin Shan8a5ad352014-04-24 18:00:17 +100032
Gavin Shanaa1e6372012-02-27 20:03:53 +000033/*
Gavin Shan26833a52014-04-24 18:00:23 +100034 * Delay for PE reset, all in ms
35 *
36 * PCI specification has reset hold time of 100 milliseconds.
37 * We have 250 milliseconds here. The PCI bus settlement time
38 * is specified as 1.5 seconds and we have 1.8 seconds.
39 */
40#define EEH_PE_RST_HOLD_TIME 250
41#define EEH_PE_RST_SETTLE_TIME 1800
42
43/*
Gavin Shan968f9682012-09-07 22:44:05 +000044 * The struct is used to trace PE related EEH functionality.
45 * In theory, there will have one instance of the struct to
Michael Ellerman027dfac2016-06-01 16:34:37 +100046 * be created against particular PE. In nature, PEs correlate
Gavin Shan968f9682012-09-07 22:44:05 +000047 * to each other. the struct has to reflect that hierarchy in
48 * order to easily pick up those affected PEs when one particular
49 * PE has EEH errors.
50 *
51 * Also, one particular PE might be composed of PCI device, PCI
52 * bus and its subordinate components. The struct also need ship
53 * the information. Further more, one particular PE is only meaingful
54 * in the corresponding PHB. Therefore, the root PEs should be created
55 * against existing PHBs in on-to-one fashion.
56 */
Gavin Shan5efc3ad2012-09-11 19:16:16 +000057#define EEH_PE_INVALID (1 << 0) /* Invalid */
58#define EEH_PE_PHB (1 << 1) /* PHB PE */
59#define EEH_PE_DEVICE (1 << 2) /* Device PE */
60#define EEH_PE_BUS (1 << 3) /* Bus PE */
Wei Yangc29fa272016-03-04 10:53:08 +110061#define EEH_PE_VF (1 << 4) /* VF PE */
Gavin Shan968f9682012-09-07 22:44:05 +000062
63#define EEH_PE_ISOLATED (1 << 0) /* Isolated PE */
64#define EEH_PE_RECOVERING (1 << 1) /* Recovering PE */
Gavin Shan8a6b3712014-10-01 17:07:50 +100065#define EEH_PE_CFG_BLOCKED (1 << 2) /* Block config access */
Gavin Shan28bf36f2014-11-14 10:47:29 +110066#define EEH_PE_RESET (1 << 3) /* PE reset in progress */
Gavin Shan968f9682012-09-07 22:44:05 +000067
Gavin Shan807a8272013-07-24 10:24:55 +080068#define EEH_PE_KEEP (1 << 8) /* Keep PE on hotplug */
Gavin Shanb6541db2014-10-01 17:07:53 +100069#define EEH_PE_CFG_RESTRICTED (1 << 9) /* Block config on error */
Gavin Shan432227e2014-12-11 14:28:55 +110070#define EEH_PE_REMOVED (1 << 10) /* Removed permanently */
Gavin Shan05ba75f2016-02-09 15:50:21 +110071#define EEH_PE_PRI_BUS (1 << 11) /* Cached primary bus */
Gavin Shan807a8272013-07-24 10:24:55 +080072
Gavin Shan968f9682012-09-07 22:44:05 +000073struct eeh_pe {
74 int type; /* PE type: PHB/Bus/Device */
75 int state; /* PE EEH dependent mode */
Gavin Shan968f9682012-09-07 22:44:05 +000076 int addr; /* PE configuration address */
77 struct pci_controller *phb; /* Associated PHB */
Gavin Shan8cdb2832013-06-20 13:20:55 +080078 struct pci_bus *bus; /* Top PCI bus for bus PE */
Gavin Shan968f9682012-09-07 22:44:05 +000079 int check_count; /* Times of ignored error */
80 int freeze_count; /* Times of froze up */
Arnd Bergmannedfd17f2017-11-04 22:26:52 +010081 time64_t tstamp; /* Time on first-time freeze */
Gavin Shan968f9682012-09-07 22:44:05 +000082 int false_positives; /* Times of reported #ff's */
Gavin Shan05ec4242014-06-10 11:41:55 +100083 atomic_t pass_dev_cnt; /* Count of passed through devs */
Gavin Shan968f9682012-09-07 22:44:05 +000084 struct eeh_pe *parent; /* Parent PE */
Gavin Shanbb593c02014-07-17 14:41:43 +100085 void *data; /* PE auxillary data */
Sam Bobroff80e65b02018-09-12 11:23:26 +100086 struct list_head child_list; /* List of PEs below this PE */
87 struct list_head child; /* Memb. child_list/eeh_phb_pe */
88 struct list_head edevs; /* List of eeh_dev in this PE */
Oliver O'Halloran25baf3d2019-09-03 20:15:56 +100089
Michael Ellerman1b7f3b6c2019-09-13 23:32:13 +100090#ifdef CONFIG_STACKTRACE
Oliver O'Halloran25baf3d2019-09-03 20:15:56 +100091 /*
92 * Saved stack trace. When we find a PE freeze in eeh_dev_check_failure
93 * the stack trace is saved here so we can print it in the recovery
94 * thread if it turns out to due to a real problem rather than
95 * a hot-remove.
96 *
97 * A max of 64 entries might be overkill, but it also might not be.
98 */
99 unsigned long stack_trace[64];
100 int trace_entries;
Michael Ellerman1b7f3b6c2019-09-13 23:32:13 +1000101#endif /* CONFIG_STACKTRACE */
Gavin Shan968f9682012-09-07 22:44:05 +0000102};
103
Gavin Shan9feed422013-07-24 10:24:56 +0800104#define eeh_pe_for_each_dev(pe, edev, tmp) \
Sam Bobroff80e65b02018-09-12 11:23:26 +1000105 list_for_each_entry_safe(edev, tmp, &pe->edevs, entry)
Gavin Shan5b663522012-09-07 22:44:12 +0000106
Sam Bobroff309ed3a2018-05-25 13:11:35 +1000107#define eeh_for_each_pe(root, pe) \
108 for (pe = root; pe; pe = eeh_pe_next(pe, root))
109
Gavin Shan05ec4242014-06-10 11:41:55 +1000110static inline bool eeh_pe_passed(struct eeh_pe *pe)
111{
112 return pe ? !!atomic_read(&pe->pass_dev_cnt) : false;
113}
114
Gavin Shan968f9682012-09-07 22:44:05 +0000115/*
Gavin Shaneb740b52012-02-27 20:04:04 +0000116 * The struct is used to trace EEH state for the associated
117 * PCI device node or PCI device. In future, it might
118 * represent PE as well so that the EEH device to form
119 * another tree except the currently existing tree of PCI
120 * buses and PCI devices
121 */
Gavin Shan4b83bd42013-07-24 10:24:59 +0800122#define EEH_DEV_BRIDGE (1 << 0) /* PCI bridge */
123#define EEH_DEV_ROOT_PORT (1 << 1) /* PCIe root port */
124#define EEH_DEV_DS_PORT (1 << 2) /* Downstream port */
125#define EEH_DEV_IRQ_DISABLED (1 << 3) /* Interrupt disabled */
126#define EEH_DEV_DISCONNECTED (1 << 4) /* Removing from PE */
Gavin Shaneb740b52012-02-27 20:04:04 +0000127
Gavin Shanf26c7a02014-01-12 14:13:45 +0800128#define EEH_DEV_NO_HANDLER (1 << 8) /* No error handler */
129#define EEH_DEV_SYSFS (1 << 9) /* Sysfs created */
Gavin Shand2b0f6f2014-04-24 18:00:19 +1000130#define EEH_DEV_REMOVED (1 << 10) /* Removed permanently */
Gavin Shanab55d212013-07-24 10:25:01 +0800131
Gavin Shaneb740b52012-02-27 20:04:04 +0000132struct eeh_dev {
133 int mode; /* EEH mode */
Oliver O'Halloran7c33a992019-08-16 14:48:11 +1000134 int bdfn; /* bdfn of device (for cfg ops) */
135 struct pci_controller *controller;
Gavin Shaneb740b52012-02-27 20:04:04 +0000136 int pe_config_addr; /* PE config address */
Gavin Shaneb740b52012-02-27 20:04:04 +0000137 u32 config_space[16]; /* Saved PCI config space */
Gavin Shan2a18dfc2014-04-24 18:00:16 +1000138 int pcix_cap; /* Saved PCIx capability */
139 int pcie_cap; /* Saved PCIe capability */
140 int aer_cap; /* Saved AER capability */
Wei Yang9312bc52016-03-04 10:53:09 +1100141 int af_cap; /* Saved AF capability */
Gavin Shan968f9682012-09-07 22:44:05 +0000142 struct eeh_pe *pe; /* Associated PE */
Sam Bobroff80e65b02018-09-12 11:23:26 +1000143 struct list_head entry; /* Membership in eeh_pe.edevs */
144 struct list_head rmv_entry; /* Membership in rmv_list */
Gavin Shane8e9b342015-03-17 16:15:05 +1100145 struct pci_dn *pdn; /* Associated PCI device node */
Gavin Shaneb740b52012-02-27 20:04:04 +0000146 struct pci_dev *pdev; /* Associated PCI device */
Wei Yang67086e32016-03-04 10:53:11 +1100147 bool in_error; /* Error flag for edev */
Oliver O'Hallorandffa9152020-07-25 18:12:20 +1000148
149 /* VF specific properties */
Wei Yang39218cd2016-03-04 10:53:07 +1100150 struct pci_dev *physfn; /* Associated SRIOV PF */
Oliver O'Hallorandffa9152020-07-25 18:12:20 +1000151 int vf_index; /* Index of this VF */
Gavin Shaneb740b52012-02-27 20:04:04 +0000152};
153
Sam Bobroffb093f2c2019-08-16 14:48:12 +1000154/* "fmt" must be a simple literal string */
155#define EEH_EDEV_PRINT(level, edev, fmt, ...) \
156 pr_##level("PCI %04x:%02x:%02x.%x#%04x: EEH: " fmt, \
157 (edev)->controller->global_number, PCI_BUSNO((edev)->bdfn), \
158 PCI_SLOT((edev)->bdfn), PCI_FUNC((edev)->bdfn), \
159 ((edev)->pe ? (edev)->pe_config_addr : 0xffff), ##__VA_ARGS__)
160#define eeh_edev_dbg(edev, fmt, ...) EEH_EDEV_PRINT(debug, (edev), fmt, ##__VA_ARGS__)
161#define eeh_edev_info(edev, fmt, ...) EEH_EDEV_PRINT(info, (edev), fmt, ##__VA_ARGS__)
162#define eeh_edev_warn(edev, fmt, ...) EEH_EDEV_PRINT(warn, (edev), fmt, ##__VA_ARGS__)
163#define eeh_edev_err(edev, fmt, ...) EEH_EDEV_PRINT(err, (edev), fmt, ##__VA_ARGS__)
164
Gavin Shane8e9b342015-03-17 16:15:05 +1100165static inline struct pci_dn *eeh_dev_to_pdn(struct eeh_dev *edev)
166{
167 return edev ? edev->pdn : NULL;
168}
169
Gavin Shaneb740b52012-02-27 20:04:04 +0000170static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
171{
Gavin Shan2d5c1212013-06-05 15:34:03 +0800172 return edev ? edev->pdev : NULL;
Gavin Shaneb740b52012-02-27 20:04:04 +0000173}
174
Wei Yang2a582222014-09-17 10:48:26 +0800175static inline struct eeh_pe *eeh_dev_to_pe(struct eeh_dev* edev)
176{
177 return edev ? edev->pe : NULL;
178}
179
Gavin Shan7e4e7862014-01-15 13:16:11 +0800180/* Return values from eeh_ops::next_error */
181enum {
182 EEH_NEXT_ERR_NONE = 0,
183 EEH_NEXT_ERR_INF,
184 EEH_NEXT_ERR_FROZEN_PE,
185 EEH_NEXT_ERR_FENCED_PHB,
186 EEH_NEXT_ERR_DEAD_PHB,
187 EEH_NEXT_ERR_DEAD_IOC
188};
189
Gavin Shaneb740b52012-02-27 20:04:04 +0000190/*
Gavin Shanaa1e6372012-02-27 20:03:53 +0000191 * The struct is used to trace the registered EEH operation
192 * callback functions. Actually, those operation callback
193 * functions are heavily platform dependent. That means the
194 * platform should register its own EEH operation callback
195 * functions before any EEH further operations.
196 */
Gavin Shan8fb8f7092012-02-27 20:03:55 +0000197#define EEH_OPT_DISABLE 0 /* EEH disable */
198#define EEH_OPT_ENABLE 1 /* EEH enable */
199#define EEH_OPT_THAW_MMIO 2 /* MMIO enable */
200#define EEH_OPT_THAW_DMA 3 /* DMA enable */
Gavin Shan0d5ee522014-09-30 12:38:52 +1000201#define EEH_OPT_FREEZE_PE 4 /* Freeze PE */
Gavin Shaneb594a42012-02-27 20:03:57 +0000202#define EEH_STATE_UNAVAILABLE (1 << 0) /* State unavailable */
203#define EEH_STATE_NOT_SUPPORT (1 << 1) /* EEH not supported */
204#define EEH_STATE_RESET_ACTIVE (1 << 2) /* Active reset */
205#define EEH_STATE_MMIO_ACTIVE (1 << 3) /* Active MMIO */
206#define EEH_STATE_DMA_ACTIVE (1 << 4) /* Active DMA */
207#define EEH_STATE_MMIO_ENABLED (1 << 5) /* MMIO enabled */
208#define EEH_STATE_DMA_ENABLED (1 << 6) /* DMA enabled */
Gavin Shan26524812012-02-27 20:03:59 +0000209#define EEH_RESET_DEACTIVATE 0 /* Deactivate the PE reset */
210#define EEH_RESET_HOT 1 /* Hot reset */
211#define EEH_RESET_FUNDAMENTAL 3 /* Fundamental reset */
Gavin Shan8d633292012-02-27 20:04:00 +0000212#define EEH_LOG_TEMP 1 /* EEH temporary error log */
213#define EEH_LOG_PERM 2 /* EEH permanent error log */
Gavin Shaneb594a42012-02-27 20:03:57 +0000214
Gavin Shanaa1e6372012-02-27 20:03:53 +0000215struct eeh_ops {
216 char *name;
Oliver O'Hallorane86350f72020-03-06 18:39:04 +1100217 struct eeh_dev *(*probe)(struct pci_dev *pdev);
Gavin Shan371a3952012-09-07 22:44:14 +0000218 int (*set_option)(struct eeh_pe *pe, int option);
Sam Bobrofffef7f902018-09-12 11:23:32 +1000219 int (*get_state)(struct eeh_pe *pe, int *delay);
Gavin Shan371a3952012-09-07 22:44:14 +0000220 int (*reset)(struct eeh_pe *pe, int option);
Gavin Shan371a3952012-09-07 22:44:14 +0000221 int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
222 int (*configure_bridge)(struct eeh_pe *pe);
Gavin Shan131c1232014-09-30 12:38:56 +1000223 int (*err_inject)(struct eeh_pe *pe, int type, int func,
224 unsigned long addr, unsigned long mask);
Oliver O'Halloran17d2a482020-07-25 18:12:26 +1000225 int (*read_config)(struct eeh_dev *edev, int where, int size, u32 *val);
226 int (*write_config)(struct eeh_dev *edev, int where, int size, u32 val);
Gavin Shan8a6b1bc2013-06-20 13:21:04 +0800227 int (*next_error)(struct eeh_pe **pe);
Oliver O'Halloran0c2c7652020-07-25 18:12:24 +1000228 int (*restore_config)(struct eeh_dev *edev);
Oliver O'Halloran8225d542020-07-25 18:12:25 +1000229 int (*notify_resume)(struct eeh_dev *edev);
Gavin Shanaa1e6372012-02-27 20:03:53 +0000230};
231
Gavin Shan8a5ad352014-04-24 18:00:17 +1000232extern int eeh_subsystem_flags;
Oliver O'Halloran46ee7c32019-02-15 11:48:11 +1100233extern u32 eeh_max_freezes;
Oliver O'Halloran6b493f62019-02-15 11:48:16 +1100234extern bool eeh_debugfs_no_recover;
Gavin Shanaa1e6372012-02-27 20:03:53 +0000235extern struct eeh_ops *eeh_ops;
Gavin Shan49075812013-06-20 13:21:03 +0800236extern raw_spinlock_t confirm_error_lock;
Gavin Shand7bb8862012-09-07 22:44:21 +0000237
Gavin Shan05b17212014-07-17 14:41:38 +1000238static inline void eeh_add_flag(int flag)
Gavin Shand7bb8862012-09-07 22:44:21 +0000239{
Gavin Shan8a5ad352014-04-24 18:00:17 +1000240 eeh_subsystem_flags |= flag;
Gavin Shand7bb8862012-09-07 22:44:21 +0000241}
242
Gavin Shan05b17212014-07-17 14:41:38 +1000243static inline void eeh_clear_flag(int flag)
Gavin Shand7bb8862012-09-07 22:44:21 +0000244{
Gavin Shan05b17212014-07-17 14:41:38 +1000245 eeh_subsystem_flags &= ~flag;
Gavin Shand7bb8862012-09-07 22:44:21 +0000246}
247
Gavin Shan05b17212014-07-17 14:41:38 +1000248static inline bool eeh_has_flag(int flag)
Gavin Shand7bb8862012-09-07 22:44:21 +0000249{
Gavin Shan05b17212014-07-17 14:41:38 +1000250 return !!(eeh_subsystem_flags & flag);
251}
252
253static inline bool eeh_enabled(void)
254{
Sam Bobroff54644922018-09-12 11:23:29 +1000255 return eeh_has_flag(EEH_ENABLED) && !eeh_has_flag(EEH_FORCE_DISABLED);
Gavin Shand7bb8862012-09-07 22:44:21 +0000256}
Gavin Shan646a8492012-09-07 22:44:06 +0000257
Gavin Shan49075812013-06-20 13:21:03 +0800258static inline void eeh_serialize_lock(unsigned long *flags)
259{
260 raw_spin_lock_irqsave(&confirm_error_lock, *flags);
261}
262
263static inline void eeh_serialize_unlock(unsigned long flags)
264{
265 raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
266}
267
Sam Bobroff34a286a2018-03-19 13:49:23 +1100268static inline bool eeh_state_active(int state)
269{
270 return (state & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE))
271 == (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
272}
273
Sam Bobroffcef50c62019-08-16 14:48:15 +1000274typedef void (*eeh_edev_traverse_func)(struct eeh_dev *edev, void *flag);
Sam Bobroffd6c49322018-05-25 13:11:32 +1000275typedef void *(*eeh_pe_traverse_func)(struct eeh_pe *pe, void *flag);
Gavin Shanbb593c02014-07-17 14:41:43 +1000276void eeh_set_pe_aux_size(int size);
Greg Kroah-Hartmancad5cef2012-12-21 14:04:10 -0800277int eeh_phb_pe_create(struct pci_controller *phb);
Sam Bobrofffef7f902018-09-12 11:23:32 +1000278int eeh_wait_state(struct eeh_pe *pe, int max_wait);
Gavin Shan9ff67432013-06-20 13:20:53 +0800279struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
Sam Bobroff309ed3a2018-05-25 13:11:35 +1000280struct eeh_pe *eeh_pe_next(struct eeh_pe *pe, struct eeh_pe *root);
Oliver O'Halloran35d64732020-09-18 19:30:50 +1000281struct eeh_pe *eeh_pe_get(struct pci_controller *phb, int pe_no);
Oliver O'Hallorana131bfc2020-07-25 18:12:31 +1000282int eeh_pe_tree_insert(struct eeh_dev *edev, struct eeh_pe *new_pe_parent);
Oliver O'Hallorand923ab72020-07-25 18:12:29 +1000283int eeh_pe_tree_remove(struct eeh_dev *edev);
Gavin Shan5a719782013-06-20 13:21:01 +0800284void eeh_pe_update_time_stamp(struct eeh_pe *pe);
Gavin Shanf5c57712013-07-24 10:24:58 +0800285void *eeh_pe_traverse(struct eeh_pe *root,
Sam Bobroffd6c49322018-05-25 13:11:32 +1000286 eeh_pe_traverse_func fn, void *flag);
Sam Bobroffcef50c62019-08-16 14:48:15 +1000287void eeh_pe_dev_traverse(struct eeh_pe *root,
288 eeh_edev_traverse_func fn, void *flag);
Gavin Shan9e6d2cf2012-09-07 22:44:15 +0000289void eeh_pe_restore_bars(struct eeh_pe *pe);
Gavin Shan357b2f32014-06-11 18:26:44 +1000290const char *eeh_pe_loc_get(struct eeh_pe *pe);
Gavin Shan9b3c76f2012-09-07 22:44:19 +0000291struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
Gavin Shan55037d12012-09-07 22:44:07 +0000292
Sam Bobroffc44e4cc2019-08-16 14:48:10 +1000293void eeh_show_enabled(void);
Oliver O'Hallorand125aed2020-09-18 19:30:42 +1000294int __init eeh_init(struct eeh_ops *ops);
Gavin Shan3e938052014-09-30 12:38:50 +1000295int eeh_check_failure(const volatile void __iomem *token);
Gavin Shanf8f7d632012-09-07 22:44:22 +0000296int eeh_dev_check_failure(struct eeh_dev *edev);
Sam Bobroff685a0bc2019-08-16 14:48:08 +1000297void eeh_addr_cache_init(void);
Oliver O'Hallorane86350f72020-03-06 18:39:04 +1100298void eeh_probe_device(struct pci_dev *pdev);
Gavin Shan807a8272013-07-24 10:24:55 +0800299void eeh_remove_device(struct pci_dev *);
Sam Bobroff188fdea2018-11-29 14:16:38 +1100300int eeh_unfreeze_pe(struct eeh_pe *pe);
Gavin Shan5cfb20b2014-09-30 12:39:07 +1000301int eeh_pe_reset_and_recover(struct eeh_pe *pe);
Gavin Shan212d16c2014-06-10 11:41:56 +1000302int eeh_dev_open(struct pci_dev *pdev);
303void eeh_dev_release(struct pci_dev *pdev);
304struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group);
305int eeh_pe_set_option(struct eeh_pe *pe, int option);
306int eeh_pe_get_state(struct eeh_pe *pe);
Sam Bobroff1ef52072018-11-29 14:16:41 +1100307int eeh_pe_reset(struct eeh_pe *pe, int option, bool include_passed);
Gavin Shan212d16c2014-06-10 11:41:56 +1000308int eeh_pe_configure(struct eeh_pe *pe);
Gavin Shanec33d362015-03-26 16:42:08 +1100309int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
310 unsigned long addr, unsigned long mask);
Linas Vepstase2a296e2005-11-03 18:51:31 -0600311
312/**
Linus Torvalds1da177e2005-04-16 15:20:36 -0700313 * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
314 *
315 * If this macro yields TRUE, the caller relays to eeh_check_failure()
316 * which does further tests out of line.
317 */
Gavin Shan2ec5a0a2014-02-12 15:24:55 +0800318#define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_enabled())
Linus Torvalds1da177e2005-04-16 15:20:36 -0700319
320/*
321 * Reads from a device which has been isolated by EEH will return
322 * all 1s. This macro gives an all-1s value of the given size (in
323 * bytes: 1, 2, or 4) for comparing with the result of a read.
324 */
325#define EEH_IO_ERROR_VALUE(size) (~0U >> ((4 - (size)) * 8))
326
327#else /* !CONFIG_EEH */
Gavin Shaneb740b52012-02-27 20:04:04 +0000328
Gavin Shan2ec5a0a2014-02-12 15:24:55 +0800329static inline bool eeh_enabled(void)
330{
331 return false;
332}
333
Sam Bobroffc44e4cc2019-08-16 14:48:10 +1000334static inline void eeh_show_enabled(void) { }
Gavin Shan51fb5f52013-06-20 13:20:56 +0800335
Gavin Shan3e938052014-09-30 12:38:50 +1000336static inline int eeh_check_failure(const volatile void __iomem *token)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700337{
Gavin Shan3e938052014-09-30 12:38:50 +1000338 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700339}
340
Gavin Shanf8f7d632012-09-07 22:44:22 +0000341#define eeh_dev_check_failure(x) (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700342
Sam Bobroff685a0bc2019-08-16 14:48:08 +1000343static inline void eeh_addr_cache_init(void) { }
344
Oliver O'Hallorane86350f72020-03-06 18:39:04 +1100345static inline void eeh_probe_device(struct pci_dev *dev) { }
Gavin Shanf2856492013-07-24 10:24:52 +0800346
Gavin Shan807a8272013-07-24 10:24:55 +0800347static inline void eeh_remove_device(struct pci_dev *dev) { }
Gavin Shan646a8492012-09-07 22:44:06 +0000348
Linus Torvalds1da177e2005-04-16 15:20:36 -0700349#define EEH_POSSIBLE_ERROR(val, type) (0)
350#define EEH_IO_ERROR_VALUE(size) (-1UL)
Oliver O'Halloran475028e2020-07-25 18:12:18 +1000351static inline int eeh_phb_pe_create(struct pci_controller *phb) { return 0; }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700352#endif /* CONFIG_EEH */
353
Oliver O'Halloranb6eebb02020-03-06 18:39:03 +1100354#if defined(CONFIG_PPC_PSERIES) && defined(CONFIG_EEH)
Oliver O'Halloranb6eebb02020-03-06 18:39:03 +1100355void pseries_eeh_init_edev_recursive(struct pci_dn *pdn);
Oliver O'Halloranb6eebb02020-03-06 18:39:03 +1100356#endif
357
Benjamin Herrenschmidt8b8da352008-10-27 19:48:37 +0000358#ifdef CONFIG_PPC64
Linas Vepstas172ca922005-11-03 18:50:04 -0600359/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700360 * MMIO read/write operations with EEH support.
361 */
362static inline u8 eeh_readb(const volatile void __iomem *addr)
363{
364 u8 val = in_8(addr);
365 if (EEH_POSSIBLE_ERROR(val, u8))
Gavin Shan3e938052014-09-30 12:38:50 +1000366 eeh_check_failure(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367 return val;
368}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700369
370static inline u16 eeh_readw(const volatile void __iomem *addr)
371{
372 u16 val = in_le16(addr);
373 if (EEH_POSSIBLE_ERROR(val, u16))
Gavin Shan3e938052014-09-30 12:38:50 +1000374 eeh_check_failure(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700375 return val;
376}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700377
378static inline u32 eeh_readl(const volatile void __iomem *addr)
379{
380 u32 val = in_le32(addr);
381 if (EEH_POSSIBLE_ERROR(val, u32))
Gavin Shan3e938052014-09-30 12:38:50 +1000382 eeh_check_failure(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700383 return val;
384}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700385
386static inline u64 eeh_readq(const volatile void __iomem *addr)
387{
388 u64 val = in_le64(addr);
389 if (EEH_POSSIBLE_ERROR(val, u64))
Gavin Shan3e938052014-09-30 12:38:50 +1000390 eeh_check_failure(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391 return val;
392}
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100393
394static inline u16 eeh_readw_be(const volatile void __iomem *addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700395{
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100396 u16 val = in_be16(addr);
397 if (EEH_POSSIBLE_ERROR(val, u16))
Gavin Shan3e938052014-09-30 12:38:50 +1000398 eeh_check_failure(addr);
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100399 return val;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700400}
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100401
402static inline u32 eeh_readl_be(const volatile void __iomem *addr)
403{
404 u32 val = in_be32(addr);
405 if (EEH_POSSIBLE_ERROR(val, u32))
Gavin Shan3e938052014-09-30 12:38:50 +1000406 eeh_check_failure(addr);
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100407 return val;
408}
409
410static inline u64 eeh_readq_be(const volatile void __iomem *addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700411{
412 u64 val = in_be64(addr);
413 if (EEH_POSSIBLE_ERROR(val, u64))
Gavin Shan3e938052014-09-30 12:38:50 +1000414 eeh_check_failure(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700415 return val;
416}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417
Benjamin Herrenschmidt68a64352006-11-13 09:27:39 +1100418static inline void eeh_memcpy_fromio(void *dest, const
419 volatile void __iomem *src,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420 unsigned long n)
421{
Benjamin Herrenschmidt68a64352006-11-13 09:27:39 +1100422 _memcpy_fromio(dest, src, n);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700423
424 /* Look for ffff's here at dest[n]. Assume that at least 4 bytes
425 * were copied. Check all four bytes.
426 */
Benjamin Herrenschmidt68a64352006-11-13 09:27:39 +1100427 if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
Gavin Shan3e938052014-09-30 12:38:50 +1000428 eeh_check_failure(src);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700429}
430
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431/* in-string eeh macros */
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100432static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
433 int ns)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700434{
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100435 _insb(addr, buf, ns);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700436 if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
Gavin Shan3e938052014-09-30 12:38:50 +1000437 eeh_check_failure(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700438}
439
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100440static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
441 int ns)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700442{
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100443 _insw(addr, buf, ns);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700444 if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
Gavin Shan3e938052014-09-30 12:38:50 +1000445 eeh_check_failure(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446}
447
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100448static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
449 int nl)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700450{
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100451 _insl(addr, buf, nl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700452 if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
Gavin Shan3e938052014-09-30 12:38:50 +1000453 eeh_check_failure(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700454}
455
Oliver O'Halloran5ca85ae2019-02-15 11:48:13 +1100456
Nick Childd2769602021-12-16 17:00:16 -0500457void __init eeh_cache_debugfs_init(void);
Oliver O'Halloran5ca85ae2019-02-15 11:48:13 +1100458
Benjamin Herrenschmidt8b8da352008-10-27 19:48:37 +0000459#endif /* CONFIG_PPC64 */
Arnd Bergmann88ced032005-12-16 22:43:46 +0100460#endif /* __KERNEL__ */
Benjamin Herrenschmidt8b8da352008-10-27 19:48:37 +0000461#endif /* _POWERPC_EEH_H */