blob: f6cc9166082a13977004a48782c02471de4a009a [file] [log] [blame]
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
Mark Rustad49425df2016-04-01 12:18:09 -07004 Copyright(c) 1999 - 2016 Intel Corporation.
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00005
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
Jacob Kellerb89aae72014-02-22 01:23:50 +000023 Linux NICS <linux.nics@intel.com>
Jacob Keller3a6a4ed2012-05-01 05:24:58 +000024 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28#include "ixgbe.h"
Jacob Keller1d1a79b2012-05-22 06:18:08 +000029#include <linux/ptp_classify.h>
Mark Rustada9763f32015-10-27 09:58:07 -070030#include <linux/clocksource.h>
Jacob Keller3a6a4ed2012-05-01 05:24:58 +000031
32/*
33 * The 82599 and the X540 do not have true 64bit nanosecond scale
34 * counter registers. Instead, SYSTIME is defined by a fixed point
35 * system which allows the user to define the scale counter increment
36 * value at every level change of the oscillator driving the SYSTIME
37 * value. For both devices the TIMINCA:IV field defines this
38 * increment. On the X540 device, 31 bits are provided. However on the
39 * 82599 only provides 24 bits. The time unit is determined by the
40 * clock frequency of the oscillator in combination with the TIMINCA
41 * register. When these devices link at 10Gb the oscillator has a
42 * period of 6.4ns. In order to convert the scale counter into
43 * nanoseconds the cyclecounter and timecounter structures are
44 * used. The SYSTIME registers need to be converted to ns values by use
45 * of only a right shift (division by power of 2). The following math
46 * determines the largest incvalue that will fit into the available
47 * bits in the TIMINCA register.
48 *
49 * PeriodWidth: Number of bits to store the clock period
50 * MaxWidth: The maximum width value of the TIMINCA register
51 * Period: The clock period for the oscillator
52 * round(): discard the fractional portion of the calculation
53 *
54 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
55 *
56 * For the X540, MaxWidth is 31 bits, and the base period is 6.4 ns
57 * For the 82599, MaxWidth is 24 bits, and the base period is 6.4 ns
58 *
59 * The period also changes based on the link speed:
60 * At 10Gb link or no link, the period remains the same.
61 * At 1Gb link, the period is multiplied by 10. (64ns)
62 * At 100Mb link, the period is multiplied by 100. (640ns)
63 *
64 * The calculated value allows us to right shift the SYSTIME register
65 * value in order to quickly convert it into a nanosecond clock,
66 * while allowing for the maximum possible adjustment value.
67 *
68 * These diagrams are only for the 10Gb link period
69 *
70 * SYSTIMEH SYSTIMEL
71 * +--------------+ +--------------+
72 * X540 | 32 | | 1 | 3 | 28 |
73 * *--------------+ +--------------+
74 * \________ 36 bits ______/ fract
75 *
76 * +--------------+ +--------------+
77 * 82599 | 32 | | 8 | 3 | 21 |
78 * *--------------+ +--------------+
79 * \________ 43 bits ______/ fract
80 *
81 * The 36 bit X540 SYSTIME overflows every
82 * 2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds
83 *
84 * The 43 bit 82599 SYSTIME overflows every
85 * 2^43 * 10^-9 / 3600 = 2.4 hours
86 */
87#define IXGBE_INCVAL_10GB 0x66666666
88#define IXGBE_INCVAL_1GB 0x40000000
89#define IXGBE_INCVAL_100 0x50000000
90
91#define IXGBE_INCVAL_SHIFT_10GB 28
92#define IXGBE_INCVAL_SHIFT_1GB 24
93#define IXGBE_INCVAL_SHIFT_100 21
94
95#define IXGBE_INCVAL_SHIFT_82599 7
96#define IXGBE_INCPER_SHIFT_82599 24
Jacob Keller3a6a4ed2012-05-01 05:24:58 +000097
98#define IXGBE_OVERFLOW_PERIOD (HZ * 30)
Jacob Keller891dc082012-12-05 07:24:46 +000099#define IXGBE_PTP_TX_TIMEOUT (HZ * 15)
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000100
Jacob Kellera5a0fc02014-05-28 07:21:47 +0000101/* half of a one second clock period, for use with PPS signal. We have to use
102 * this instead of something pre-defined like IXGBE_PTP_PPS_HALF_SECOND, in
103 * order to force at least 64bits of precision for shifting
104 */
105#define IXGBE_PTP_PPS_HALF_SECOND 500000000ULL
Jacob E Keller681ae1a2012-05-01 05:24:41 +0000106
Mark Rustada9763f32015-10-27 09:58:07 -0700107/* In contrast, the X550 controller has two registers, SYSTIMEH and SYSTIMEL
108 * which contain measurements of seconds and nanoseconds respectively. This
109 * matches the standard linux representation of time in the kernel. In addition,
110 * the X550 also has a SYSTIMER register which represents residue, or
111 * subnanosecond overflow adjustments. To control clock adjustment, the TIMINCA
112 * register is used, but it is unlike the X540 and 82599 devices. TIMINCA
113 * represents units of 2^-32 nanoseconds, and uses 31 bits for this, with the
114 * high bit representing whether the adjustent is positive or negative. Every
115 * clock cycle, the X550 will add 12.5 ns + TIMINCA which can result in a range
116 * of 12 to 13 nanoseconds adjustment. Unlike the 82599 and X540 devices, the
117 * X550's clock for purposes of SYSTIME generation is constant and not dependent
118 * on the link speed.
119 *
120 * SYSTIMEH SYSTIMEL SYSTIMER
121 * +--------------+ +--------------+ +-------------+
122 * X550 | 32 | | 32 | | 32 |
123 * *--------------+ +--------------+ +-------------+
124 * \____seconds___/ \_nanoseconds_/ \__2^-32 ns__/
125 *
126 * This results in a full 96 bits to represent the clock, with 32 bits for
127 * seconds, 32 bits for nanoseconds (largest value is 0d999999999 or just under
128 * 1 second) and an additional 32 bits to measure sub nanosecond adjustments for
129 * underflow of adjustments.
130 *
131 * The 32 bits of seconds for the X550 overflows every
132 * 2^32 / ( 365.25 * 24 * 60 * 60 ) = ~136 years.
133 *
134 * In order to adjust the clock frequency for the X550, the TIMINCA register is
135 * provided. This register represents a + or minus nearly 0.5 ns adjustment to
136 * the base frequency. It is measured in 2^-32 ns units, with the high bit being
137 * the sign bit. This register enables software to calculate frequency
138 * adjustments and apply them directly to the clock rate.
139 *
140 * The math for converting ppb into TIMINCA values is fairly straightforward.
141 * TIMINCA value = ( Base_Frequency * ppb ) / 1000000000ULL
142 *
143 * This assumes that ppb is never high enough to create a value bigger than
144 * TIMINCA's 31 bits can store. This is ensured by the stack. Calculating this
145 * value is also simple.
146 * Max ppb = ( Max Adjustment / Base Frequency ) / 1000000000ULL
147 *
148 * For the X550, the Max adjustment is +/- 0.5 ns, and the base frequency is
149 * 12.5 nanoseconds. This means that the Max ppb is 39999999
150 * Note: We subtract one in order to ensure no overflow, because the TIMINCA
151 * register can only hold slightly under 0.5 nanoseconds.
152 *
153 * Because TIMINCA is measured in 2^-32 ns units, we have to convert 12.5 ns
154 * into 2^-32 units, which is
155 *
156 * 12.5 * 2^32 = C80000000
157 *
158 * Some revisions of hardware have a faster base frequency than the registers
159 * were defined for. To fix this, we use a timecounter structure with the
160 * proper mult and shift to convert the cycles into nanoseconds of time.
161 */
162#define IXGBE_X550_BASE_PERIOD 0xC80000000ULL
163#define INCVALUE_MASK 0x7FFFFFFF
164#define ISGN 0x80000000
165#define MAX_TIMADJ 0x7FFFFFFF
166
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000167/**
Mark Rustada9763f32015-10-27 09:58:07 -0700168 * ixgbe_ptp_setup_sdp_x540
Tony Nguyen5ba643c2017-12-04 11:28:30 -0800169 * @adapter: private adapter structure
Jacob Keller82083672012-08-01 07:12:25 +0000170 *
Jacob Kellerdb0677f2012-08-24 07:46:54 +0000171 * this function enables or disables the clock out feature on SDP0 for
172 * the X540 device. It will create a 1second periodic output that can
173 * be used as the PPS (via an interrupt).
Jacob Keller82083672012-08-01 07:12:25 +0000174 *
175 * It calculates when the systime will be on an exact second, and then
176 * aligns the start of the PPS signal to that value. The shift is
177 * necessary because it can change based on the link speed.
178 */
Mark Rustada9763f32015-10-27 09:58:07 -0700179static void ixgbe_ptp_setup_sdp_x540(struct ixgbe_adapter *adapter)
Jacob Keller82083672012-08-01 07:12:25 +0000180{
181 struct ixgbe_hw *hw = &adapter->hw;
Mark Rustada9763f32015-10-27 09:58:07 -0700182 int shift = adapter->hw_cc.shift;
Jacob Keller82083672012-08-01 07:12:25 +0000183 u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem;
184 u64 ns = 0, clock_edge = 0;
185
Mark Rustada9763f32015-10-27 09:58:07 -0700186 /* disable the pin first */
187 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
188 IXGBE_WRITE_FLUSH(hw);
Jacob Kellerdb0677f2012-08-24 07:46:54 +0000189
Mark Rustada9763f32015-10-27 09:58:07 -0700190 if (!(adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED))
191 return;
Jacob Kellerdb0677f2012-08-24 07:46:54 +0000192
Mark Rustada9763f32015-10-27 09:58:07 -0700193 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
Jacob Keller82083672012-08-01 07:12:25 +0000194
Mark Rustada9763f32015-10-27 09:58:07 -0700195 /* enable the SDP0 pin as output, and connected to the
196 * native function for Timesync (ClockOut)
197 */
198 esdp |= IXGBE_ESDP_SDP0_DIR |
199 IXGBE_ESDP_SDP0_NATIVE;
Jacob Keller82083672012-08-01 07:12:25 +0000200
Mark Rustada9763f32015-10-27 09:58:07 -0700201 /* enable the Clock Out feature on SDP0, and allow
202 * interrupts to occur when the pin changes
203 */
204 tsauxc = IXGBE_TSAUXC_EN_CLK |
205 IXGBE_TSAUXC_SYNCLK |
206 IXGBE_TSAUXC_SDP0_INT;
Jacob Keller82083672012-08-01 07:12:25 +0000207
Mark Rustada9763f32015-10-27 09:58:07 -0700208 /* clock period (or pulse length) */
209 clktiml = (u32)(IXGBE_PTP_PPS_HALF_SECOND << shift);
210 clktimh = (u32)((IXGBE_PTP_PPS_HALF_SECOND << shift) >> 32);
Jacob Keller82083672012-08-01 07:12:25 +0000211
Mark Rustada9763f32015-10-27 09:58:07 -0700212 /* Account for the cyclecounter wrap-around value by
213 * using the converted ns value of the current time to
214 * check for when the next aligned second would occur.
215 */
216 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
217 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
218 ns = timecounter_cyc2time(&adapter->hw_tc, clock_edge);
Jacob Keller82083672012-08-01 07:12:25 +0000219
Mark Rustada9763f32015-10-27 09:58:07 -0700220 div_u64_rem(ns, IXGBE_PTP_PPS_HALF_SECOND, &rem);
221 clock_edge += ((IXGBE_PTP_PPS_HALF_SECOND - (u64)rem) << shift);
Jacob Keller82083672012-08-01 07:12:25 +0000222
Mark Rustada9763f32015-10-27 09:58:07 -0700223 /* specify the initial clock start time */
224 trgttiml = (u32)clock_edge;
225 trgttimh = (u32)(clock_edge >> 32);
Jacob Keller82083672012-08-01 07:12:25 +0000226
Mark Rustada9763f32015-10-27 09:58:07 -0700227 IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
228 IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
229 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
230 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
Jacob Keller82083672012-08-01 07:12:25 +0000231
Mark Rustada9763f32015-10-27 09:58:07 -0700232 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
233 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
Jacob Keller82083672012-08-01 07:12:25 +0000234
Jacob Keller82083672012-08-01 07:12:25 +0000235 IXGBE_WRITE_FLUSH(hw);
236}
237
238/**
Mark Rustada9763f32015-10-27 09:58:07 -0700239 * ixgbe_ptp_read_X550 - read cycle counter value
240 * @hw_cc: cyclecounter structure
241 *
242 * This function reads SYSTIME registers. It is called by the cyclecounter
243 * structure to convert from internal representation into nanoseconds. We need
244 * this for X550 since some skews do not have expected clock frequency and
245 * result of SYSTIME is 32bits of "billions of cycles" and 32 bits of
246 * "cycles", rather than seconds and nanoseconds.
247 */
Thomas Gleixnera5a1d1c2016-12-21 20:32:01 +0100248static u64 ixgbe_ptp_read_X550(const struct cyclecounter *hw_cc)
Mark Rustada9763f32015-10-27 09:58:07 -0700249{
250 struct ixgbe_adapter *adapter =
251 container_of(hw_cc, struct ixgbe_adapter, hw_cc);
252 struct ixgbe_hw *hw = &adapter->hw;
253 struct timespec64 ts;
254
255 /* storage is 32 bits of 'billions of cycles' and 32 bits of 'cycles'.
256 * Some revisions of hardware run at a higher frequency and so the
257 * cycles are not guaranteed to be nanoseconds. The timespec64 created
258 * here is used for its math/conversions but does not necessarily
259 * represent nominal time.
260 *
261 * It should be noted that this cyclecounter will overflow at a
262 * non-bitmask field since we have to convert our billions of cycles
263 * into an actual cycles count. This results in some possible weird
264 * situations at high cycle counter stamps. However given that 32 bits
265 * of "seconds" is ~138 years this isn't a problem. Even at the
266 * increased frequency of some revisions, this is still ~103 years.
267 * Since the SYSTIME values start at 0 and we never write them, it is
268 * highly unlikely for the cyclecounter to overflow in practice.
269 */
270 IXGBE_READ_REG(hw, IXGBE_SYSTIMR);
271 ts.tv_nsec = IXGBE_READ_REG(hw, IXGBE_SYSTIML);
272 ts.tv_sec = IXGBE_READ_REG(hw, IXGBE_SYSTIMH);
273
274 return (u64)timespec64_to_ns(&ts);
275}
276
277/**
278 * ixgbe_ptp_read_82599 - read raw cycle counter (to be used by time counter)
Ben Hutchings49ce9c22012-07-10 10:56:00 +0000279 * @cc: the cyclecounter structure
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000280 *
281 * this function reads the cyclecounter registers and is called by the
282 * cyclecounter structure used to construct a ns counter from the
283 * arbitrary fixed point registers
284 */
Thomas Gleixnera5a1d1c2016-12-21 20:32:01 +0100285static u64 ixgbe_ptp_read_82599(const struct cyclecounter *cc)
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000286{
287 struct ixgbe_adapter *adapter =
Mark Rustada9763f32015-10-27 09:58:07 -0700288 container_of(cc, struct ixgbe_adapter, hw_cc);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000289 struct ixgbe_hw *hw = &adapter->hw;
290 u64 stamp = 0;
291
292 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
293 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
294
295 return stamp;
296}
297
298/**
Mark Rustada9763f32015-10-27 09:58:07 -0700299 * ixgbe_ptp_convert_to_hwtstamp - convert register value to hw timestamp
300 * @adapter: private adapter structure
301 * @hwtstamp: stack timestamp structure
Tony Nguyen5ba643c2017-12-04 11:28:30 -0800302 * @timestamp: unsigned 64bit system time value
Mark Rustada9763f32015-10-27 09:58:07 -0700303 *
304 * We need to convert the adapter's RX/TXSTMP registers into a hwtstamp value
305 * which can be used by the stack's ptp functions.
306 *
307 * The lock is used to protect consistency of the cyclecounter and the SYSTIME
308 * registers. However, it does not need to protect against the Rx or Tx
309 * timestamp registers, as there can't be a new timestamp until the old one is
310 * unlatched by reading.
311 *
312 * In addition to the timestamp in hardware, some controllers need a software
313 * overflow cyclecounter, and this function takes this into account as well.
314 **/
315static void ixgbe_ptp_convert_to_hwtstamp(struct ixgbe_adapter *adapter,
316 struct skb_shared_hwtstamps *hwtstamp,
317 u64 timestamp)
318{
319 unsigned long flags;
320 struct timespec64 systime;
321 u64 ns;
322
323 memset(hwtstamp, 0, sizeof(*hwtstamp));
324
325 switch (adapter->hw.mac.type) {
326 /* X550 and later hardware supposedly represent time using a seconds
327 * and nanoseconds counter, instead of raw 64bits nanoseconds. We need
328 * to convert the timestamp into cycles before it can be fed to the
329 * cyclecounter. We need an actual cyclecounter because some revisions
330 * of hardware run at a higher frequency and thus the counter does
331 * not represent seconds/nanoseconds. Instead it can be thought of as
332 * cycles and billions of cycles.
333 */
334 case ixgbe_mac_X550:
335 case ixgbe_mac_X550EM_x:
Mark Rustad49425df2016-04-01 12:18:09 -0700336 case ixgbe_mac_x550em_a:
Mark Rustada9763f32015-10-27 09:58:07 -0700337 /* Upper 32 bits represent billions of cycles, lower 32 bits
338 * represent cycles. However, we use timespec64_to_ns for the
339 * correct math even though the units haven't been corrected
340 * yet.
341 */
342 systime.tv_sec = timestamp >> 32;
343 systime.tv_nsec = timestamp & 0xFFFFFFFF;
344
345 timestamp = timespec64_to_ns(&systime);
346 break;
347 default:
348 break;
349 }
350
351 spin_lock_irqsave(&adapter->tmreg_lock, flags);
352 ns = timecounter_cyc2time(&adapter->hw_tc, timestamp);
353 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
354
355 hwtstamp->hwtstamp = ns_to_ktime(ns);
356}
357
358/**
359 * ixgbe_ptp_adjfreq_82599
Ben Hutchings49ce9c22012-07-10 10:56:00 +0000360 * @ptp: the ptp clock structure
361 * @ppb: parts per billion adjustment from base
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000362 *
363 * adjust the frequency of the ptp cycle counter by the
364 * indicated ppb from the base frequency.
365 */
Mark Rustada9763f32015-10-27 09:58:07 -0700366static int ixgbe_ptp_adjfreq_82599(struct ptp_clock_info *ptp, s32 ppb)
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000367{
368 struct ixgbe_adapter *adapter =
369 container_of(ptp, struct ixgbe_adapter, ptp_caps);
370 struct ixgbe_hw *hw = &adapter->hw;
Mark Rustada9763f32015-10-27 09:58:07 -0700371 u64 freq, incval;
372 u32 diff;
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000373 int neg_adj = 0;
374
375 if (ppb < 0) {
376 neg_adj = 1;
377 ppb = -ppb;
378 }
379
380 smp_mb();
Mark Rutland6aa7de02017-10-23 14:07:29 -0700381 incval = READ_ONCE(adapter->base_incval);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000382
383 freq = incval;
384 freq *= ppb;
385 diff = div_u64(freq, 1000000000ULL);
386
387 incval = neg_adj ? (incval - diff) : (incval + diff);
388
389 switch (hw->mac.type) {
390 case ixgbe_mac_X540:
Mark Rustada9763f32015-10-27 09:58:07 -0700391 if (incval > 0xFFFFFFFFULL)
392 e_dev_warn("PTP ppb adjusted SYSTIME rate overflowed!\n");
393 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, (u32)incval);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000394 break;
395 case ixgbe_mac_82599EB:
Mark Rustada9763f32015-10-27 09:58:07 -0700396 if (incval > 0x00FFFFFFULL)
397 e_dev_warn("PTP ppb adjusted SYSTIME rate overflowed!\n");
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000398 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
Jacob Kellerb4f47a42016-04-13 16:08:22 -0700399 BIT(IXGBE_INCPER_SHIFT_82599) |
Mark Rustada9763f32015-10-27 09:58:07 -0700400 ((u32)incval & 0x00FFFFFFUL));
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000401 break;
402 default:
403 break;
404 }
405
406 return 0;
407}
408
409/**
Mark Rustada9763f32015-10-27 09:58:07 -0700410 * ixgbe_ptp_adjfreq_X550
411 * @ptp: the ptp clock structure
412 * @ppb: parts per billion adjustment from base
413 *
414 * adjust the frequency of the SYSTIME registers by the indicated ppb from base
415 * frequency
416 */
417static int ixgbe_ptp_adjfreq_X550(struct ptp_clock_info *ptp, s32 ppb)
418{
419 struct ixgbe_adapter *adapter =
420 container_of(ptp, struct ixgbe_adapter, ptp_caps);
421 struct ixgbe_hw *hw = &adapter->hw;
422 int neg_adj = 0;
423 u64 rate = IXGBE_X550_BASE_PERIOD;
424 u32 inca;
425
426 if (ppb < 0) {
427 neg_adj = 1;
428 ppb = -ppb;
429 }
430 rate *= ppb;
431 rate = div_u64(rate, 1000000000ULL);
432
433 /* warn if rate is too large */
434 if (rate >= INCVALUE_MASK)
435 e_dev_warn("PTP ppb adjusted SYSTIME rate overflowed!\n");
436
437 inca = rate & INCVALUE_MASK;
438 if (neg_adj)
439 inca |= ISGN;
440
441 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, inca);
442
443 return 0;
444}
445
446/**
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000447 * ixgbe_ptp_adjtime
Ben Hutchings49ce9c22012-07-10 10:56:00 +0000448 * @ptp: the ptp clock structure
449 * @delta: offset to adjust the cycle counter by
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000450 *
451 * adjust the timer by resetting the timecounter structure.
452 */
453static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
454{
455 struct ixgbe_adapter *adapter =
456 container_of(ptp, struct ixgbe_adapter, ptp_caps);
457 unsigned long flags;
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000458
459 spin_lock_irqsave(&adapter->tmreg_lock, flags);
Mark Rustada9763f32015-10-27 09:58:07 -0700460 timecounter_adjtime(&adapter->hw_tc, delta);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000461 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
Jacob Kellerdb0677f2012-08-24 07:46:54 +0000462
Mark Rustada9763f32015-10-27 09:58:07 -0700463 if (adapter->ptp_setup_sdp)
464 adapter->ptp_setup_sdp(adapter);
Jacob Keller82083672012-08-01 07:12:25 +0000465
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000466 return 0;
467}
468
469/**
470 * ixgbe_ptp_gettime
Ben Hutchings49ce9c22012-07-10 10:56:00 +0000471 * @ptp: the ptp clock structure
472 * @ts: timespec structure to hold the current time value
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000473 *
474 * read the timecounter and return the correct value on ns,
475 * after converting it into a struct timespec.
476 */
Richard Cochran91432d12015-03-29 23:12:04 +0200477static int ixgbe_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000478{
479 struct ixgbe_adapter *adapter =
480 container_of(ptp, struct ixgbe_adapter, ptp_caps);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000481 unsigned long flags;
Mark Rustada9763f32015-10-27 09:58:07 -0700482 u64 ns;
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000483
484 spin_lock_irqsave(&adapter->tmreg_lock, flags);
Mark Rustada9763f32015-10-27 09:58:07 -0700485 ns = timecounter_read(&adapter->hw_tc);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000486 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
487
Richard Cochran0704fae2015-03-31 23:08:13 +0200488 *ts = ns_to_timespec64(ns);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000489
490 return 0;
491}
492
493/**
494 * ixgbe_ptp_settime
Ben Hutchings49ce9c22012-07-10 10:56:00 +0000495 * @ptp: the ptp clock structure
496 * @ts: the timespec containing the new time for the cycle counter
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000497 *
498 * reset the timecounter to use a new base value instead of the kernel
499 * wall timer value.
500 */
501static int ixgbe_ptp_settime(struct ptp_clock_info *ptp,
Richard Cochran91432d12015-03-29 23:12:04 +0200502 const struct timespec64 *ts)
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000503{
504 struct ixgbe_adapter *adapter =
505 container_of(ptp, struct ixgbe_adapter, ptp_caps);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000506 unsigned long flags;
Mark Rustada9763f32015-10-27 09:58:07 -0700507 u64 ns = timespec64_to_ns(ts);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000508
509 /* reset the timecounter */
510 spin_lock_irqsave(&adapter->tmreg_lock, flags);
Mark Rustada9763f32015-10-27 09:58:07 -0700511 timecounter_init(&adapter->hw_tc, &adapter->hw_cc, ns);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000512 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
513
Mark Rustada9763f32015-10-27 09:58:07 -0700514 if (adapter->ptp_setup_sdp)
515 adapter->ptp_setup_sdp(adapter);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000516 return 0;
517}
518
519/**
Jacob Keller04c8de82014-05-16 05:12:24 +0000520 * ixgbe_ptp_feature_enable
Ben Hutchings49ce9c22012-07-10 10:56:00 +0000521 * @ptp: the ptp clock structure
522 * @rq: the requested feature to change
523 * @on: whether to enable or disable the feature
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000524 *
525 * enable (or disable) ancillary features of the phc subsystem.
Jacob E Keller681ae1a2012-05-01 05:24:41 +0000526 * our driver only supports the PPS feature on the X540
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000527 */
Jacob Keller04c8de82014-05-16 05:12:24 +0000528static int ixgbe_ptp_feature_enable(struct ptp_clock_info *ptp,
529 struct ptp_clock_request *rq, int on)
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000530{
Jacob E Keller681ae1a2012-05-01 05:24:41 +0000531 struct ixgbe_adapter *adapter =
532 container_of(ptp, struct ixgbe_adapter, ptp_caps);
533
534 /**
535 * When PPS is enabled, unmask the interrupt for the ClockOut
536 * feature, so that the interrupt handler can send the PPS
537 * event when the clock SDP triggers. Clear mask when PPS is
538 * disabled
539 */
Mark Rustada9763f32015-10-27 09:58:07 -0700540 if (rq->type != PTP_CLK_REQ_PPS || !adapter->ptp_setup_sdp)
541 return -ENOTSUPP;
Jacob Kellerdb0677f2012-08-24 07:46:54 +0000542
Mark Rustada9763f32015-10-27 09:58:07 -0700543 if (on)
544 adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED;
545 else
546 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
Jacob E Keller681ae1a2012-05-01 05:24:41 +0000547
Mark Rustada9763f32015-10-27 09:58:07 -0700548 adapter->ptp_setup_sdp(adapter);
549 return 0;
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000550}
551
552/**
Jacob E Keller681ae1a2012-05-01 05:24:41 +0000553 * ixgbe_ptp_check_pps_event
Ben Hutchings49ce9c22012-07-10 10:56:00 +0000554 * @adapter: the private adapter structure
Jacob E Keller681ae1a2012-05-01 05:24:41 +0000555 *
556 * This function is called by the interrupt routine when checking for
557 * interrupts. It will check and handle a pps event.
558 */
Mark Rustada9763f32015-10-27 09:58:07 -0700559void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter)
Jacob E Keller681ae1a2012-05-01 05:24:41 +0000560{
561 struct ixgbe_hw *hw = &adapter->hw;
562 struct ptp_clock_event event;
563
Jacob Keller3645adb2012-10-13 05:00:06 +0000564 event.type = PTP_CLOCK_PPS;
565
566 /* this check is necessary in case the interrupt was enabled via some
567 * alternative means (ex. debug_fs). Better to check here than
568 * everywhere that calls this function.
569 */
570 if (!adapter->ptp_clock)
571 return;
572
Jacob Kellerdb0677f2012-08-24 07:46:54 +0000573 switch (hw->mac.type) {
574 case ixgbe_mac_X540:
575 ptp_clock_event(adapter->ptp_clock, &event);
576 break;
577 default:
578 break;
Jacob E Keller681ae1a2012-05-01 05:24:41 +0000579 }
580}
581
Jacob E Keller681ae1a2012-05-01 05:24:41 +0000582/**
Jacob Kellerf2f333872012-12-05 07:24:35 +0000583 * ixgbe_ptp_overflow_check - watchdog task to detect SYSTIME overflow
584 * @adapter: private adapter struct
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000585 *
Jacob Kellerf2f333872012-12-05 07:24:35 +0000586 * this watchdog task periodically reads the timecounter
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000587 * in order to prevent missing when the system time registers wrap
Jacob Kellerf2f333872012-12-05 07:24:35 +0000588 * around. This needs to be run approximately twice a minute.
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000589 */
590void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter)
591{
Jacob Kellerf2f333872012-12-05 07:24:35 +0000592 bool timeout = time_is_before_jiffies(adapter->last_overflow_check +
593 IXGBE_OVERFLOW_PERIOD);
Richard Cochran91432d12015-03-29 23:12:04 +0200594 struct timespec64 ts;
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000595
Jacob Keller891dc082012-12-05 07:24:46 +0000596 if (timeout) {
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000597 ixgbe_ptp_gettime(&adapter->ptp_caps, &ts);
598 adapter->last_overflow_check = jiffies;
599 }
600}
601
602/**
Jacob Keller6cb562d2012-12-05 07:24:41 +0000603 * ixgbe_ptp_rx_hang - detect error case when Rx timestamp registers latched
604 * @adapter: private network adapter structure
Jacob Keller1d1a79b2012-05-22 06:18:08 +0000605 *
Jacob Keller6cb562d2012-12-05 07:24:41 +0000606 * this watchdog task is scheduled to detect error case where hardware has
607 * dropped an Rx packet that was timestamped when the ring is full. The
608 * particular error is rare but leaves the device in a state unable to timestamp
609 * any future packets.
Jacob Keller1d1a79b2012-05-22 06:18:08 +0000610 */
Jacob Keller6cb562d2012-12-05 07:24:41 +0000611void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter)
Jacob Keller1d1a79b2012-05-22 06:18:08 +0000612{
Jacob Keller6cb562d2012-12-05 07:24:41 +0000613 struct ixgbe_hw *hw = &adapter->hw;
Jacob Keller6cb562d2012-12-05 07:24:41 +0000614 u32 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
Mark Rustada9763f32015-10-27 09:58:07 -0700615 struct ixgbe_ring *rx_ring;
Jacob Keller6cb562d2012-12-05 07:24:41 +0000616 unsigned long rx_event;
Mark Rustada9763f32015-10-27 09:58:07 -0700617 int n;
Jacob Keller1d1a79b2012-05-22 06:18:08 +0000618
Jacob Keller6cb562d2012-12-05 07:24:41 +0000619 /* if we don't have a valid timestamp in the registers, just update the
620 * timeout counter and exit
621 */
622 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID)) {
623 adapter->last_rx_ptp_check = jiffies;
624 return;
Jacob Keller1d1a79b2012-05-22 06:18:08 +0000625 }
626
Jacob Keller6cb562d2012-12-05 07:24:41 +0000627 /* determine the most recent watchdog or rx_timestamp event */
628 rx_event = adapter->last_rx_ptp_check;
Mark Rustada9763f32015-10-27 09:58:07 -0700629 for (n = 0; n < adapter->num_rx_queues; n++) {
630 rx_ring = adapter->rx_ring[n];
631 if (time_after(rx_ring->last_rx_timestamp, rx_event))
632 rx_event = rx_ring->last_rx_timestamp;
633 }
Jacob Keller1d1a79b2012-05-22 06:18:08 +0000634
Jacob Keller6cb562d2012-12-05 07:24:41 +0000635 /* only need to read the high RXSTMP register to clear the lock */
Mark Rustada9763f32015-10-27 09:58:07 -0700636 if (time_is_before_jiffies(rx_event + 5 * HZ)) {
Jacob Keller6cb562d2012-12-05 07:24:41 +0000637 IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
638 adapter->last_rx_ptp_check = jiffies;
Jacob Keller1d1a79b2012-05-22 06:18:08 +0000639
Mark Rustada9763f32015-10-27 09:58:07 -0700640 adapter->rx_hwtstamp_cleared++;
Jakub Kicinskic5ffe7e2014-04-02 10:33:22 +0000641 e_warn(drv, "clearing RX Timestamp hang\n");
Jacob Keller1d1a79b2012-05-22 06:18:08 +0000642 }
643}
644
645/**
Mark Rustada9763f32015-10-27 09:58:07 -0700646 * ixgbe_ptp_clear_tx_timestamp - utility function to clear Tx timestamp state
647 * @adapter: the private adapter structure
648 *
649 * This function should be called whenever the state related to a Tx timestamp
650 * needs to be cleared. This helps ensure that all related bits are reset for
651 * the next Tx timestamp event.
652 */
653static void ixgbe_ptp_clear_tx_timestamp(struct ixgbe_adapter *adapter)
654{
655 struct ixgbe_hw *hw = &adapter->hw;
656
657 IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
658 if (adapter->ptp_tx_skb) {
659 dev_kfree_skb_any(adapter->ptp_tx_skb);
660 adapter->ptp_tx_skb = NULL;
661 }
662 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
663}
664
665/**
Jacob Keller622a2ef2017-05-03 10:29:04 -0700666 * ixgbe_ptp_tx_hang - detect error case where Tx timestamp never finishes
667 * @adapter: private network adapter structure
668 */
669void ixgbe_ptp_tx_hang(struct ixgbe_adapter *adapter)
670{
671 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
672 IXGBE_PTP_TX_TIMEOUT);
673
674 if (!adapter->ptp_tx_skb)
675 return;
676
677 if (!test_bit(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state))
678 return;
679
680 /* If we haven't received a timestamp within the timeout, it is
681 * reasonable to assume that it will never occur, so we can unlock the
682 * timestamp bit when this occurs.
683 */
684 if (timeout) {
685 cancel_work_sync(&adapter->ptp_tx_work);
686 ixgbe_ptp_clear_tx_timestamp(adapter);
687 adapter->tx_hwtstamp_timeouts++;
688 e_warn(drv, "clearing Tx timestamp hang\n");
689 }
690}
691
692/**
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000693 * ixgbe_ptp_tx_hwtstamp - utility function which checks for TX time stamp
Jacob Keller891dc082012-12-05 07:24:46 +0000694 * @adapter: the private adapter struct
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000695 *
696 * if the timestamp is valid, we convert it into the timecounter ns
697 * value, then store that result into the shhwtstamps structure which
698 * is passed up the network stack
699 */
Jacob Keller891dc082012-12-05 07:24:46 +0000700static void ixgbe_ptp_tx_hwtstamp(struct ixgbe_adapter *adapter)
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000701{
Jacob Kelleraaebaf52017-05-03 10:28:53 -0700702 struct sk_buff *skb = adapter->ptp_tx_skb;
Jacob Keller891dc082012-12-05 07:24:46 +0000703 struct ixgbe_hw *hw = &adapter->hw;
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000704 struct skb_shared_hwtstamps shhwtstamps;
Mark Rustada9763f32015-10-27 09:58:07 -0700705 u64 regval = 0;
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000706
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000707 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
708 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32;
Mark Rustada9763f32015-10-27 09:58:07 -0700709 ixgbe_ptp_convert_to_hwtstamp(adapter, &shhwtstamps, regval);
Jacob Keller891dc082012-12-05 07:24:46 +0000710
Jacob Kelleraaebaf52017-05-03 10:28:53 -0700711 /* Handle cleanup of the ptp_tx_skb ourselves, and unlock the state
712 * bit prior to notifying the stack via skb_tstamp_tx(). This prevents
713 * well behaved applications from attempting to timestamp again prior
714 * to the lock bit being clear.
715 */
716 adapter->ptp_tx_skb = NULL;
717 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
718
719 /* Notify the stack and then free the skb after we've unlocked */
720 skb_tstamp_tx(skb, &shhwtstamps);
721 dev_kfree_skb_any(skb);
Jacob Keller891dc082012-12-05 07:24:46 +0000722}
723
724/**
725 * ixgbe_ptp_tx_hwtstamp_work
726 * @work: pointer to the work struct
727 *
728 * This work item polls TSYNCTXCTL valid bit to determine when a Tx hardware
Joe Perchesdbedd442015-03-06 20:49:12 -0800729 * timestamp has been taken for the current skb. It is necessary, because the
Jacob Keller891dc082012-12-05 07:24:46 +0000730 * descriptor's "done" bit does not correlate with the timestamp event.
731 */
732static void ixgbe_ptp_tx_hwtstamp_work(struct work_struct *work)
733{
734 struct ixgbe_adapter *adapter = container_of(work, struct ixgbe_adapter,
735 ptp_tx_work);
736 struct ixgbe_hw *hw = &adapter->hw;
737 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
738 IXGBE_PTP_TX_TIMEOUT);
739 u32 tsynctxctl;
740
Mark Rustada9763f32015-10-27 09:58:07 -0700741 /* we have to have a valid skb to poll for a timestamp */
742 if (!adapter->ptp_tx_skb) {
743 ixgbe_ptp_clear_tx_timestamp(adapter);
Jacob Keller891dc082012-12-05 07:24:46 +0000744 return;
745 }
746
Mark Rustada9763f32015-10-27 09:58:07 -0700747 /* stop polling once we have a valid timestamp */
Jacob Keller891dc082012-12-05 07:24:46 +0000748 tsynctxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
Mark Rustada9763f32015-10-27 09:58:07 -0700749 if (tsynctxctl & IXGBE_TSYNCTXCTL_VALID) {
Jacob Keller891dc082012-12-05 07:24:46 +0000750 ixgbe_ptp_tx_hwtstamp(adapter);
Mark Rustada9763f32015-10-27 09:58:07 -0700751 return;
752 }
753
754 if (timeout) {
755 ixgbe_ptp_clear_tx_timestamp(adapter);
756 adapter->tx_hwtstamp_timeouts++;
757 e_warn(drv, "clearing Tx Timestamp hang\n");
758 } else {
Jacob Keller891dc082012-12-05 07:24:46 +0000759 /* reschedule to keep checking if it's not available yet */
760 schedule_work(&adapter->ptp_tx_work);
Mark Rustada9763f32015-10-27 09:58:07 -0700761 }
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000762}
763
764/**
Mark Rustada9763f32015-10-27 09:58:07 -0700765 * ixgbe_ptp_rx_pktstamp - utility function to get RX time stamp from buffer
766 * @q_vector: structure containing interrupt and ring information
767 * @skb: the packet
768 *
769 * This function will be called by the Rx routine of the timestamp for this
770 * packet is stored in the buffer. The value is stored in little endian format
771 * starting at the end of the packet data.
772 */
773void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *q_vector,
774 struct sk_buff *skb)
775{
776 __le64 regval;
777
778 /* copy the bits out of the skb, and then trim the skb length */
779 skb_copy_bits(skb, skb->len - IXGBE_TS_HDR_LEN, &regval,
780 IXGBE_TS_HDR_LEN);
781 __pskb_trim(skb, skb->len - IXGBE_TS_HDR_LEN);
782
783 /* The timestamp is recorded in little endian format, and is stored at
784 * the end of the packet.
785 *
786 * DWORD: N N + 1 N + 2
787 * Field: End of Packet SYSTIMH SYSTIML
788 */
789 ixgbe_ptp_convert_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb),
790 le64_to_cpu(regval));
791}
792
793/**
794 * ixgbe_ptp_rx_rgtstamp - utility function which checks for RX time stamp
795 * @q_vector: structure containing interrupt and ring information
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000796 * @skb: particular skb to send timestamp with
797 *
798 * if the timestamp is valid, we convert it into the timecounter ns
799 * value, then store that result into the shhwtstamps structure which
800 * is passed up the network stack
801 */
Mark Rustada9763f32015-10-27 09:58:07 -0700802void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *q_vector,
803 struct sk_buff *skb)
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000804{
Mark Rustada9763f32015-10-27 09:58:07 -0700805 struct ixgbe_adapter *adapter;
806 struct ixgbe_hw *hw;
807 u64 regval = 0;
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000808 u32 tsyncrxctl;
Mark Rustada9763f32015-10-27 09:58:07 -0700809
810 /* we cannot process timestamps on a ring without a q_vector */
811 if (!q_vector || !q_vector->adapter)
812 return;
813
814 adapter = q_vector->adapter;
815 hw = &adapter->hw;
816
817 /* Read the tsyncrxctl register afterwards in order to prevent taking an
818 * I/O hit on every packet.
819 */
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000820
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000821 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
Jiri Bencf42df162012-10-25 18:12:05 +0000822 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID))
Jacob Keller1d1a79b2012-05-22 06:18:08 +0000823 return;
824
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000825 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
826 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32;
827
Mark Rustada9763f32015-10-27 09:58:07 -0700828 ixgbe_ptp_convert_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000829}
830
Jacob Keller93501d42014-02-28 15:48:58 -0800831int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
832{
833 struct hwtstamp_config *config = &adapter->tstamp_config;
834
835 return copy_to_user(ifr->ifr_data, config,
836 sizeof(*config)) ? -EFAULT : 0;
837}
838
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000839/**
Jacob Kellera7ef4282014-05-16 05:12:25 +0000840 * ixgbe_ptp_set_timestamp_mode - setup the hardware for the requested mode
841 * @adapter: the private ixgbe adapter structure
842 * @config: the hwtstamp configuration requested
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000843 *
844 * Outgoing time stamping can be enabled and disabled. Play nice and
Jacob Keller93501d42014-02-28 15:48:58 -0800845 * disable it when requested, although it shouldn't cause any overhead
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000846 * when no packet needs it. At most one packet in the queue may be
847 * marked for time stamping, otherwise it would be impossible to tell
848 * for sure to which packet the hardware time stamp belongs.
849 *
850 * Incoming time stamping has to be configured via the hardware
851 * filters. Not all combinations are supported, in particular event
852 * type has to be specified. Matching the kind of event packet is
853 * not supported, with the exception of "all V2 events regardless of
854 * level 2 or 4".
Jacob Kellerc19197a2012-05-22 06:08:37 +0000855 *
856 * Since hardware always timestamps Path delay packets when timestamping V2
857 * packets, regardless of the type specified in the register, only use V2
858 * Event mode. This more accurately tells the user what the hardware is going
859 * to do anyways.
Jacob Kellera7ef4282014-05-16 05:12:25 +0000860 *
861 * Note: this may modify the hwtstamp configuration towards a more general
862 * mode, if required to support the specifically requested mode.
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000863 */
Jacob Kellera7ef4282014-05-16 05:12:25 +0000864static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter,
865 struct hwtstamp_config *config)
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000866{
867 struct ixgbe_hw *hw = &adapter->hw;
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000868 u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED;
869 u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED;
Jacob Kellerf3444d82012-10-24 02:31:47 +0000870 u32 tsync_rx_mtrl = PTP_EV_PORT << 16;
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000871 bool is_l2 = false;
872 u32 regval;
873
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000874 /* reserved for future extensions */
Jacob Kellera7ef4282014-05-16 05:12:25 +0000875 if (config->flags)
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000876 return -EINVAL;
877
Jacob Kellera7ef4282014-05-16 05:12:25 +0000878 switch (config->tx_type) {
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000879 case HWTSTAMP_TX_OFF:
880 tsync_tx_ctl = 0;
881 case HWTSTAMP_TX_ON:
882 break;
883 default:
884 return -ERANGE;
885 }
886
Jacob Kellera7ef4282014-05-16 05:12:25 +0000887 switch (config->rx_filter) {
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000888 case HWTSTAMP_FILTER_NONE:
889 tsync_rx_ctl = 0;
Jacob Kellerf3444d82012-10-24 02:31:47 +0000890 tsync_rx_mtrl = 0;
Mark Rustada9763f32015-10-27 09:58:07 -0700891 adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
892 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000893 break;
894 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
895 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
Jacob Kellerb1e50f72012-12-05 07:53:38 +0000896 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_SYNC_MSG;
Yusuke Suzukiaeb4c732016-11-21 06:48:45 +0000897 adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
898 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000899 break;
900 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
901 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
Jacob Kellerb1e50f72012-12-05 07:53:38 +0000902 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_DELAY_REQ_MSG;
Yusuke Suzukiaeb4c732016-11-21 06:48:45 +0000903 adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
904 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000905 break;
Jacob Kellerc19197a2012-05-22 06:08:37 +0000906 case HWTSTAMP_FILTER_PTP_V2_EVENT:
907 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
908 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000909 case HWTSTAMP_FILTER_PTP_V2_SYNC:
910 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
911 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000912 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
913 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
914 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000915 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2;
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000916 is_l2 = true;
Jacob Kellera7ef4282014-05-16 05:12:25 +0000917 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
Yusuke Suzukiaeb4c732016-11-21 06:48:45 +0000918 adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
919 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000920 break;
921 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
Miroslav Lichvare3412572017-05-19 17:52:36 +0200922 case HWTSTAMP_FILTER_NTP_ALL:
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000923 case HWTSTAMP_FILTER_ALL:
Mark Rustada9763f32015-10-27 09:58:07 -0700924 /* The X550 controller is capable of timestamping all packets,
925 * which allows it to accept any filter.
926 */
927 if (hw->mac.type >= ixgbe_mac_X550) {
928 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_ALL;
929 config->rx_filter = HWTSTAMP_FILTER_ALL;
930 adapter->flags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED;
931 break;
932 }
933 /* fall through */
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000934 default:
935 /*
Jacob Keller1d1a79b2012-05-22 06:18:08 +0000936 * register RXMTRL must be set in order to do V1 packets,
937 * therefore it is not possible to time stamp both V1 Sync and
938 * Delay_Req messages and hardware does not support
939 * timestamping all packets => return error
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000940 */
Mark Rustada9763f32015-10-27 09:58:07 -0700941 adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
942 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
Jacob Kellera7ef4282014-05-16 05:12:25 +0000943 config->rx_filter = HWTSTAMP_FILTER_NONE;
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000944 return -ERANGE;
945 }
946
947 if (hw->mac.type == ixgbe_mac_82598EB) {
Mark Rustada9763f32015-10-27 09:58:07 -0700948 adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
949 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000950 if (tsync_rx_ctl | tsync_tx_ctl)
951 return -ERANGE;
952 return 0;
953 }
954
Mark Rustada9763f32015-10-27 09:58:07 -0700955 /* Per-packet timestamping only works if the filter is set to all
956 * packets. Since this is desired, always timestamp all packets as long
957 * as any Rx filter was configured.
958 */
959 switch (hw->mac.type) {
960 case ixgbe_mac_X550:
961 case ixgbe_mac_X550EM_x:
Mark Rustad49425df2016-04-01 12:18:09 -0700962 case ixgbe_mac_x550em_a:
Mark Rustada9763f32015-10-27 09:58:07 -0700963 /* enable timestamping all packets only if at least some
964 * packets were requested. Otherwise, play nice and disable
965 * timestamping
966 */
967 if (config->rx_filter == HWTSTAMP_FILTER_NONE)
968 break;
969
970 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED |
971 IXGBE_TSYNCRXCTL_TYPE_ALL |
972 IXGBE_TSYNCRXCTL_TSIP_UT_EN;
973 config->rx_filter = HWTSTAMP_FILTER_ALL;
974 adapter->flags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED;
975 adapter->flags &= ~IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER;
976 is_l2 = true;
977 break;
978 default:
979 break;
980 }
981
Jacob Keller6ccf7a52012-10-23 08:09:21 +0000982 /* define ethertype filter for timestamping L2 packets */
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000983 if (is_l2)
Jacob Keller6ccf7a52012-10-23 08:09:21 +0000984 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000985 (IXGBE_ETQF_FILTER_EN | /* enable filter */
986 IXGBE_ETQF_1588 | /* enable timestamping */
987 ETH_P_1588)); /* 1588 eth protocol type */
988 else
Jacob Keller6ccf7a52012-10-23 08:09:21 +0000989 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000990
Jacob Keller3a6a4ed2012-05-01 05:24:58 +0000991 /* enable/disable TX */
992 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
993 regval &= ~IXGBE_TSYNCTXCTL_ENABLED;
994 regval |= tsync_tx_ctl;
995 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval);
996
997 /* enable/disable RX */
998 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
999 regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK);
1000 regval |= tsync_rx_ctl;
1001 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval);
1002
1003 /* define which PTP packets are time stamped */
1004 IXGBE_WRITE_REG(hw, IXGBE_RXMTRL, tsync_rx_mtrl);
1005
1006 IXGBE_WRITE_FLUSH(hw);
1007
1008 /* clear TX/RX time stamp registers, just to be sure */
Mark Rustada9763f32015-10-27 09:58:07 -07001009 ixgbe_ptp_clear_tx_timestamp(adapter);
1010 IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001011
Jacob Kellera7ef4282014-05-16 05:12:25 +00001012 return 0;
1013}
1014
1015/**
1016 * ixgbe_ptp_set_ts_config - user entry point for timestamp mode
1017 * @adapter: pointer to adapter struct
Tony Nguyen5ba643c2017-12-04 11:28:30 -08001018 * @ifr: ioctl data
Jacob Kellera7ef4282014-05-16 05:12:25 +00001019 *
1020 * Set hardware to requested mode. If unsupported, return an error with no
1021 * changes. Otherwise, store the mode for future reference.
1022 */
1023int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
1024{
1025 struct hwtstamp_config config;
1026 int err;
1027
1028 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1029 return -EFAULT;
1030
1031 err = ixgbe_ptp_set_timestamp_mode(adapter, &config);
1032 if (err)
1033 return err;
1034
Jacob Keller93501d42014-02-28 15:48:58 -08001035 /* save these settings for future reference */
1036 memcpy(&adapter->tstamp_config, &config,
1037 sizeof(adapter->tstamp_config));
1038
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001039 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1040 -EFAULT : 0;
1041}
1042
Mark Rustada9763f32015-10-27 09:58:07 -07001043static void ixgbe_ptp_link_speed_adjust(struct ixgbe_adapter *adapter,
1044 u32 *shift, u32 *incval)
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001045{
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001046 /**
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001047 * Scale the NIC cycle counter by a large factor so that
1048 * relatively small corrections to the frequency can be added
1049 * or subtracted. The drawbacks of a large factor include
1050 * (a) the clock register overflows more quickly, (b) the cycle
1051 * counter structure must be able to convert the systime value
1052 * to nanoseconds using only a multiplier and a right-shift,
1053 * and (c) the value must fit within the timinca register space
1054 * => math based on internal DMA clock rate and available bits
Jacob Keller1a71ab22012-08-25 03:54:19 +00001055 *
1056 * Note that when there is no link, internal DMA clock is same as when
1057 * link speed is 10Gb. Set the registers correctly even when link is
1058 * down to preserve the clock setting
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001059 */
Jacob Keller1a71ab22012-08-25 03:54:19 +00001060 switch (adapter->link_speed) {
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001061 case IXGBE_LINK_SPEED_100_FULL:
Mark Rustada9763f32015-10-27 09:58:07 -07001062 *shift = IXGBE_INCVAL_SHIFT_100;
1063 *incval = IXGBE_INCVAL_100;
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001064 break;
1065 case IXGBE_LINK_SPEED_1GB_FULL:
Mark Rustada9763f32015-10-27 09:58:07 -07001066 *shift = IXGBE_INCVAL_SHIFT_1GB;
1067 *incval = IXGBE_INCVAL_1GB;
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001068 break;
1069 case IXGBE_LINK_SPEED_10GB_FULL:
Jacob Keller1a71ab22012-08-25 03:54:19 +00001070 default:
Mark Rustada9763f32015-10-27 09:58:07 -07001071 *shift = IXGBE_INCVAL_SHIFT_10GB;
1072 *incval = IXGBE_INCVAL_10GB;
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001073 break;
1074 }
Mark Rustada9763f32015-10-27 09:58:07 -07001075}
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001076
Mark Rustada9763f32015-10-27 09:58:07 -07001077/**
1078 * ixgbe_ptp_start_cyclecounter - create the cycle counter from hw
1079 * @adapter: pointer to the adapter structure
1080 *
1081 * This function should be called to set the proper values for the TIMINCA
1082 * register and tell the cyclecounter structure what the tick rate of SYSTIME
1083 * is. It does not directly modify SYSTIME registers or the timecounter
1084 * structure. It should be called whenever a new TIMINCA value is necessary,
1085 * such as during initialization or when the link speed changes.
1086 */
1087void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
1088{
1089 struct ixgbe_hw *hw = &adapter->hw;
1090 struct cyclecounter cc;
1091 unsigned long flags;
1092 u32 incval = 0;
1093 u32 tsauxc = 0;
1094 u32 fuse0 = 0;
1095
1096 /* For some of the boards below this mask is technically incorrect.
1097 * The timestamp mask overflows at approximately 61bits. However the
1098 * particular hardware does not overflow on an even bitmask value.
1099 * Instead, it overflows due to conversion of upper 32bits billions of
1100 * cycles. Timecounters are not really intended for this purpose so
1101 * they do not properly function if the overflow point isn't 2^N-1.
1102 * However, the actual SYSTIME values in question take ~138 years to
1103 * overflow. In practice this means they won't actually overflow. A
1104 * proper fix to this problem would require modification of the
1105 * timecounter delta calculations.
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001106 */
Mark Rustada9763f32015-10-27 09:58:07 -07001107 cc.mask = CLOCKSOURCE_MASK(64);
1108 cc.mult = 1;
1109 cc.shift = 0;
1110
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001111 switch (hw->mac.type) {
Mark Rustada9763f32015-10-27 09:58:07 -07001112 case ixgbe_mac_X550EM_x:
1113 /* SYSTIME assumes X550EM_x board frequency is 300Mhz, and is
1114 * designed to represent seconds and nanoseconds when this is
1115 * the case. However, some revisions of hardware have a 400Mhz
1116 * clock and we have to compensate for this frequency
1117 * variation using corrected mult and shift values.
1118 */
1119 fuse0 = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
1120 if (!(fuse0 & IXGBE_FUSES0_300MHZ)) {
1121 cc.mult = 3;
1122 cc.shift = 2;
1123 }
1124 /* fallthrough */
Mark Rustad49425df2016-04-01 12:18:09 -07001125 case ixgbe_mac_x550em_a:
Mark Rustada9763f32015-10-27 09:58:07 -07001126 case ixgbe_mac_X550:
1127 cc.read = ixgbe_ptp_read_X550;
1128
1129 /* enable SYSTIME counter */
1130 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMR, 0);
1131 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0);
1132 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0);
1133 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
1134 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC,
1135 tsauxc & ~IXGBE_TSAUXC_DISABLE_SYSTIME);
1136 IXGBE_WRITE_REG(hw, IXGBE_TSIM, IXGBE_TSIM_TXTS);
1137 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_TIMESYNC);
1138
1139 IXGBE_WRITE_FLUSH(hw);
1140 break;
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001141 case ixgbe_mac_X540:
Mark Rustada9763f32015-10-27 09:58:07 -07001142 cc.read = ixgbe_ptp_read_82599;
1143
1144 ixgbe_ptp_link_speed_adjust(adapter, &cc.shift, &incval);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001145 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
1146 break;
1147 case ixgbe_mac_82599EB:
Mark Rustada9763f32015-10-27 09:58:07 -07001148 cc.read = ixgbe_ptp_read_82599;
1149
1150 ixgbe_ptp_link_speed_adjust(adapter, &cc.shift, &incval);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001151 incval >>= IXGBE_INCVAL_SHIFT_82599;
Mark Rustada9763f32015-10-27 09:58:07 -07001152 cc.shift -= IXGBE_INCVAL_SHIFT_82599;
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001153 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
Jacob Kellerb4f47a42016-04-13 16:08:22 -07001154 BIT(IXGBE_INCPER_SHIFT_82599) | incval);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001155 break;
1156 default:
1157 /* other devices aren't supported */
1158 return;
1159 }
1160
Jacob Keller1a71ab22012-08-25 03:54:19 +00001161 /* update the base incval used to calculate frequency adjustment */
Mark Rutland6aa7de02017-10-23 14:07:29 -07001162 WRITE_ONCE(adapter->base_incval, incval);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001163 smp_mb();
1164
Jacob Keller1a71ab22012-08-25 03:54:19 +00001165 /* need lock to prevent incorrect read while modifying cyclecounter */
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001166 spin_lock_irqsave(&adapter->tmreg_lock, flags);
Mark Rustada9763f32015-10-27 09:58:07 -07001167 memcpy(&adapter->hw_cc, &cc, sizeof(adapter->hw_cc));
Jacob Keller1a71ab22012-08-25 03:54:19 +00001168 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1169}
1170
1171/**
1172 * ixgbe_ptp_reset
1173 * @adapter: the ixgbe private board structure
1174 *
Jacob Kellerd6321402014-05-16 05:12:26 +00001175 * When the MAC resets, all the hardware bits for timesync are reset. This
1176 * function is used to re-enable the device for PTP based on current settings.
1177 * We do lose the current clock time, so just reset the cyclecounter to the
1178 * system real clock time.
1179 *
1180 * This function will maintain hwtstamp_config settings, and resets the SDP
1181 * output if it was enabled.
Jacob Keller1a71ab22012-08-25 03:54:19 +00001182 */
1183void ixgbe_ptp_reset(struct ixgbe_adapter *adapter)
1184{
1185 struct ixgbe_hw *hw = &adapter->hw;
1186 unsigned long flags;
1187
Jacob Kellerd6321402014-05-16 05:12:26 +00001188 /* reset the hardware timestamping mode */
1189 ixgbe_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
Jacob Keller93501d42014-02-28 15:48:58 -08001190
Mark Rustada9763f32015-10-27 09:58:07 -07001191 /* 82598 does not support PTP */
1192 if (hw->mac.type == ixgbe_mac_82598EB)
1193 return;
1194
Jacob Keller1a71ab22012-08-25 03:54:19 +00001195 ixgbe_ptp_start_cyclecounter(adapter);
1196
1197 spin_lock_irqsave(&adapter->tmreg_lock, flags);
Mark Rustada9763f32015-10-27 09:58:07 -07001198 timecounter_init(&adapter->hw_tc, &adapter->hw_cc,
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001199 ktime_to_ns(ktime_get_real()));
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001200 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
Jacob Keller82083672012-08-01 07:12:25 +00001201
Mark Rustada9763f32015-10-27 09:58:07 -07001202 adapter->last_overflow_check = jiffies;
1203
1204 /* Now that the shift has been calculated and the systime
Jacob Keller82083672012-08-01 07:12:25 +00001205 * registers reset, (re-)enable the Clock out feature
1206 */
Mark Rustada9763f32015-10-27 09:58:07 -07001207 if (adapter->ptp_setup_sdp)
1208 adapter->ptp_setup_sdp(adapter);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001209}
1210
1211/**
Jacob Keller63328ad2014-05-16 05:12:27 +00001212 * ixgbe_ptp_create_clock
Ben Hutchings49ce9c22012-07-10 10:56:00 +00001213 * @adapter: the ixgbe private adapter structure
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001214 *
Jacob Keller63328ad2014-05-16 05:12:27 +00001215 * This function performs setup of the user entry point function table and
1216 * initializes the PTP clock device, which is used to access the clock-like
Mark Rustada9763f32015-10-27 09:58:07 -07001217 * features of the PTP core. It will be called by ixgbe_ptp_init, and may
1218 * reuse a previously initialized clock (such as during a suspend/resume
1219 * cycle).
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001220 */
Mark Rustada9763f32015-10-27 09:58:07 -07001221static long ixgbe_ptp_create_clock(struct ixgbe_adapter *adapter)
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001222{
1223 struct net_device *netdev = adapter->netdev;
Jacob Keller63328ad2014-05-16 05:12:27 +00001224 long err;
1225
1226 /* do nothing if we already have a clock device */
1227 if (!IS_ERR_OR_NULL(adapter->ptp_clock))
1228 return 0;
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001229
1230 switch (adapter->hw.mac.type) {
1231 case ixgbe_mac_X540:
Jacob Kellerca324092014-02-25 17:58:54 -08001232 snprintf(adapter->ptp_caps.name,
1233 sizeof(adapter->ptp_caps.name),
1234 "%s", netdev->name);
Jacob E Keller681ae1a2012-05-01 05:24:41 +00001235 adapter->ptp_caps.owner = THIS_MODULE;
1236 adapter->ptp_caps.max_adj = 250000000;
1237 adapter->ptp_caps.n_alarm = 0;
1238 adapter->ptp_caps.n_ext_ts = 0;
1239 adapter->ptp_caps.n_per_out = 0;
1240 adapter->ptp_caps.pps = 1;
Mark Rustada9763f32015-10-27 09:58:07 -07001241 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq_82599;
Jacob E Keller681ae1a2012-05-01 05:24:41 +00001242 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
Richard Cochran91432d12015-03-29 23:12:04 +02001243 adapter->ptp_caps.gettime64 = ixgbe_ptp_gettime;
1244 adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
Jacob Keller04c8de82014-05-16 05:12:24 +00001245 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
Mark Rustada9763f32015-10-27 09:58:07 -07001246 adapter->ptp_setup_sdp = ixgbe_ptp_setup_sdp_x540;
Jacob E Keller681ae1a2012-05-01 05:24:41 +00001247 break;
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001248 case ixgbe_mac_82599EB:
Jacob Kellerca324092014-02-25 17:58:54 -08001249 snprintf(adapter->ptp_caps.name,
1250 sizeof(adapter->ptp_caps.name),
1251 "%s", netdev->name);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001252 adapter->ptp_caps.owner = THIS_MODULE;
1253 adapter->ptp_caps.max_adj = 250000000;
1254 adapter->ptp_caps.n_alarm = 0;
1255 adapter->ptp_caps.n_ext_ts = 0;
1256 adapter->ptp_caps.n_per_out = 0;
1257 adapter->ptp_caps.pps = 0;
Mark Rustada9763f32015-10-27 09:58:07 -07001258 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq_82599;
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001259 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
Richard Cochran91432d12015-03-29 23:12:04 +02001260 adapter->ptp_caps.gettime64 = ixgbe_ptp_gettime;
1261 adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
Jacob Keller04c8de82014-05-16 05:12:24 +00001262 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001263 break;
Mark Rustada9763f32015-10-27 09:58:07 -07001264 case ixgbe_mac_X550:
1265 case ixgbe_mac_X550EM_x:
Mark Rustad49425df2016-04-01 12:18:09 -07001266 case ixgbe_mac_x550em_a:
Mark Rustada9763f32015-10-27 09:58:07 -07001267 snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name);
1268 adapter->ptp_caps.owner = THIS_MODULE;
1269 adapter->ptp_caps.max_adj = 30000000;
1270 adapter->ptp_caps.n_alarm = 0;
1271 adapter->ptp_caps.n_ext_ts = 0;
1272 adapter->ptp_caps.n_per_out = 0;
1273 adapter->ptp_caps.pps = 0;
1274 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq_X550;
1275 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
1276 adapter->ptp_caps.gettime64 = ixgbe_ptp_gettime;
1277 adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
1278 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
1279 adapter->ptp_setup_sdp = NULL;
1280 break;
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001281 default:
1282 adapter->ptp_clock = NULL;
Mark Rustada9763f32015-10-27 09:58:07 -07001283 adapter->ptp_setup_sdp = NULL;
Jacob Keller63328ad2014-05-16 05:12:27 +00001284 return -EOPNOTSUPP;
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001285 }
1286
Richard Cochran1ef76152012-09-22 07:02:03 +00001287 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1288 &adapter->pdev->dev);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001289 if (IS_ERR(adapter->ptp_clock)) {
Jacob Keller63328ad2014-05-16 05:12:27 +00001290 err = PTR_ERR(adapter->ptp_clock);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001291 adapter->ptp_clock = NULL;
1292 e_dev_err("ptp_clock_register failed\n");
Jacob Keller63328ad2014-05-16 05:12:27 +00001293 return err;
Nicolas Pitreefee95f2016-09-20 19:25:58 -04001294 } else if (adapter->ptp_clock)
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001295 e_dev_info("registered PHC device on %s\n", netdev->name);
1296
Jacob Keller63328ad2014-05-16 05:12:27 +00001297 /* set default timestamp mode to disabled here. We do this in
1298 * create_clock instead of init, because we don't want to override the
1299 * previous settings during a resume cycle.
1300 */
Jacob Kellerd6321402014-05-16 05:12:26 +00001301 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1302 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
Jacob Keller63328ad2014-05-16 05:12:27 +00001303
1304 return 0;
1305}
1306
1307/**
1308 * ixgbe_ptp_init
1309 * @adapter: the ixgbe private adapter structure
1310 *
1311 * This function performs the required steps for enabling PTP
1312 * support. If PTP support has already been loaded it simply calls the
1313 * cyclecounter init routine and exits.
1314 */
1315void ixgbe_ptp_init(struct ixgbe_adapter *adapter)
1316{
1317 /* initialize the spin lock first since we can't control when a user
1318 * will call the entry functions once we have initialized the clock
1319 * device
1320 */
1321 spin_lock_init(&adapter->tmreg_lock);
1322
1323 /* obtain a PTP device, or re-use an existing device */
1324 if (ixgbe_ptp_create_clock(adapter))
1325 return;
1326
1327 /* we have a clock so we can initialize work now */
1328 INIT_WORK(&adapter->ptp_tx_work, ixgbe_ptp_tx_hwtstamp_work);
1329
1330 /* reset the PTP related hardware bits */
Jacob Keller1a71ab22012-08-25 03:54:19 +00001331 ixgbe_ptp_reset(adapter);
1332
Jacob Keller8fecf672013-06-21 08:14:32 +00001333 /* enter the IXGBE_PTP_RUNNING state */
1334 set_bit(__IXGBE_PTP_RUNNING, &adapter->state);
Jacob Keller1a71ab22012-08-25 03:54:19 +00001335
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001336 return;
1337}
1338
1339/**
Jacob Keller9966d1e2014-05-16 05:12:28 +00001340 * ixgbe_ptp_suspend - stop PTP work items
Tony Nguyen5ba643c2017-12-04 11:28:30 -08001341 * @adapter: pointer to adapter struct
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001342 *
Jacob Keller9966d1e2014-05-16 05:12:28 +00001343 * this function suspends PTP activity, and prevents more PTP work from being
1344 * generated, but does not destroy the PTP clock device.
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001345 */
Jacob Keller9966d1e2014-05-16 05:12:28 +00001346void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter)
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001347{
Jacob Keller8fecf672013-06-21 08:14:32 +00001348 /* Leave the IXGBE_PTP_RUNNING state. */
1349 if (!test_and_clear_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1350 return;
Jacob Kellerdb0677f2012-08-24 07:46:54 +00001351
Mark Rustada9763f32015-10-27 09:58:07 -07001352 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
1353 if (adapter->ptp_setup_sdp)
1354 adapter->ptp_setup_sdp(adapter);
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001355
Jacob Keller9966d1e2014-05-16 05:12:28 +00001356 /* ensure that we cancel any pending PTP Tx work item in progress */
Jacob Keller891dc082012-12-05 07:24:46 +00001357 cancel_work_sync(&adapter->ptp_tx_work);
Mark Rustada9763f32015-10-27 09:58:07 -07001358 ixgbe_ptp_clear_tx_timestamp(adapter);
Jacob Keller9966d1e2014-05-16 05:12:28 +00001359}
Jacob Keller891dc082012-12-05 07:24:46 +00001360
Jacob Keller9966d1e2014-05-16 05:12:28 +00001361/**
1362 * ixgbe_ptp_stop - close the PTP device
1363 * @adapter: pointer to adapter struct
1364 *
1365 * completely destroy the PTP device, should only be called when the device is
1366 * being fully closed.
1367 */
1368void ixgbe_ptp_stop(struct ixgbe_adapter *adapter)
1369{
1370 /* first, suspend PTP activity */
1371 ixgbe_ptp_suspend(adapter);
1372
1373 /* disable the PTP clock device */
Jacob Keller3a6a4ed2012-05-01 05:24:58 +00001374 if (adapter->ptp_clock) {
1375 ptp_clock_unregister(adapter->ptp_clock);
1376 adapter->ptp_clock = NULL;
1377 e_dev_info("removed PHC on %s\n",
1378 adapter->netdev->name);
1379 }
1380}