Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 1 | /* Copyright 2008 - 2016 Freescale Semiconductor, Inc. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are met: |
| 5 | * * Redistributions of source code must retain the above copyright |
| 6 | * notice, this list of conditions and the following disclaimer. |
| 7 | * * Redistributions in binary form must reproduce the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer in the |
| 9 | * documentation and/or other materials provided with the distribution. |
| 10 | * * Neither the name of Freescale Semiconductor nor the |
| 11 | * names of its contributors may be used to endorse or promote products |
| 12 | * derived from this software without specific prior written permission. |
| 13 | * |
| 14 | * ALTERNATIVELY, this software may be distributed under the terms of the |
| 15 | * GNU General Public License ("GPL") as published by the Free Software |
| 16 | * Foundation, either version 2 of that License or (at your option) any |
| 17 | * later version. |
| 18 | * |
| 19 | * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY |
| 20 | * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 22 | * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY |
| 23 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 26 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __FSL_QMAN_H |
| 32 | #define __FSL_QMAN_H |
| 33 | |
| 34 | #include <linux/bitops.h> |
| 35 | |
| 36 | /* Hardware constants */ |
| 37 | #define QM_CHANNEL_SWPORTAL0 0 |
| 38 | #define QMAN_CHANNEL_POOL1 0x21 |
Horia Geantă | 329d090 | 2017-03-17 12:05:57 +0200 | [diff] [blame] | 39 | #define QMAN_CHANNEL_CAAM 0x80 |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 40 | #define QMAN_CHANNEL_POOL1_REV3 0x401 |
Horia Geantă | 329d090 | 2017-03-17 12:05:57 +0200 | [diff] [blame] | 41 | #define QMAN_CHANNEL_CAAM_REV3 0x840 |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 42 | extern u16 qm_channel_pool1; |
Horia Geantă | 329d090 | 2017-03-17 12:05:57 +0200 | [diff] [blame] | 43 | extern u16 qm_channel_caam; |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 44 | |
| 45 | /* Portal processing (interrupt) sources */ |
| 46 | #define QM_PIRQ_CSCI 0x00100000 /* Congestion State Change */ |
| 47 | #define QM_PIRQ_EQCI 0x00080000 /* Enqueue Command Committed */ |
| 48 | #define QM_PIRQ_EQRI 0x00040000 /* EQCR Ring (below threshold) */ |
| 49 | #define QM_PIRQ_DQRI 0x00020000 /* DQRR Ring (non-empty) */ |
| 50 | #define QM_PIRQ_MRI 0x00010000 /* MR Ring (non-empty) */ |
| 51 | /* |
| 52 | * This mask contains all the interrupt sources that need handling except DQRI, |
| 53 | * ie. that if present should trigger slow-path processing. |
| 54 | */ |
| 55 | #define QM_PIRQ_SLOW (QM_PIRQ_CSCI | QM_PIRQ_EQCI | QM_PIRQ_EQRI | \ |
| 56 | QM_PIRQ_MRI) |
| 57 | |
| 58 | /* For qman_static_dequeue_*** APIs */ |
| 59 | #define QM_SDQCR_CHANNELS_POOL_MASK 0x00007fff |
| 60 | /* for n in [1,15] */ |
| 61 | #define QM_SDQCR_CHANNELS_POOL(n) (0x00008000 >> (n)) |
| 62 | /* for conversion from n of qm_channel */ |
| 63 | static inline u32 QM_SDQCR_CHANNELS_POOL_CONV(u16 channel) |
| 64 | { |
| 65 | return QM_SDQCR_CHANNELS_POOL(channel + 1 - qm_channel_pool1); |
| 66 | } |
| 67 | |
| 68 | /* --- QMan data structures (and associated constants) --- */ |
| 69 | |
| 70 | /* "Frame Descriptor (FD)" */ |
| 71 | struct qm_fd { |
| 72 | union { |
| 73 | struct { |
| 74 | u8 cfg8b_w1; |
| 75 | u8 bpid; /* Buffer Pool ID */ |
| 76 | u8 cfg8b_w3; |
| 77 | u8 addr_hi; /* high 8-bits of 40-bit address */ |
| 78 | __be32 addr_lo; /* low 32-bits of 40-bit address */ |
| 79 | } __packed; |
| 80 | __be64 data; |
| 81 | }; |
| 82 | __be32 cfg; /* format, offset, length / congestion */ |
| 83 | union { |
| 84 | __be32 cmd; |
| 85 | __be32 status; |
| 86 | }; |
| 87 | } __aligned(8); |
| 88 | |
| 89 | #define QM_FD_FORMAT_SG BIT(31) |
| 90 | #define QM_FD_FORMAT_LONG BIT(30) |
| 91 | #define QM_FD_FORMAT_COMPOUND BIT(29) |
| 92 | #define QM_FD_FORMAT_MASK GENMASK(31, 29) |
| 93 | #define QM_FD_OFF_SHIFT 20 |
| 94 | #define QM_FD_OFF_MASK GENMASK(28, 20) |
| 95 | #define QM_FD_LEN_MASK GENMASK(19, 0) |
| 96 | #define QM_FD_LEN_BIG_MASK GENMASK(28, 0) |
| 97 | |
| 98 | enum qm_fd_format { |
| 99 | /* |
| 100 | * 'contig' implies a contiguous buffer, whereas 'sg' implies a |
| 101 | * scatter-gather table. 'big' implies a 29-bit length with no offset |
| 102 | * field, otherwise length is 20-bit and offset is 9-bit. 'compound' |
| 103 | * implies a s/g-like table, where each entry itself represents a frame |
| 104 | * (contiguous or scatter-gather) and the 29-bit "length" is |
| 105 | * interpreted purely for congestion calculations, ie. a "congestion |
| 106 | * weight". |
| 107 | */ |
| 108 | qm_fd_contig = 0, |
| 109 | qm_fd_contig_big = QM_FD_FORMAT_LONG, |
| 110 | qm_fd_sg = QM_FD_FORMAT_SG, |
| 111 | qm_fd_sg_big = QM_FD_FORMAT_SG | QM_FD_FORMAT_LONG, |
| 112 | qm_fd_compound = QM_FD_FORMAT_COMPOUND |
| 113 | }; |
| 114 | |
| 115 | static inline dma_addr_t qm_fd_addr(const struct qm_fd *fd) |
| 116 | { |
| 117 | return be64_to_cpu(fd->data) & 0xffffffffffLLU; |
| 118 | } |
| 119 | |
| 120 | static inline u64 qm_fd_addr_get64(const struct qm_fd *fd) |
| 121 | { |
| 122 | return be64_to_cpu(fd->data) & 0xffffffffffLLU; |
| 123 | } |
| 124 | |
| 125 | static inline void qm_fd_addr_set64(struct qm_fd *fd, u64 addr) |
| 126 | { |
| 127 | fd->addr_hi = upper_32_bits(addr); |
| 128 | fd->addr_lo = cpu_to_be32(lower_32_bits(addr)); |
| 129 | } |
| 130 | |
| 131 | /* |
| 132 | * The 'format' field indicates the interpretation of the remaining |
| 133 | * 29 bits of the 32-bit word. |
| 134 | * If 'format' is _contig or _sg, 20b length and 9b offset. |
| 135 | * If 'format' is _contig_big or _sg_big, 29b length. |
| 136 | * If 'format' is _compound, 29b "congestion weight". |
| 137 | */ |
| 138 | static inline enum qm_fd_format qm_fd_get_format(const struct qm_fd *fd) |
| 139 | { |
| 140 | return be32_to_cpu(fd->cfg) & QM_FD_FORMAT_MASK; |
| 141 | } |
| 142 | |
| 143 | static inline int qm_fd_get_offset(const struct qm_fd *fd) |
| 144 | { |
| 145 | return (be32_to_cpu(fd->cfg) & QM_FD_OFF_MASK) >> QM_FD_OFF_SHIFT; |
| 146 | } |
| 147 | |
| 148 | static inline int qm_fd_get_length(const struct qm_fd *fd) |
| 149 | { |
| 150 | return be32_to_cpu(fd->cfg) & QM_FD_LEN_MASK; |
| 151 | } |
| 152 | |
| 153 | static inline int qm_fd_get_len_big(const struct qm_fd *fd) |
| 154 | { |
| 155 | return be32_to_cpu(fd->cfg) & QM_FD_LEN_BIG_MASK; |
| 156 | } |
| 157 | |
| 158 | static inline void qm_fd_set_param(struct qm_fd *fd, enum qm_fd_format fmt, |
| 159 | int off, int len) |
| 160 | { |
| 161 | fd->cfg = cpu_to_be32(fmt | (len & QM_FD_LEN_BIG_MASK) | |
| 162 | ((off << QM_FD_OFF_SHIFT) & QM_FD_OFF_MASK)); |
| 163 | } |
| 164 | |
| 165 | #define qm_fd_set_contig(fd, off, len) \ |
| 166 | qm_fd_set_param(fd, qm_fd_contig, off, len) |
| 167 | #define qm_fd_set_sg(fd, off, len) qm_fd_set_param(fd, qm_fd_sg, off, len) |
| 168 | #define qm_fd_set_contig_big(fd, len) \ |
| 169 | qm_fd_set_param(fd, qm_fd_contig_big, 0, len) |
| 170 | #define qm_fd_set_sg_big(fd, len) qm_fd_set_param(fd, qm_fd_sg_big, 0, len) |
Horia Geantă | e5c748a | 2017-03-17 12:05:59 +0200 | [diff] [blame] | 171 | #define qm_fd_set_compound(fd, len) qm_fd_set_param(fd, qm_fd_compound, 0, len) |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 172 | |
| 173 | static inline void qm_fd_clear_fd(struct qm_fd *fd) |
| 174 | { |
| 175 | fd->data = 0; |
| 176 | fd->cfg = 0; |
| 177 | fd->cmd = 0; |
| 178 | } |
| 179 | |
| 180 | /* Scatter/Gather table entry */ |
| 181 | struct qm_sg_entry { |
| 182 | union { |
| 183 | struct { |
| 184 | u8 __reserved1[3]; |
| 185 | u8 addr_hi; /* high 8-bits of 40-bit address */ |
| 186 | __be32 addr_lo; /* low 32-bits of 40-bit address */ |
| 187 | }; |
| 188 | __be64 data; |
| 189 | }; |
| 190 | __be32 cfg; /* E bit, F bit, length */ |
| 191 | u8 __reserved2; |
| 192 | u8 bpid; |
| 193 | __be16 offset; /* 13-bit, _res[13-15]*/ |
| 194 | } __packed; |
| 195 | |
| 196 | #define QM_SG_LEN_MASK GENMASK(29, 0) |
| 197 | #define QM_SG_OFF_MASK GENMASK(12, 0) |
| 198 | #define QM_SG_FIN BIT(30) |
| 199 | #define QM_SG_EXT BIT(31) |
| 200 | |
| 201 | static inline dma_addr_t qm_sg_addr(const struct qm_sg_entry *sg) |
| 202 | { |
| 203 | return be64_to_cpu(sg->data) & 0xffffffffffLLU; |
| 204 | } |
| 205 | |
| 206 | static inline u64 qm_sg_entry_get64(const struct qm_sg_entry *sg) |
| 207 | { |
| 208 | return be64_to_cpu(sg->data) & 0xffffffffffLLU; |
| 209 | } |
| 210 | |
| 211 | static inline void qm_sg_entry_set64(struct qm_sg_entry *sg, u64 addr) |
| 212 | { |
| 213 | sg->addr_hi = upper_32_bits(addr); |
| 214 | sg->addr_lo = cpu_to_be32(lower_32_bits(addr)); |
| 215 | } |
| 216 | |
| 217 | static inline bool qm_sg_entry_is_final(const struct qm_sg_entry *sg) |
| 218 | { |
| 219 | return be32_to_cpu(sg->cfg) & QM_SG_FIN; |
| 220 | } |
| 221 | |
| 222 | static inline bool qm_sg_entry_is_ext(const struct qm_sg_entry *sg) |
| 223 | { |
| 224 | return be32_to_cpu(sg->cfg) & QM_SG_EXT; |
| 225 | } |
| 226 | |
| 227 | static inline int qm_sg_entry_get_len(const struct qm_sg_entry *sg) |
| 228 | { |
| 229 | return be32_to_cpu(sg->cfg) & QM_SG_LEN_MASK; |
| 230 | } |
| 231 | |
| 232 | static inline void qm_sg_entry_set_len(struct qm_sg_entry *sg, int len) |
| 233 | { |
| 234 | sg->cfg = cpu_to_be32(len & QM_SG_LEN_MASK); |
| 235 | } |
| 236 | |
| 237 | static inline void qm_sg_entry_set_f(struct qm_sg_entry *sg, int len) |
| 238 | { |
| 239 | sg->cfg = cpu_to_be32(QM_SG_FIN | (len & QM_SG_LEN_MASK)); |
| 240 | } |
| 241 | |
| 242 | static inline int qm_sg_entry_get_off(const struct qm_sg_entry *sg) |
| 243 | { |
| 244 | return be32_to_cpu(sg->offset) & QM_SG_OFF_MASK; |
| 245 | } |
| 246 | |
| 247 | /* "Frame Dequeue Response" */ |
| 248 | struct qm_dqrr_entry { |
| 249 | u8 verb; |
| 250 | u8 stat; |
Claudiu Manoil | 1805882 | 2016-11-16 16:40:30 +0200 | [diff] [blame] | 251 | __be16 seqnum; /* 15-bit */ |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 252 | u8 tok; |
| 253 | u8 __reserved2[3]; |
Claudiu Manoil | 1805882 | 2016-11-16 16:40:30 +0200 | [diff] [blame] | 254 | __be32 fqid; /* 24-bit */ |
| 255 | __be32 context_b; |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 256 | struct qm_fd fd; |
| 257 | u8 __reserved4[32]; |
| 258 | } __packed; |
| 259 | #define QM_DQRR_VERB_VBIT 0x80 |
| 260 | #define QM_DQRR_VERB_MASK 0x7f /* where the verb contains; */ |
| 261 | #define QM_DQRR_VERB_FRAME_DEQUEUE 0x60 /* "this format" */ |
| 262 | #define QM_DQRR_STAT_FQ_EMPTY 0x80 /* FQ empty */ |
| 263 | #define QM_DQRR_STAT_FQ_HELDACTIVE 0x40 /* FQ held active */ |
| 264 | #define QM_DQRR_STAT_FQ_FORCEELIGIBLE 0x20 /* FQ was force-eligible'd */ |
| 265 | #define QM_DQRR_STAT_FD_VALID 0x10 /* has a non-NULL FD */ |
| 266 | #define QM_DQRR_STAT_UNSCHEDULED 0x02 /* Unscheduled dequeue */ |
| 267 | #define QM_DQRR_STAT_DQCR_EXPIRED 0x01 /* VDQCR or PDQCR expired*/ |
| 268 | |
Claudiu Manoil | d6753c7 | 2016-11-16 16:40:25 +0200 | [diff] [blame] | 269 | /* 'fqid' is a 24-bit field in every h/w descriptor */ |
| 270 | #define QM_FQID_MASK GENMASK(23, 0) |
Claudiu Manoil | 1805882 | 2016-11-16 16:40:30 +0200 | [diff] [blame] | 271 | #define qm_fqid_set(p, v) ((p)->fqid = cpu_to_be32((v) & QM_FQID_MASK)) |
| 272 | #define qm_fqid_get(p) (be32_to_cpu((p)->fqid) & QM_FQID_MASK) |
Claudiu Manoil | d6753c7 | 2016-11-16 16:40:25 +0200 | [diff] [blame] | 273 | |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 274 | /* "ERN Message Response" */ |
| 275 | /* "FQ State Change Notification" */ |
| 276 | union qm_mr_entry { |
| 277 | struct { |
| 278 | u8 verb; |
| 279 | u8 __reserved[63]; |
| 280 | }; |
| 281 | struct { |
| 282 | u8 verb; |
| 283 | u8 dca; |
Claudiu Manoil | 1805882 | 2016-11-16 16:40:30 +0200 | [diff] [blame] | 284 | __be16 seqnum; |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 285 | u8 rc; /* Rej Code: 8-bit */ |
Claudiu Manoil | b539945 | 2016-11-16 16:40:26 +0200 | [diff] [blame] | 286 | u8 __reserved[3]; |
Claudiu Manoil | 1805882 | 2016-11-16 16:40:30 +0200 | [diff] [blame] | 287 | __be32 fqid; /* 24-bit */ |
| 288 | __be32 tag; |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 289 | struct qm_fd fd; |
| 290 | u8 __reserved1[32]; |
| 291 | } __packed ern; |
| 292 | struct { |
| 293 | u8 verb; |
| 294 | u8 fqs; /* Frame Queue Status */ |
| 295 | u8 __reserved1[6]; |
Claudiu Manoil | 1805882 | 2016-11-16 16:40:30 +0200 | [diff] [blame] | 296 | __be32 fqid; /* 24-bit */ |
| 297 | __be32 context_b; |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 298 | u8 __reserved2[48]; |
| 299 | } __packed fq; /* FQRN/FQRNI/FQRL/FQPN */ |
| 300 | }; |
| 301 | #define QM_MR_VERB_VBIT 0x80 |
| 302 | /* |
| 303 | * ERNs originating from direct-connect portals ("dcern") use 0x20 as a verb |
| 304 | * which would be invalid as a s/w enqueue verb. A s/w ERN can be distinguished |
| 305 | * from the other MR types by noting if the 0x20 bit is unset. |
| 306 | */ |
| 307 | #define QM_MR_VERB_TYPE_MASK 0x27 |
| 308 | #define QM_MR_VERB_DC_ERN 0x20 |
| 309 | #define QM_MR_VERB_FQRN 0x21 |
| 310 | #define QM_MR_VERB_FQRNI 0x22 |
| 311 | #define QM_MR_VERB_FQRL 0x23 |
| 312 | #define QM_MR_VERB_FQPN 0x24 |
| 313 | #define QM_MR_RC_MASK 0xf0 /* contains one of; */ |
| 314 | #define QM_MR_RC_CGR_TAILDROP 0x00 |
| 315 | #define QM_MR_RC_WRED 0x10 |
| 316 | #define QM_MR_RC_ERROR 0x20 |
| 317 | #define QM_MR_RC_ORPWINDOW_EARLY 0x30 |
| 318 | #define QM_MR_RC_ORPWINDOW_LATE 0x40 |
| 319 | #define QM_MR_RC_FQ_TAILDROP 0x50 |
| 320 | #define QM_MR_RC_ORPWINDOW_RETIRED 0x60 |
| 321 | #define QM_MR_RC_ORP_ZERO 0x70 |
| 322 | #define QM_MR_FQS_ORLPRESENT 0x02 /* ORL fragments to come */ |
| 323 | #define QM_MR_FQS_NOTEMPTY 0x01 /* FQ has enqueued frames */ |
| 324 | |
| 325 | /* |
| 326 | * An identical structure of FQD fields is present in the "Init FQ" command and |
| 327 | * the "Query FQ" result, it's suctioned out into the "struct qm_fqd" type. |
| 328 | * Within that, the 'stashing' and 'taildrop' pieces are also factored out, the |
| 329 | * latter has two inlines to assist with converting to/from the mant+exp |
| 330 | * representation. |
| 331 | */ |
| 332 | struct qm_fqd_stashing { |
| 333 | /* See QM_STASHING_EXCL_<...> */ |
| 334 | u8 exclusive; |
| 335 | /* Numbers of cachelines */ |
| 336 | u8 cl; /* _res[6-7], as[4-5], ds[2-3], cs[0-1] */ |
| 337 | }; |
| 338 | |
| 339 | struct qm_fqd_oac { |
| 340 | /* "Overhead Accounting Control", see QM_OAC_<...> */ |
| 341 | u8 oac; /* oac[6-7], _res[0-5] */ |
| 342 | /* Two's-complement value (-128 to +127) */ |
| 343 | s8 oal; /* "Overhead Accounting Length" */ |
| 344 | }; |
| 345 | |
| 346 | struct qm_fqd { |
| 347 | /* _res[6-7], orprws[3-5], oa[2], olws[0-1] */ |
| 348 | u8 orpc; |
| 349 | u8 cgid; |
| 350 | __be16 fq_ctrl; /* See QM_FQCTRL_<...> */ |
| 351 | __be16 dest_wq; /* channel[3-15], wq[0-2] */ |
| 352 | __be16 ics_cred; /* 15-bit */ |
| 353 | /* |
| 354 | * For "Initialize Frame Queue" commands, the write-enable mask |
| 355 | * determines whether 'td' or 'oac_init' is observed. For query |
| 356 | * commands, this field is always 'td', and 'oac_query' (below) reflects |
| 357 | * the Overhead ACcounting values. |
| 358 | */ |
| 359 | union { |
| 360 | __be16 td; /* "Taildrop": _res[13-15], mant[5-12], exp[0-4] */ |
| 361 | struct qm_fqd_oac oac_init; |
| 362 | }; |
| 363 | __be32 context_b; |
| 364 | union { |
| 365 | /* Treat it as 64-bit opaque */ |
| 366 | __be64 opaque; |
| 367 | struct { |
| 368 | __be32 hi; |
| 369 | __be32 lo; |
| 370 | }; |
| 371 | /* Treat it as s/w portal stashing config */ |
| 372 | /* see "FQD Context_A field used for [...]" */ |
| 373 | struct { |
| 374 | struct qm_fqd_stashing stashing; |
| 375 | /* |
| 376 | * 48-bit address of FQ context to |
| 377 | * stash, must be cacheline-aligned |
| 378 | */ |
| 379 | __be16 context_hi; |
| 380 | __be32 context_lo; |
| 381 | } __packed; |
| 382 | } context_a; |
| 383 | struct qm_fqd_oac oac_query; |
| 384 | } __packed; |
| 385 | |
| 386 | #define QM_FQD_CHAN_OFF 3 |
| 387 | #define QM_FQD_WQ_MASK GENMASK(2, 0) |
| 388 | #define QM_FQD_TD_EXP_MASK GENMASK(4, 0) |
| 389 | #define QM_FQD_TD_MANT_OFF 5 |
| 390 | #define QM_FQD_TD_MANT_MASK GENMASK(12, 5) |
| 391 | #define QM_FQD_TD_MAX 0xe0000000 |
| 392 | #define QM_FQD_TD_MANT_MAX 0xff |
| 393 | #define QM_FQD_OAC_OFF 6 |
| 394 | #define QM_FQD_AS_OFF 4 |
| 395 | #define QM_FQD_DS_OFF 2 |
| 396 | #define QM_FQD_XS_MASK 0x3 |
| 397 | |
| 398 | /* 64-bit converters for context_hi/lo */ |
| 399 | static inline u64 qm_fqd_stashing_get64(const struct qm_fqd *fqd) |
| 400 | { |
| 401 | return be64_to_cpu(fqd->context_a.opaque) & 0xffffffffffffULL; |
| 402 | } |
| 403 | |
| 404 | static inline dma_addr_t qm_fqd_stashing_addr(const struct qm_fqd *fqd) |
| 405 | { |
| 406 | return be64_to_cpu(fqd->context_a.opaque) & 0xffffffffffffULL; |
| 407 | } |
| 408 | |
| 409 | static inline u64 qm_fqd_context_a_get64(const struct qm_fqd *fqd) |
| 410 | { |
| 411 | return qm_fqd_stashing_get64(fqd); |
| 412 | } |
| 413 | |
| 414 | static inline void qm_fqd_stashing_set64(struct qm_fqd *fqd, u64 addr) |
| 415 | { |
Claudiu Manoil | 1805882 | 2016-11-16 16:40:30 +0200 | [diff] [blame] | 416 | fqd->context_a.context_hi = cpu_to_be16(upper_32_bits(addr)); |
| 417 | fqd->context_a.context_lo = cpu_to_be32(lower_32_bits(addr)); |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 418 | } |
| 419 | |
| 420 | static inline void qm_fqd_context_a_set64(struct qm_fqd *fqd, u64 addr) |
| 421 | { |
Claudiu Manoil | 9f3670e | 2016-11-16 16:40:18 +0200 | [diff] [blame] | 422 | fqd->context_a.hi = cpu_to_be32(upper_32_bits(addr)); |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 423 | fqd->context_a.lo = cpu_to_be32(lower_32_bits(addr)); |
| 424 | } |
| 425 | |
| 426 | /* convert a threshold value into mant+exp representation */ |
| 427 | static inline int qm_fqd_set_taildrop(struct qm_fqd *fqd, u32 val, |
| 428 | int roundup) |
| 429 | { |
| 430 | u32 e = 0; |
| 431 | int td, oddbit = 0; |
| 432 | |
| 433 | if (val > QM_FQD_TD_MAX) |
| 434 | return -ERANGE; |
| 435 | |
| 436 | while (val > QM_FQD_TD_MANT_MAX) { |
| 437 | oddbit = val & 1; |
| 438 | val >>= 1; |
| 439 | e++; |
| 440 | if (roundup && oddbit) |
| 441 | val++; |
| 442 | } |
| 443 | |
| 444 | td = (val << QM_FQD_TD_MANT_OFF) & QM_FQD_TD_MANT_MASK; |
| 445 | td |= (e & QM_FQD_TD_EXP_MASK); |
| 446 | fqd->td = cpu_to_be16(td); |
| 447 | return 0; |
| 448 | } |
| 449 | /* and the other direction */ |
| 450 | static inline int qm_fqd_get_taildrop(const struct qm_fqd *fqd) |
| 451 | { |
| 452 | int td = be16_to_cpu(fqd->td); |
| 453 | |
| 454 | return ((td & QM_FQD_TD_MANT_MASK) >> QM_FQD_TD_MANT_OFF) |
| 455 | << (td & QM_FQD_TD_EXP_MASK); |
| 456 | } |
| 457 | |
| 458 | static inline void qm_fqd_set_stashing(struct qm_fqd *fqd, u8 as, u8 ds, u8 cs) |
| 459 | { |
| 460 | struct qm_fqd_stashing *st = &fqd->context_a.stashing; |
| 461 | |
| 462 | st->cl = ((as & QM_FQD_XS_MASK) << QM_FQD_AS_OFF) | |
| 463 | ((ds & QM_FQD_XS_MASK) << QM_FQD_DS_OFF) | |
| 464 | (cs & QM_FQD_XS_MASK); |
| 465 | } |
| 466 | |
| 467 | static inline u8 qm_fqd_get_stashing(const struct qm_fqd *fqd) |
| 468 | { |
| 469 | return fqd->context_a.stashing.cl; |
| 470 | } |
| 471 | |
| 472 | static inline void qm_fqd_set_oac(struct qm_fqd *fqd, u8 val) |
| 473 | { |
| 474 | fqd->oac_init.oac = val << QM_FQD_OAC_OFF; |
| 475 | } |
| 476 | |
| 477 | static inline void qm_fqd_set_oal(struct qm_fqd *fqd, s8 val) |
| 478 | { |
| 479 | fqd->oac_init.oal = val; |
| 480 | } |
| 481 | |
| 482 | static inline void qm_fqd_set_destwq(struct qm_fqd *fqd, int ch, int wq) |
| 483 | { |
| 484 | fqd->dest_wq = cpu_to_be16((ch << QM_FQD_CHAN_OFF) | |
| 485 | (wq & QM_FQD_WQ_MASK)); |
| 486 | } |
| 487 | |
| 488 | static inline int qm_fqd_get_chan(const struct qm_fqd *fqd) |
| 489 | { |
| 490 | return be16_to_cpu(fqd->dest_wq) >> QM_FQD_CHAN_OFF; |
| 491 | } |
| 492 | |
| 493 | static inline int qm_fqd_get_wq(const struct qm_fqd *fqd) |
| 494 | { |
| 495 | return be16_to_cpu(fqd->dest_wq) & QM_FQD_WQ_MASK; |
| 496 | } |
| 497 | |
| 498 | /* See "Frame Queue Descriptor (FQD)" */ |
| 499 | /* Frame Queue Descriptor (FQD) field 'fq_ctrl' uses these constants */ |
| 500 | #define QM_FQCTRL_MASK 0x07ff /* 'fq_ctrl' flags; */ |
| 501 | #define QM_FQCTRL_CGE 0x0400 /* Congestion Group Enable */ |
| 502 | #define QM_FQCTRL_TDE 0x0200 /* Tail-Drop Enable */ |
| 503 | #define QM_FQCTRL_CTXASTASHING 0x0080 /* Context-A stashing */ |
| 504 | #define QM_FQCTRL_CPCSTASH 0x0040 /* CPC Stash Enable */ |
| 505 | #define QM_FQCTRL_FORCESFDR 0x0008 /* High-priority SFDRs */ |
| 506 | #define QM_FQCTRL_AVOIDBLOCK 0x0004 /* Don't block active */ |
| 507 | #define QM_FQCTRL_HOLDACTIVE 0x0002 /* Hold active in portal */ |
| 508 | #define QM_FQCTRL_PREFERINCACHE 0x0001 /* Aggressively cache FQD */ |
| 509 | #define QM_FQCTRL_LOCKINCACHE QM_FQCTRL_PREFERINCACHE /* older naming */ |
| 510 | |
| 511 | /* See "FQD Context_A field used for [...] */ |
| 512 | /* Frame Queue Descriptor (FQD) field 'CONTEXT_A' uses these constants */ |
| 513 | #define QM_STASHING_EXCL_ANNOTATION 0x04 |
| 514 | #define QM_STASHING_EXCL_DATA 0x02 |
| 515 | #define QM_STASHING_EXCL_CTX 0x01 |
| 516 | |
| 517 | /* See "Intra Class Scheduling" */ |
| 518 | /* FQD field 'OAC' (Overhead ACcounting) uses these constants */ |
| 519 | #define QM_OAC_ICS 0x2 /* Accounting for Intra-Class Scheduling */ |
| 520 | #define QM_OAC_CG 0x1 /* Accounting for Congestion Groups */ |
| 521 | |
| 522 | /* |
| 523 | * This struct represents the 32-bit "WR_PARM_[GYR]" parameters in CGR fields |
| 524 | * and associated commands/responses. The WRED parameters are calculated from |
| 525 | * these fields as follows; |
| 526 | * MaxTH = MA * (2 ^ Mn) |
| 527 | * Slope = SA / (2 ^ Sn) |
| 528 | * MaxP = 4 * (Pn + 1) |
| 529 | */ |
| 530 | struct qm_cgr_wr_parm { |
| 531 | /* MA[24-31], Mn[19-23], SA[12-18], Sn[6-11], Pn[0-5] */ |
Claudiu Manoil | 1805882 | 2016-11-16 16:40:30 +0200 | [diff] [blame] | 532 | __be32 word; |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 533 | }; |
| 534 | /* |
| 535 | * This struct represents the 13-bit "CS_THRES" CGR field. In the corresponding |
| 536 | * management commands, this is padded to a 16-bit structure field, so that's |
| 537 | * how we represent it here. The congestion state threshold is calculated from |
| 538 | * these fields as follows; |
| 539 | * CS threshold = TA * (2 ^ Tn) |
| 540 | */ |
| 541 | struct qm_cgr_cs_thres { |
| 542 | /* _res[13-15], TA[5-12], Tn[0-4] */ |
Claudiu Manoil | 1805882 | 2016-11-16 16:40:30 +0200 | [diff] [blame] | 543 | __be16 word; |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 544 | }; |
| 545 | /* |
| 546 | * This identical structure of CGR fields is present in the "Init/Modify CGR" |
| 547 | * commands and the "Query CGR" result. It's suctioned out here into its own |
| 548 | * struct. |
| 549 | */ |
| 550 | struct __qm_mc_cgr { |
| 551 | struct qm_cgr_wr_parm wr_parm_g; |
| 552 | struct qm_cgr_wr_parm wr_parm_y; |
| 553 | struct qm_cgr_wr_parm wr_parm_r; |
| 554 | u8 wr_en_g; /* boolean, use QM_CGR_EN */ |
| 555 | u8 wr_en_y; /* boolean, use QM_CGR_EN */ |
| 556 | u8 wr_en_r; /* boolean, use QM_CGR_EN */ |
| 557 | u8 cscn_en; /* boolean, use QM_CGR_EN */ |
| 558 | union { |
| 559 | struct { |
Claudiu Manoil | 1805882 | 2016-11-16 16:40:30 +0200 | [diff] [blame] | 560 | __be16 cscn_targ_upd_ctrl; /* use QM_CGR_TARG_UDP_* */ |
| 561 | __be16 cscn_targ_dcp_low; |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 562 | }; |
Claudiu Manoil | 1805882 | 2016-11-16 16:40:30 +0200 | [diff] [blame] | 563 | __be32 cscn_targ; /* use QM_CGR_TARG_* */ |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 564 | }; |
| 565 | u8 cstd_en; /* boolean, use QM_CGR_EN */ |
| 566 | u8 cs; /* boolean, only used in query response */ |
| 567 | struct qm_cgr_cs_thres cs_thres; /* use qm_cgr_cs_thres_set64() */ |
| 568 | u8 mode; /* QMAN_CGR_MODE_FRAME not supported in rev1.0 */ |
| 569 | } __packed; |
| 570 | #define QM_CGR_EN 0x01 /* For wr_en_*, cscn_en, cstd_en */ |
| 571 | #define QM_CGR_TARG_UDP_CTRL_WRITE_BIT 0x8000 /* value written to portal bit*/ |
| 572 | #define QM_CGR_TARG_UDP_CTRL_DCP 0x4000 /* 0: SWP, 1: DCP */ |
| 573 | #define QM_CGR_TARG_PORTAL(n) (0x80000000 >> (n)) /* s/w portal, 0-9 */ |
| 574 | #define QM_CGR_TARG_FMAN0 0x00200000 /* direct-connect portal: fman0 */ |
| 575 | #define QM_CGR_TARG_FMAN1 0x00100000 /* : fman1 */ |
| 576 | /* Convert CGR thresholds to/from "cs_thres" format */ |
| 577 | static inline u64 qm_cgr_cs_thres_get64(const struct qm_cgr_cs_thres *th) |
| 578 | { |
Claudiu Manoil | 1805882 | 2016-11-16 16:40:30 +0200 | [diff] [blame] | 579 | int thres = be16_to_cpu(th->word); |
| 580 | |
| 581 | return ((thres >> 5) & 0xff) << (thres & 0x1f); |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 582 | } |
| 583 | |
| 584 | static inline int qm_cgr_cs_thres_set64(struct qm_cgr_cs_thres *th, u64 val, |
| 585 | int roundup) |
| 586 | { |
| 587 | u32 e = 0; |
| 588 | int oddbit = 0; |
| 589 | |
| 590 | while (val > 0xff) { |
| 591 | oddbit = val & 1; |
| 592 | val >>= 1; |
| 593 | e++; |
| 594 | if (roundup && oddbit) |
| 595 | val++; |
| 596 | } |
Claudiu Manoil | 1805882 | 2016-11-16 16:40:30 +0200 | [diff] [blame] | 597 | th->word = cpu_to_be16(((val & 0xff) << 5) | (e & 0x1f)); |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 598 | return 0; |
| 599 | } |
| 600 | |
| 601 | /* "Initialize FQ" */ |
| 602 | struct qm_mcc_initfq { |
| 603 | u8 __reserved1[2]; |
Claudiu Manoil | 1805882 | 2016-11-16 16:40:30 +0200 | [diff] [blame] | 604 | __be16 we_mask; /* Write Enable Mask */ |
| 605 | __be32 fqid; /* 24-bit */ |
| 606 | __be16 count; /* Initialises 'count+1' FQDs */ |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 607 | struct qm_fqd fqd; /* the FQD fields go here */ |
| 608 | u8 __reserved2[30]; |
| 609 | } __packed; |
| 610 | /* "Initialize/Modify CGR" */ |
| 611 | struct qm_mcc_initcgr { |
| 612 | u8 __reserve1[2]; |
Claudiu Manoil | 1805882 | 2016-11-16 16:40:30 +0200 | [diff] [blame] | 613 | __be16 we_mask; /* Write Enable Mask */ |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 614 | struct __qm_mc_cgr cgr; /* CGR fields */ |
| 615 | u8 __reserved2[2]; |
| 616 | u8 cgid; |
| 617 | u8 __reserved3[32]; |
| 618 | } __packed; |
| 619 | |
| 620 | /* INITFQ-specific flags */ |
| 621 | #define QM_INITFQ_WE_MASK 0x01ff /* 'Write Enable' flags; */ |
| 622 | #define QM_INITFQ_WE_OAC 0x0100 |
| 623 | #define QM_INITFQ_WE_ORPC 0x0080 |
| 624 | #define QM_INITFQ_WE_CGID 0x0040 |
| 625 | #define QM_INITFQ_WE_FQCTRL 0x0020 |
| 626 | #define QM_INITFQ_WE_DESTWQ 0x0010 |
| 627 | #define QM_INITFQ_WE_ICSCRED 0x0008 |
| 628 | #define QM_INITFQ_WE_TDTHRESH 0x0004 |
| 629 | #define QM_INITFQ_WE_CONTEXTB 0x0002 |
| 630 | #define QM_INITFQ_WE_CONTEXTA 0x0001 |
| 631 | /* INITCGR/MODIFYCGR-specific flags */ |
| 632 | #define QM_CGR_WE_MASK 0x07ff /* 'Write Enable Mask'; */ |
| 633 | #define QM_CGR_WE_WR_PARM_G 0x0400 |
| 634 | #define QM_CGR_WE_WR_PARM_Y 0x0200 |
| 635 | #define QM_CGR_WE_WR_PARM_R 0x0100 |
| 636 | #define QM_CGR_WE_WR_EN_G 0x0080 |
| 637 | #define QM_CGR_WE_WR_EN_Y 0x0040 |
| 638 | #define QM_CGR_WE_WR_EN_R 0x0020 |
| 639 | #define QM_CGR_WE_CSCN_EN 0x0010 |
| 640 | #define QM_CGR_WE_CSCN_TARG 0x0008 |
| 641 | #define QM_CGR_WE_CSTD_EN 0x0004 |
| 642 | #define QM_CGR_WE_CS_THRES 0x0002 |
| 643 | #define QM_CGR_WE_MODE 0x0001 |
| 644 | |
| 645 | #define QMAN_CGR_FLAG_USE_INIT 0x00000001 |
Horia Geantă | e5c748a | 2017-03-17 12:05:59 +0200 | [diff] [blame] | 646 | #define QMAN_CGR_MODE_FRAME 0x00000001 |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 647 | |
| 648 | /* Portal and Frame Queues */ |
| 649 | /* Represents a managed portal */ |
| 650 | struct qman_portal; |
| 651 | |
| 652 | /* |
| 653 | * This object type represents QMan frame queue descriptors (FQD), it is |
| 654 | * cacheline-aligned, and initialised by qman_create_fq(). The structure is |
| 655 | * defined further down. |
| 656 | */ |
| 657 | struct qman_fq; |
| 658 | |
| 659 | /* |
| 660 | * This object type represents a QMan congestion group, it is defined further |
| 661 | * down. |
| 662 | */ |
| 663 | struct qman_cgr; |
| 664 | |
| 665 | /* |
| 666 | * This enum, and the callback type that returns it, are used when handling |
| 667 | * dequeued frames via DQRR. Note that for "null" callbacks registered with the |
Claudiu Manoil | efe848c | 2016-11-16 16:40:28 +0200 | [diff] [blame] | 668 | * portal object (for handling dequeues that do not demux because context_b is |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 669 | * NULL), the return value *MUST* be qman_cb_dqrr_consume. |
| 670 | */ |
| 671 | enum qman_cb_dqrr_result { |
| 672 | /* DQRR entry can be consumed */ |
| 673 | qman_cb_dqrr_consume, |
| 674 | /* Like _consume, but requests parking - FQ must be held-active */ |
| 675 | qman_cb_dqrr_park, |
| 676 | /* Does not consume, for DCA mode only. */ |
| 677 | qman_cb_dqrr_defer, |
| 678 | /* |
| 679 | * Stop processing without consuming this ring entry. Exits the current |
| 680 | * qman_p_poll_dqrr() or interrupt-handling, as appropriate. If within |
| 681 | * an interrupt handler, the callback would typically call |
| 682 | * qman_irqsource_remove(QM_PIRQ_DQRI) before returning this value, |
| 683 | * otherwise the interrupt will reassert immediately. |
| 684 | */ |
| 685 | qman_cb_dqrr_stop, |
| 686 | /* Like qman_cb_dqrr_stop, but consumes the current entry. */ |
| 687 | qman_cb_dqrr_consume_stop |
| 688 | }; |
| 689 | typedef enum qman_cb_dqrr_result (*qman_cb_dqrr)(struct qman_portal *qm, |
| 690 | struct qman_fq *fq, |
| 691 | const struct qm_dqrr_entry *dqrr); |
| 692 | |
| 693 | /* |
| 694 | * This callback type is used when handling ERNs, FQRNs and FQRLs via MR. They |
| 695 | * are always consumed after the callback returns. |
| 696 | */ |
| 697 | typedef void (*qman_cb_mr)(struct qman_portal *qm, struct qman_fq *fq, |
| 698 | const union qm_mr_entry *msg); |
| 699 | |
| 700 | /* |
| 701 | * s/w-visible states. Ie. tentatively scheduled + truly scheduled + active + |
| 702 | * held-active + held-suspended are just "sched". Things like "retired" will not |
| 703 | * be assumed until it is complete (ie. QMAN_FQ_STATE_CHANGING is set until |
| 704 | * then, to indicate it's completing and to gate attempts to retry the retire |
| 705 | * command). Note, park commands do not set QMAN_FQ_STATE_CHANGING because it's |
| 706 | * technically impossible in the case of enqueue DCAs (which refer to DQRR ring |
| 707 | * index rather than the FQ that ring entry corresponds to), so repeated park |
| 708 | * commands are allowed (if you're silly enough to try) but won't change FQ |
| 709 | * state, and the resulting park notifications move FQs from "sched" to |
| 710 | * "parked". |
| 711 | */ |
| 712 | enum qman_fq_state { |
| 713 | qman_fq_state_oos, |
| 714 | qman_fq_state_parked, |
| 715 | qman_fq_state_sched, |
| 716 | qman_fq_state_retired |
| 717 | }; |
| 718 | |
| 719 | #define QMAN_FQ_STATE_CHANGING 0x80000000 /* 'state' is changing */ |
| 720 | #define QMAN_FQ_STATE_NE 0x40000000 /* retired FQ isn't empty */ |
| 721 | #define QMAN_FQ_STATE_ORL 0x20000000 /* retired FQ has ORL */ |
| 722 | #define QMAN_FQ_STATE_BLOCKOOS 0xe0000000 /* if any are set, no OOS */ |
| 723 | #define QMAN_FQ_STATE_CGR_EN 0x10000000 /* CGR enabled */ |
| 724 | #define QMAN_FQ_STATE_VDQCR 0x08000000 /* being volatile dequeued */ |
| 725 | |
| 726 | /* |
| 727 | * Frame queue objects (struct qman_fq) are stored within memory passed to |
| 728 | * qman_create_fq(), as this allows stashing of caller-provided demux callback |
| 729 | * pointers at no extra cost to stashing of (driver-internal) FQ state. If the |
| 730 | * caller wishes to add per-FQ state and have it benefit from dequeue-stashing, |
| 731 | * they should; |
| 732 | * |
| 733 | * (a) extend the qman_fq structure with their state; eg. |
| 734 | * |
| 735 | * // myfq is allocated and driver_fq callbacks filled in; |
| 736 | * struct my_fq { |
| 737 | * struct qman_fq base; |
| 738 | * int an_extra_field; |
| 739 | * [ ... add other fields to be associated with each FQ ...] |
| 740 | * } *myfq = some_my_fq_allocator(); |
| 741 | * struct qman_fq *fq = qman_create_fq(fqid, flags, &myfq->base); |
| 742 | * |
| 743 | * // in a dequeue callback, access extra fields from 'fq' via a cast; |
| 744 | * struct my_fq *myfq = (struct my_fq *)fq; |
| 745 | * do_something_with(myfq->an_extra_field); |
| 746 | * [...] |
| 747 | * |
| 748 | * (b) when and if configuring the FQ for context stashing, specify how ever |
| 749 | * many cachelines are required to stash 'struct my_fq', to accelerate not |
| 750 | * only the QMan driver but the callback as well. |
| 751 | */ |
| 752 | |
| 753 | struct qman_fq_cb { |
| 754 | qman_cb_dqrr dqrr; /* for dequeued frames */ |
| 755 | qman_cb_mr ern; /* for s/w ERNs */ |
| 756 | qman_cb_mr fqs; /* frame-queue state changes*/ |
| 757 | }; |
| 758 | |
| 759 | struct qman_fq { |
| 760 | /* Caller of qman_create_fq() provides these demux callbacks */ |
| 761 | struct qman_fq_cb cb; |
| 762 | /* |
| 763 | * These are internal to the driver, don't touch. In particular, they |
| 764 | * may change, be removed, or extended (so you shouldn't rely on |
| 765 | * sizeof(qman_fq) being a constant). |
| 766 | */ |
| 767 | u32 fqid, idx; |
| 768 | unsigned long flags; |
| 769 | enum qman_fq_state state; |
| 770 | int cgr_groupid; |
| 771 | }; |
| 772 | |
| 773 | /* |
| 774 | * This callback type is used when handling congestion group entry/exit. |
| 775 | * 'congested' is non-zero on congestion-entry, and zero on congestion-exit. |
| 776 | */ |
| 777 | typedef void (*qman_cb_cgr)(struct qman_portal *qm, |
| 778 | struct qman_cgr *cgr, int congested); |
| 779 | |
| 780 | struct qman_cgr { |
| 781 | /* Set these prior to qman_create_cgr() */ |
| 782 | u32 cgrid; /* 0..255, but u32 to allow specials like -1, 256, etc.*/ |
| 783 | qman_cb_cgr cb; |
| 784 | /* These are private to the driver */ |
| 785 | u16 chan; /* portal channel this object is created on */ |
| 786 | struct list_head node; |
| 787 | }; |
| 788 | |
| 789 | /* Flags to qman_create_fq() */ |
| 790 | #define QMAN_FQ_FLAG_NO_ENQUEUE 0x00000001 /* can't enqueue */ |
| 791 | #define QMAN_FQ_FLAG_NO_MODIFY 0x00000002 /* can only enqueue */ |
| 792 | #define QMAN_FQ_FLAG_TO_DCPORTAL 0x00000004 /* consumed by CAAM/PME/Fman */ |
| 793 | #define QMAN_FQ_FLAG_DYNAMIC_FQID 0x00000020 /* (de)allocate fqid */ |
| 794 | |
| 795 | /* Flags to qman_init_fq() */ |
| 796 | #define QMAN_INITFQ_FLAG_SCHED 0x00000001 /* schedule rather than park */ |
| 797 | #define QMAN_INITFQ_FLAG_LOCAL 0x00000004 /* set dest portal */ |
| 798 | |
Horia Geantă | 1662e93 | 2017-03-17 12:05:56 +0200 | [diff] [blame] | 799 | /* |
| 800 | * For qman_volatile_dequeue(); Choose one PRECEDENCE. EXACT is optional. Use |
| 801 | * NUMFRAMES(n) (6-bit) or NUMFRAMES_TILLEMPTY to fill in the frame-count. Use |
| 802 | * FQID(n) to fill in the frame queue ID. |
| 803 | */ |
| 804 | #define QM_VDQCR_PRECEDENCE_VDQCR 0x0 |
| 805 | #define QM_VDQCR_PRECEDENCE_SDQCR 0x80000000 |
| 806 | #define QM_VDQCR_EXACT 0x40000000 |
| 807 | #define QM_VDQCR_NUMFRAMES_MASK 0x3f000000 |
| 808 | #define QM_VDQCR_NUMFRAMES_SET(n) (((n) & 0x3f) << 24) |
| 809 | #define QM_VDQCR_NUMFRAMES_GET(n) (((n) >> 24) & 0x3f) |
| 810 | #define QM_VDQCR_NUMFRAMES_TILLEMPTY QM_VDQCR_NUMFRAMES_SET(0) |
| 811 | |
| 812 | #define QMAN_VOLATILE_FLAG_WAIT 0x00000001 /* wait if VDQCR is in use */ |
| 813 | #define QMAN_VOLATILE_FLAG_WAIT_INT 0x00000002 /* if wait, interruptible? */ |
| 814 | #define QMAN_VOLATILE_FLAG_FINISH 0x00000004 /* wait till VDQCR completes */ |
| 815 | |
Horia Geantă | 8496272 | 2017-03-17 12:05:58 +0200 | [diff] [blame] | 816 | /* "Query FQ Non-Programmable Fields" */ |
| 817 | struct qm_mcr_queryfq_np { |
| 818 | u8 verb; |
| 819 | u8 result; |
| 820 | u8 __reserved1; |
| 821 | u8 state; /* QM_MCR_NP_STATE_*** */ |
| 822 | u32 fqd_link; /* 24-bit, _res2[24-31] */ |
| 823 | u16 odp_seq; /* 14-bit, _res3[14-15] */ |
| 824 | u16 orp_nesn; /* 14-bit, _res4[14-15] */ |
| 825 | u16 orp_ea_hseq; /* 15-bit, _res5[15] */ |
| 826 | u16 orp_ea_tseq; /* 15-bit, _res6[15] */ |
| 827 | u32 orp_ea_hptr; /* 24-bit, _res7[24-31] */ |
| 828 | u32 orp_ea_tptr; /* 24-bit, _res8[24-31] */ |
| 829 | u32 pfdr_hptr; /* 24-bit, _res9[24-31] */ |
| 830 | u32 pfdr_tptr; /* 24-bit, _res10[24-31] */ |
| 831 | u8 __reserved2[5]; |
| 832 | u8 is; /* 1-bit, _res12[1-7] */ |
| 833 | u16 ics_surp; |
| 834 | u32 byte_cnt; |
| 835 | u32 frm_cnt; /* 24-bit, _res13[24-31] */ |
| 836 | u32 __reserved3; |
| 837 | u16 ra1_sfdr; /* QM_MCR_NP_RA1_*** */ |
| 838 | u16 ra2_sfdr; /* QM_MCR_NP_RA2_*** */ |
| 839 | u16 __reserved4; |
| 840 | u16 od1_sfdr; /* QM_MCR_NP_OD1_*** */ |
| 841 | u16 od2_sfdr; /* QM_MCR_NP_OD2_*** */ |
| 842 | u16 od3_sfdr; /* QM_MCR_NP_OD3_*** */ |
| 843 | } __packed; |
| 844 | |
| 845 | #define QM_MCR_NP_STATE_FE 0x10 |
| 846 | #define QM_MCR_NP_STATE_R 0x08 |
| 847 | #define QM_MCR_NP_STATE_MASK 0x07 /* Reads FQD::STATE; */ |
| 848 | #define QM_MCR_NP_STATE_OOS 0x00 |
| 849 | #define QM_MCR_NP_STATE_RETIRED 0x01 |
| 850 | #define QM_MCR_NP_STATE_TEN_SCHED 0x02 |
| 851 | #define QM_MCR_NP_STATE_TRU_SCHED 0x03 |
| 852 | #define QM_MCR_NP_STATE_PARKED 0x04 |
| 853 | #define QM_MCR_NP_STATE_ACTIVE 0x05 |
| 854 | #define QM_MCR_NP_PTR_MASK 0x07ff /* for RA[12] & OD[123] */ |
| 855 | #define QM_MCR_NP_RA1_NRA(v) (((v) >> 14) & 0x3) /* FQD::NRA */ |
| 856 | #define QM_MCR_NP_RA2_IT(v) (((v) >> 14) & 0x1) /* FQD::IT */ |
| 857 | #define QM_MCR_NP_OD1_NOD(v) (((v) >> 14) & 0x3) /* FQD::NOD */ |
| 858 | #define QM_MCR_NP_OD3_NPC(v) (((v) >> 14) & 0x3) /* FQD::NPC */ |
| 859 | |
| 860 | enum qm_mcr_queryfq_np_masks { |
| 861 | qm_mcr_fqd_link_mask = BIT(24) - 1, |
| 862 | qm_mcr_odp_seq_mask = BIT(14) - 1, |
| 863 | qm_mcr_orp_nesn_mask = BIT(14) - 1, |
| 864 | qm_mcr_orp_ea_hseq_mask = BIT(15) - 1, |
| 865 | qm_mcr_orp_ea_tseq_mask = BIT(15) - 1, |
| 866 | qm_mcr_orp_ea_hptr_mask = BIT(24) - 1, |
| 867 | qm_mcr_orp_ea_tptr_mask = BIT(24) - 1, |
| 868 | qm_mcr_pfdr_hptr_mask = BIT(24) - 1, |
| 869 | qm_mcr_pfdr_tptr_mask = BIT(24) - 1, |
| 870 | qm_mcr_is_mask = BIT(1) - 1, |
| 871 | qm_mcr_frm_cnt_mask = BIT(24) - 1, |
| 872 | }; |
| 873 | |
| 874 | #define qm_mcr_np_get(np, field) \ |
| 875 | ((np)->field & (qm_mcr_##field##_mask)) |
| 876 | |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 877 | /* Portal Management */ |
| 878 | /** |
| 879 | * qman_p_irqsource_add - add processing sources to be interrupt-driven |
| 880 | * @bits: bitmask of QM_PIRQ_**I processing sources |
| 881 | * |
| 882 | * Adds processing sources that should be interrupt-driven (rather than |
| 883 | * processed via qman_poll_***() functions). |
| 884 | */ |
| 885 | void qman_p_irqsource_add(struct qman_portal *p, u32 bits); |
| 886 | |
| 887 | /** |
| 888 | * qman_p_irqsource_remove - remove processing sources from being int-driven |
| 889 | * @bits: bitmask of QM_PIRQ_**I processing sources |
| 890 | * |
| 891 | * Removes processing sources from being interrupt-driven, so that they will |
| 892 | * instead be processed via qman_poll_***() functions. |
| 893 | */ |
| 894 | void qman_p_irqsource_remove(struct qman_portal *p, u32 bits); |
| 895 | |
| 896 | /** |
| 897 | * qman_affine_cpus - return a mask of cpus that have affine portals |
| 898 | */ |
| 899 | const cpumask_t *qman_affine_cpus(void); |
| 900 | |
| 901 | /** |
| 902 | * qman_affine_channel - return the channel ID of an portal |
| 903 | * @cpu: the cpu whose affine portal is the subject of the query |
| 904 | * |
| 905 | * If @cpu is -1, the affine portal for the current CPU will be used. It is a |
| 906 | * bug to call this function for any value of @cpu (other than -1) that is not a |
| 907 | * member of the mask returned from qman_affine_cpus(). |
| 908 | */ |
| 909 | u16 qman_affine_channel(int cpu); |
| 910 | |
| 911 | /** |
| 912 | * qman_get_affine_portal - return the portal pointer affine to cpu |
| 913 | * @cpu: the cpu whose affine portal is the subject of the query |
| 914 | */ |
| 915 | struct qman_portal *qman_get_affine_portal(int cpu); |
| 916 | |
| 917 | /** |
| 918 | * qman_p_poll_dqrr - process DQRR (fast-path) entries |
| 919 | * @limit: the maximum number of DQRR entries to process |
| 920 | * |
| 921 | * Use of this function requires that DQRR processing not be interrupt-driven. |
| 922 | * The return value represents the number of DQRR entries processed. |
| 923 | */ |
| 924 | int qman_p_poll_dqrr(struct qman_portal *p, unsigned int limit); |
| 925 | |
| 926 | /** |
| 927 | * qman_p_static_dequeue_add - Add pool channels to the portal SDQCR |
| 928 | * @pools: bit-mask of pool channels, using QM_SDQCR_CHANNELS_POOL(n) |
| 929 | * |
| 930 | * Adds a set of pool channels to the portal's static dequeue command register |
| 931 | * (SDQCR). The requested pools are limited to those the portal has dequeue |
| 932 | * access to. |
| 933 | */ |
| 934 | void qman_p_static_dequeue_add(struct qman_portal *p, u32 pools); |
| 935 | |
| 936 | /* FQ management */ |
| 937 | /** |
| 938 | * qman_create_fq - Allocates a FQ |
| 939 | * @fqid: the index of the FQD to encapsulate, must be "Out of Service" |
| 940 | * @flags: bit-mask of QMAN_FQ_FLAG_*** options |
| 941 | * @fq: memory for storing the 'fq', with callbacks filled in |
| 942 | * |
| 943 | * Creates a frame queue object for the given @fqid, unless the |
| 944 | * QMAN_FQ_FLAG_DYNAMIC_FQID flag is set in @flags, in which case a FQID is |
| 945 | * dynamically allocated (or the function fails if none are available). Once |
| 946 | * created, the caller should not touch the memory at 'fq' except as extended to |
| 947 | * adjacent memory for user-defined fields (see the definition of "struct |
| 948 | * qman_fq" for more info). NO_MODIFY is only intended for enqueuing to |
| 949 | * pre-existing frame-queues that aren't to be otherwise interfered with, it |
| 950 | * prevents all other modifications to the frame queue. The TO_DCPORTAL flag |
Claudiu Manoil | efe848c | 2016-11-16 16:40:28 +0200 | [diff] [blame] | 951 | * causes the driver to honour any context_b modifications requested in the |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 952 | * qm_init_fq() API, as this indicates the frame queue will be consumed by a |
| 953 | * direct-connect portal (PME, CAAM, or Fman). When frame queues are consumed by |
Claudiu Manoil | efe848c | 2016-11-16 16:40:28 +0200 | [diff] [blame] | 954 | * software portals, the context_b field is controlled by the driver and can't |
| 955 | * be modified by the caller. |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 956 | */ |
| 957 | int qman_create_fq(u32 fqid, u32 flags, struct qman_fq *fq); |
| 958 | |
| 959 | /** |
| 960 | * qman_destroy_fq - Deallocates a FQ |
| 961 | * @fq: the frame queue object to release |
| 962 | * |
| 963 | * The memory for this frame queue object ('fq' provided in qman_create_fq()) is |
| 964 | * not deallocated but the caller regains ownership, to do with as desired. The |
| 965 | * FQ must be in the 'out-of-service' or in the 'parked' state. |
| 966 | */ |
| 967 | void qman_destroy_fq(struct qman_fq *fq); |
| 968 | |
| 969 | /** |
| 970 | * qman_fq_fqid - Queries the frame queue ID of a FQ object |
| 971 | * @fq: the frame queue object to query |
| 972 | */ |
| 973 | u32 qman_fq_fqid(struct qman_fq *fq); |
| 974 | |
| 975 | /** |
| 976 | * qman_init_fq - Initialises FQ fields, leaves the FQ "parked" or "scheduled" |
| 977 | * @fq: the frame queue object to modify, must be 'parked' or new. |
| 978 | * @flags: bit-mask of QMAN_INITFQ_FLAG_*** options |
| 979 | * @opts: the FQ-modification settings, as defined in the low-level API |
| 980 | * |
| 981 | * The @opts parameter comes from the low-level portal API. Select |
| 982 | * QMAN_INITFQ_FLAG_SCHED in @flags to cause the frame queue to be scheduled |
| 983 | * rather than parked. NB, @opts can be NULL. |
| 984 | * |
| 985 | * Note that some fields and options within @opts may be ignored or overwritten |
| 986 | * by the driver; |
| 987 | * 1. the 'count' and 'fqid' fields are always ignored (this operation only |
| 988 | * affects one frame queue: @fq). |
| 989 | * 2. the QM_INITFQ_WE_CONTEXTB option of the 'we_mask' field and the associated |
| 990 | * 'fqd' structure's 'context_b' field are sometimes overwritten; |
| 991 | * - if @fq was not created with QMAN_FQ_FLAG_TO_DCPORTAL, then context_b is |
| 992 | * initialised to a value used by the driver for demux. |
| 993 | * - if context_b is initialised for demux, so is context_a in case stashing |
| 994 | * is requested (see item 4). |
| 995 | * (So caller control of context_b is only possible for TO_DCPORTAL frame queue |
| 996 | * objects.) |
| 997 | * 3. if @flags contains QMAN_INITFQ_FLAG_LOCAL, the 'fqd' structure's |
| 998 | * 'dest::channel' field will be overwritten to match the portal used to issue |
| 999 | * the command. If the WE_DESTWQ write-enable bit had already been set by the |
| 1000 | * caller, the channel workqueue will be left as-is, otherwise the write-enable |
| 1001 | * bit is set and the workqueue is set to a default of 4. If the "LOCAL" flag |
| 1002 | * isn't set, the destination channel/workqueue fields and the write-enable bit |
| 1003 | * are left as-is. |
| 1004 | * 4. if the driver overwrites context_a/b for demux, then if |
| 1005 | * QM_INITFQ_WE_CONTEXTA is set, the driver will only overwrite |
| 1006 | * context_a.address fields and will leave the stashing fields provided by the |
| 1007 | * user alone, otherwise it will zero out the context_a.stashing fields. |
| 1008 | */ |
| 1009 | int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts); |
| 1010 | |
| 1011 | /** |
| 1012 | * qman_schedule_fq - Schedules a FQ |
| 1013 | * @fq: the frame queue object to schedule, must be 'parked' |
| 1014 | * |
| 1015 | * Schedules the frame queue, which must be Parked, which takes it to |
| 1016 | * Tentatively-Scheduled or Truly-Scheduled depending on its fill-level. |
| 1017 | */ |
| 1018 | int qman_schedule_fq(struct qman_fq *fq); |
| 1019 | |
| 1020 | /** |
| 1021 | * qman_retire_fq - Retires a FQ |
| 1022 | * @fq: the frame queue object to retire |
| 1023 | * @flags: FQ flags (QMAN_FQ_STATE*) if retirement completes immediately |
| 1024 | * |
| 1025 | * Retires the frame queue. This returns zero if it succeeds immediately, +1 if |
| 1026 | * the retirement was started asynchronously, otherwise it returns negative for |
| 1027 | * failure. When this function returns zero, @flags is set to indicate whether |
| 1028 | * the retired FQ is empty and/or whether it has any ORL fragments (to show up |
| 1029 | * as ERNs). Otherwise the corresponding flags will be known when a subsequent |
| 1030 | * FQRN message shows up on the portal's message ring. |
| 1031 | * |
| 1032 | * NB, if the retirement is asynchronous (the FQ was in the Truly Scheduled or |
| 1033 | * Active state), the completion will be via the message ring as a FQRN - but |
| 1034 | * the corresponding callback may occur before this function returns!! Ie. the |
| 1035 | * caller should be prepared to accept the callback as the function is called, |
| 1036 | * not only once it has returned. |
| 1037 | */ |
| 1038 | int qman_retire_fq(struct qman_fq *fq, u32 *flags); |
| 1039 | |
| 1040 | /** |
| 1041 | * qman_oos_fq - Puts a FQ "out of service" |
| 1042 | * @fq: the frame queue object to be put out-of-service, must be 'retired' |
| 1043 | * |
| 1044 | * The frame queue must be retired and empty, and if any order restoration list |
| 1045 | * was released as ERNs at the time of retirement, they must all be consumed. |
| 1046 | */ |
| 1047 | int qman_oos_fq(struct qman_fq *fq); |
| 1048 | |
Horia Geantă | 1662e93 | 2017-03-17 12:05:56 +0200 | [diff] [blame] | 1049 | /* |
| 1050 | * qman_volatile_dequeue - Issue a volatile dequeue command |
| 1051 | * @fq: the frame queue object to dequeue from |
| 1052 | * @flags: a bit-mask of QMAN_VOLATILE_FLAG_*** options |
| 1053 | * @vdqcr: bit mask of QM_VDQCR_*** options, as per qm_dqrr_vdqcr_set() |
| 1054 | * |
| 1055 | * Attempts to lock access to the portal's VDQCR volatile dequeue functionality. |
| 1056 | * The function will block and sleep if QMAN_VOLATILE_FLAG_WAIT is specified and |
| 1057 | * the VDQCR is already in use, otherwise returns non-zero for failure. If |
| 1058 | * QMAN_VOLATILE_FLAG_FINISH is specified, the function will only return once |
| 1059 | * the VDQCR command has finished executing (ie. once the callback for the last |
| 1060 | * DQRR entry resulting from the VDQCR command has been called). If not using |
| 1061 | * the FINISH flag, completion can be determined either by detecting the |
| 1062 | * presence of the QM_DQRR_STAT_UNSCHEDULED and QM_DQRR_STAT_DQCR_EXPIRED bits |
| 1063 | * in the "stat" parameter passed to the FQ's dequeue callback, or by waiting |
| 1064 | * for the QMAN_FQ_STATE_VDQCR bit to disappear. |
| 1065 | */ |
| 1066 | int qman_volatile_dequeue(struct qman_fq *fq, u32 flags, u32 vdqcr); |
| 1067 | |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 1068 | /** |
| 1069 | * qman_enqueue - Enqueue a frame to a frame queue |
| 1070 | * @fq: the frame queue object to enqueue to |
| 1071 | * @fd: a descriptor of the frame to be enqueued |
| 1072 | * |
| 1073 | * Fills an entry in the EQCR of portal @qm to enqueue the frame described by |
| 1074 | * @fd. The descriptor details are copied from @fd to the EQCR entry, the 'pid' |
| 1075 | * field is ignored. The return value is non-zero on error, such as ring full. |
| 1076 | */ |
| 1077 | int qman_enqueue(struct qman_fq *fq, const struct qm_fd *fd); |
| 1078 | |
| 1079 | /** |
| 1080 | * qman_alloc_fqid_range - Allocate a contiguous range of FQIDs |
| 1081 | * @result: is set by the API to the base FQID of the allocated range |
| 1082 | * @count: the number of FQIDs required |
| 1083 | * |
| 1084 | * Returns 0 on success, or a negative error code. |
| 1085 | */ |
| 1086 | int qman_alloc_fqid_range(u32 *result, u32 count); |
| 1087 | #define qman_alloc_fqid(result) qman_alloc_fqid_range(result, 1) |
| 1088 | |
| 1089 | /** |
| 1090 | * qman_release_fqid - Release the specified frame queue ID |
| 1091 | * @fqid: the FQID to be released back to the resource pool |
| 1092 | * |
| 1093 | * This function can also be used to seed the allocator with |
| 1094 | * FQID ranges that it can subsequently allocate from. |
| 1095 | * Returns 0 on success, or a negative error code. |
| 1096 | */ |
| 1097 | int qman_release_fqid(u32 fqid); |
| 1098 | |
Horia Geantă | 8496272 | 2017-03-17 12:05:58 +0200 | [diff] [blame] | 1099 | /** |
| 1100 | * qman_query_fq_np - Queries non-programmable FQD fields |
| 1101 | * @fq: the frame queue object to be queried |
| 1102 | * @np: storage for the queried FQD fields |
| 1103 | */ |
| 1104 | int qman_query_fq_np(struct qman_fq *fq, struct qm_mcr_queryfq_np *np); |
| 1105 | |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 1106 | /* Pool-channel management */ |
| 1107 | /** |
| 1108 | * qman_alloc_pool_range - Allocate a contiguous range of pool-channel IDs |
| 1109 | * @result: is set by the API to the base pool-channel ID of the allocated range |
| 1110 | * @count: the number of pool-channel IDs required |
| 1111 | * |
| 1112 | * Returns 0 on success, or a negative error code. |
| 1113 | */ |
| 1114 | int qman_alloc_pool_range(u32 *result, u32 count); |
| 1115 | #define qman_alloc_pool(result) qman_alloc_pool_range(result, 1) |
| 1116 | |
| 1117 | /** |
| 1118 | * qman_release_pool - Release the specified pool-channel ID |
| 1119 | * @id: the pool-chan ID to be released back to the resource pool |
| 1120 | * |
| 1121 | * This function can also be used to seed the allocator with |
| 1122 | * pool-channel ID ranges that it can subsequently allocate from. |
| 1123 | * Returns 0 on success, or a negative error code. |
| 1124 | */ |
| 1125 | int qman_release_pool(u32 id); |
| 1126 | |
| 1127 | /* CGR management */ |
| 1128 | /** |
| 1129 | * qman_create_cgr - Register a congestion group object |
| 1130 | * @cgr: the 'cgr' object, with fields filled in |
| 1131 | * @flags: QMAN_CGR_FLAG_* values |
| 1132 | * @opts: optional state of CGR settings |
| 1133 | * |
| 1134 | * Registers this object to receiving congestion entry/exit callbacks on the |
| 1135 | * portal affine to the cpu portal on which this API is executed. If opts is |
| 1136 | * NULL then only the callback (cgr->cb) function is registered. If @flags |
| 1137 | * contains QMAN_CGR_FLAG_USE_INIT, then an init hw command (which will reset |
| 1138 | * any unspecified parameters) will be used rather than a modify hw hardware |
| 1139 | * (which only modifies the specified parameters). |
| 1140 | */ |
| 1141 | int qman_create_cgr(struct qman_cgr *cgr, u32 flags, |
| 1142 | struct qm_mcc_initcgr *opts); |
| 1143 | |
| 1144 | /** |
| 1145 | * qman_delete_cgr - Deregisters a congestion group object |
| 1146 | * @cgr: the 'cgr' object to deregister |
| 1147 | * |
| 1148 | * "Unplugs" this CGR object from the portal affine to the cpu on which this API |
| 1149 | * is executed. This must be excuted on the same affine portal on which it was |
| 1150 | * created. |
| 1151 | */ |
| 1152 | int qman_delete_cgr(struct qman_cgr *cgr); |
| 1153 | |
| 1154 | /** |
| 1155 | * qman_delete_cgr_safe - Deregisters a congestion group object from any CPU |
| 1156 | * @cgr: the 'cgr' object to deregister |
| 1157 | * |
| 1158 | * This will select the proper CPU and run there qman_delete_cgr(). |
| 1159 | */ |
| 1160 | void qman_delete_cgr_safe(struct qman_cgr *cgr); |
| 1161 | |
| 1162 | /** |
| 1163 | * qman_query_cgr_congested - Queries CGR's congestion status |
| 1164 | * @cgr: the 'cgr' object to query |
| 1165 | * @result: returns 'cgr's congestion status, 1 (true) if congested |
| 1166 | */ |
| 1167 | int qman_query_cgr_congested(struct qman_cgr *cgr, bool *result); |
| 1168 | |
| 1169 | /** |
| 1170 | * qman_alloc_cgrid_range - Allocate a contiguous range of CGR IDs |
| 1171 | * @result: is set by the API to the base CGR ID of the allocated range |
| 1172 | * @count: the number of CGR IDs required |
| 1173 | * |
| 1174 | * Returns 0 on success, or a negative error code. |
| 1175 | */ |
| 1176 | int qman_alloc_cgrid_range(u32 *result, u32 count); |
| 1177 | #define qman_alloc_cgrid(result) qman_alloc_cgrid_range(result, 1) |
| 1178 | |
| 1179 | /** |
| 1180 | * qman_release_cgrid - Release the specified CGR ID |
| 1181 | * @id: the CGR ID to be released back to the resource pool |
| 1182 | * |
| 1183 | * This function can also be used to seed the allocator with |
| 1184 | * CGR ID ranges that it can subsequently allocate from. |
| 1185 | * Returns 0 on success, or a negative error code. |
| 1186 | */ |
| 1187 | int qman_release_cgrid(u32 id); |
| 1188 | |
Laurentiu Tudor | 853dc10 | 2018-09-26 16:22:30 +0300 | [diff] [blame] | 1189 | /** |
| 1190 | * qman_is_probed - Check if qman is probed |
| 1191 | * |
| 1192 | * Returns 1 if the qman driver successfully probed, -1 if the qman driver |
| 1193 | * failed to probe or 0 if the qman driver did not probed yet. |
| 1194 | */ |
| 1195 | int qman_is_probed(void); |
| 1196 | |
Madalin Bucur | 6d06009 | 2018-09-28 11:43:24 +0300 | [diff] [blame] | 1197 | /** |
| 1198 | * qman_dqrr_get_ithresh - Get coalesce interrupt threshold |
| 1199 | * @portal: portal to get the value for |
| 1200 | * @ithresh: threshold pointer |
| 1201 | */ |
| 1202 | void qman_dqrr_get_ithresh(struct qman_portal *portal, u8 *ithresh); |
| 1203 | |
| 1204 | /** |
| 1205 | * qman_dqrr_set_ithresh - Set coalesce interrupt threshold |
| 1206 | * @portal: portal to set the new value on |
| 1207 | * @ithresh: new threshold value |
Madalin Bucur | 5c664ace | 2018-11-21 13:41:08 +0200 | [diff] [blame] | 1208 | * |
| 1209 | * Returns 0 on success, or a negative error code. |
Madalin Bucur | 6d06009 | 2018-09-28 11:43:24 +0300 | [diff] [blame] | 1210 | */ |
Madalin Bucur | 5c664ace | 2018-11-21 13:41:08 +0200 | [diff] [blame] | 1211 | int qman_dqrr_set_ithresh(struct qman_portal *portal, u8 ithresh); |
Madalin Bucur | 6d06009 | 2018-09-28 11:43:24 +0300 | [diff] [blame] | 1212 | |
| 1213 | /** |
| 1214 | * qman_dqrr_get_iperiod - Get coalesce interrupt period |
| 1215 | * @portal: portal to get the value for |
| 1216 | * @iperiod: period pointer |
| 1217 | */ |
| 1218 | void qman_portal_get_iperiod(struct qman_portal *portal, u32 *iperiod); |
| 1219 | |
| 1220 | /** |
| 1221 | * qman_dqrr_set_iperiod - Set coalesce interrupt period |
| 1222 | * @portal: portal to set the new value on |
| 1223 | * @ithresh: new period value |
Madalin Bucur | 5c664ace | 2018-11-21 13:41:08 +0200 | [diff] [blame] | 1224 | * |
| 1225 | * Returns 0 on success, or a negative error code. |
Madalin Bucur | 6d06009 | 2018-09-28 11:43:24 +0300 | [diff] [blame] | 1226 | */ |
Madalin Bucur | 5c664ace | 2018-11-21 13:41:08 +0200 | [diff] [blame] | 1227 | int qman_portal_set_iperiod(struct qman_portal *portal, u32 iperiod); |
Madalin Bucur | 6d06009 | 2018-09-28 11:43:24 +0300 | [diff] [blame] | 1228 | |
Claudiu Manoil | c535e92 | 2016-09-22 18:04:09 +0300 | [diff] [blame] | 1229 | #endif /* __FSL_QMAN_H */ |