Thomas Gleixner | d2912cb | 2019-06-04 10:11:33 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 2 | /* |
| 3 | * PWM driver for Rockchip SoCs |
| 4 | * |
| 5 | * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> |
Caesar Wang | f630629 | 2014-08-08 15:28:49 +0800 | [diff] [blame] | 6 | * Copyright (C) 2014 ROCKCHIP, Inc. |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <linux/clk.h> |
| 10 | #include <linux/io.h> |
| 11 | #include <linux/module.h> |
| 12 | #include <linux/of.h> |
Caesar Wang | f630629 | 2014-08-08 15:28:49 +0800 | [diff] [blame] | 13 | #include <linux/of_device.h> |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 14 | #include <linux/platform_device.h> |
| 15 | #include <linux/pwm.h> |
| 16 | #include <linux/time.h> |
| 17 | |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 18 | #define PWM_CTRL_TIMER_EN (1 << 0) |
| 19 | #define PWM_CTRL_OUTPUT_EN (1 << 3) |
| 20 | |
Caesar Wang | f630629 | 2014-08-08 15:28:49 +0800 | [diff] [blame] | 21 | #define PWM_ENABLE (1 << 0) |
| 22 | #define PWM_CONTINUOUS (1 << 1) |
| 23 | #define PWM_DUTY_POSITIVE (1 << 3) |
Doug Anderson | 7264354 | 2014-08-25 15:59:25 -0700 | [diff] [blame] | 24 | #define PWM_DUTY_NEGATIVE (0 << 3) |
Caesar Wang | f630629 | 2014-08-08 15:28:49 +0800 | [diff] [blame] | 25 | #define PWM_INACTIVE_NEGATIVE (0 << 4) |
Doug Anderson | 7264354 | 2014-08-25 15:59:25 -0700 | [diff] [blame] | 26 | #define PWM_INACTIVE_POSITIVE (1 << 4) |
David Wu | bc834d7 | 2017-08-08 23:38:32 +0800 | [diff] [blame] | 27 | #define PWM_POLARITY_MASK (PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE) |
Caesar Wang | f630629 | 2014-08-08 15:28:49 +0800 | [diff] [blame] | 28 | #define PWM_OUTPUT_LEFT (0 << 5) |
David Wu | 3f9a363 | 2017-08-08 23:42:47 +0800 | [diff] [blame] | 29 | #define PWM_LOCK_EN (1 << 6) |
Caesar Wang | f630629 | 2014-08-08 15:28:49 +0800 | [diff] [blame] | 30 | #define PWM_LP_DISABLE (0 << 8) |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 31 | |
| 32 | struct rockchip_pwm_chip { |
| 33 | struct pwm_chip chip; |
| 34 | struct clk *clk; |
David Wu | 27922ff5 | 2017-08-08 23:38:29 +0800 | [diff] [blame] | 35 | struct clk *pclk; |
Caesar Wang | f630629 | 2014-08-08 15:28:49 +0800 | [diff] [blame] | 36 | const struct rockchip_pwm_data *data; |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 37 | void __iomem *base; |
| 38 | }; |
| 39 | |
Caesar Wang | f630629 | 2014-08-08 15:28:49 +0800 | [diff] [blame] | 40 | struct rockchip_pwm_regs { |
| 41 | unsigned long duty; |
| 42 | unsigned long period; |
| 43 | unsigned long cntr; |
| 44 | unsigned long ctrl; |
| 45 | }; |
| 46 | |
| 47 | struct rockchip_pwm_data { |
| 48 | struct rockchip_pwm_regs regs; |
| 49 | unsigned int prescaler; |
Boris Brezillon | 2bf1c98 | 2016-06-14 11:13:14 +0200 | [diff] [blame] | 50 | bool supports_polarity; |
David Wu | 3f9a363 | 2017-08-08 23:42:47 +0800 | [diff] [blame] | 51 | bool supports_lock; |
David Wu | 831b279 | 2017-08-08 23:41:28 +0800 | [diff] [blame] | 52 | u32 enable_conf; |
Caesar Wang | f630629 | 2014-08-08 15:28:49 +0800 | [diff] [blame] | 53 | }; |
| 54 | |
Uwe Kleine-König | 454a8f5 | 2023-07-14 22:56:20 +0200 | [diff] [blame] | 55 | static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *chip) |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 56 | { |
Uwe Kleine-König | 454a8f5 | 2023-07-14 22:56:20 +0200 | [diff] [blame] | 57 | return container_of(chip, struct rockchip_pwm_chip, chip); |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 58 | } |
| 59 | |
Uwe Kleine-König | 6c452cf | 2022-12-02 19:35:26 +0100 | [diff] [blame] | 60 | static int rockchip_pwm_get_state(struct pwm_chip *chip, |
| 61 | struct pwm_device *pwm, |
| 62 | struct pwm_state *state) |
Boris Brezillon | 1ebb74c | 2016-06-14 11:13:12 +0200 | [diff] [blame] | 63 | { |
| 64 | struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); |
David Wu | 831b279 | 2017-08-08 23:41:28 +0800 | [diff] [blame] | 65 | u32 enable_conf = pc->data->enable_conf; |
Boris Brezillon | 1ebb74c | 2016-06-14 11:13:12 +0200 | [diff] [blame] | 66 | unsigned long clk_rate; |
| 67 | u64 tmp; |
David Wu | 831b279 | 2017-08-08 23:41:28 +0800 | [diff] [blame] | 68 | u32 val; |
Boris Brezillon | 1ebb74c | 2016-06-14 11:13:12 +0200 | [diff] [blame] | 69 | int ret; |
| 70 | |
David Wu | 27922ff5 | 2017-08-08 23:38:29 +0800 | [diff] [blame] | 71 | ret = clk_enable(pc->pclk); |
Boris Brezillon | 1ebb74c | 2016-06-14 11:13:12 +0200 | [diff] [blame] | 72 | if (ret) |
Uwe Kleine-König | 790a8ba | 2022-12-02 19:35:34 +0100 | [diff] [blame] | 73 | return ret; |
Boris Brezillon | 1ebb74c | 2016-06-14 11:13:12 +0200 | [diff] [blame] | 74 | |
Simon South | 11be938 | 2021-01-19 11:12:09 -0500 | [diff] [blame] | 75 | ret = clk_enable(pc->clk); |
| 76 | if (ret) |
Uwe Kleine-König | 790a8ba | 2022-12-02 19:35:34 +0100 | [diff] [blame] | 77 | return ret; |
Simon South | 11be938 | 2021-01-19 11:12:09 -0500 | [diff] [blame] | 78 | |
Boris Brezillon | 1ebb74c | 2016-06-14 11:13:12 +0200 | [diff] [blame] | 79 | clk_rate = clk_get_rate(pc->clk); |
| 80 | |
| 81 | tmp = readl_relaxed(pc->base + pc->data->regs.period); |
| 82 | tmp *= pc->data->prescaler * NSEC_PER_SEC; |
| 83 | state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); |
| 84 | |
| 85 | tmp = readl_relaxed(pc->base + pc->data->regs.duty); |
| 86 | tmp *= pc->data->prescaler * NSEC_PER_SEC; |
David Wu | 831b279 | 2017-08-08 23:41:28 +0800 | [diff] [blame] | 87 | state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); |
Boris Brezillon | 1ebb74c | 2016-06-14 11:13:12 +0200 | [diff] [blame] | 88 | |
David Wu | 831b279 | 2017-08-08 23:41:28 +0800 | [diff] [blame] | 89 | val = readl_relaxed(pc->base + pc->data->regs.ctrl); |
Rasmus Villemoes | cad0f29 | 2019-09-19 11:17:27 +0200 | [diff] [blame] | 90 | state->enabled = (val & enable_conf) == enable_conf; |
David Wu | 831b279 | 2017-08-08 23:41:28 +0800 | [diff] [blame] | 91 | |
Uwe Kleine-König | ba73deb | 2019-09-02 16:39:41 +0200 | [diff] [blame] | 92 | if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE)) |
| 93 | state->polarity = PWM_POLARITY_INVERSED; |
| 94 | else |
| 95 | state->polarity = PWM_POLARITY_NORMAL; |
Boris Brezillon | 1ebb74c | 2016-06-14 11:13:12 +0200 | [diff] [blame] | 96 | |
Simon South | 11be938 | 2021-01-19 11:12:09 -0500 | [diff] [blame] | 97 | clk_disable(pc->clk); |
David Wu | 27922ff5 | 2017-08-08 23:38:29 +0800 | [diff] [blame] | 98 | clk_disable(pc->pclk); |
Uwe Kleine-König | 6c452cf | 2022-12-02 19:35:26 +0100 | [diff] [blame] | 99 | |
| 100 | return 0; |
Boris Brezillon | 1ebb74c | 2016-06-14 11:13:12 +0200 | [diff] [blame] | 101 | } |
| 102 | |
David Wu | f90df9c | 2017-08-08 23:38:30 +0800 | [diff] [blame] | 103 | static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, |
Uwe Kleine-König | 71523d1 | 2019-08-24 17:37:07 +0200 | [diff] [blame] | 104 | const struct pwm_state *state) |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 105 | { |
| 106 | struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); |
| 107 | unsigned long period, duty; |
| 108 | u64 clk_rate, div; |
David Wu | bc834d7 | 2017-08-08 23:38:32 +0800 | [diff] [blame] | 109 | u32 ctrl; |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 110 | |
| 111 | clk_rate = clk_get_rate(pc->clk); |
| 112 | |
| 113 | /* |
| 114 | * Since period and duty cycle registers have a width of 32 |
| 115 | * bits, every possible input period can be obtained using the |
| 116 | * default prescaler value for all practical clock rate values. |
| 117 | */ |
David Wu | bc834d7 | 2017-08-08 23:38:32 +0800 | [diff] [blame] | 118 | div = clk_rate * state->period; |
Boris Brezillon | 12f9ce4 | 2016-06-14 11:13:11 +0200 | [diff] [blame] | 119 | period = DIV_ROUND_CLOSEST_ULL(div, |
| 120 | pc->data->prescaler * NSEC_PER_SEC); |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 121 | |
David Wu | bc834d7 | 2017-08-08 23:38:32 +0800 | [diff] [blame] | 122 | div = clk_rate * state->duty_cycle; |
Boris Brezillon | 12f9ce4 | 2016-06-14 11:13:11 +0200 | [diff] [blame] | 123 | duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC); |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 124 | |
David Wu | 3f9a363 | 2017-08-08 23:42:47 +0800 | [diff] [blame] | 125 | /* |
| 126 | * Lock the period and duty of previous configuration, then |
| 127 | * change the duty and period, that would not be effective. |
| 128 | */ |
| 129 | ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl); |
| 130 | if (pc->data->supports_lock) { |
| 131 | ctrl |= PWM_LOCK_EN; |
| 132 | writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl); |
| 133 | } |
| 134 | |
Caesar Wang | f630629 | 2014-08-08 15:28:49 +0800 | [diff] [blame] | 135 | writel(period, pc->base + pc->data->regs.period); |
| 136 | writel(duty, pc->base + pc->data->regs.duty); |
David Wu | bc834d7 | 2017-08-08 23:38:32 +0800 | [diff] [blame] | 137 | |
David Wu | bc834d7 | 2017-08-08 23:38:32 +0800 | [diff] [blame] | 138 | if (pc->data->supports_polarity) { |
| 139 | ctrl &= ~PWM_POLARITY_MASK; |
| 140 | if (state->polarity == PWM_POLARITY_INVERSED) |
| 141 | ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE; |
| 142 | else |
| 143 | ctrl |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE; |
| 144 | } |
David Wu | 3f9a363 | 2017-08-08 23:42:47 +0800 | [diff] [blame] | 145 | |
| 146 | /* |
| 147 | * Unlock and set polarity at the same time, |
| 148 | * the configuration of duty, period and polarity |
| 149 | * would be effective together at next period. |
| 150 | */ |
| 151 | if (pc->data->supports_lock) |
| 152 | ctrl &= ~PWM_LOCK_EN; |
| 153 | |
David Wu | bc834d7 | 2017-08-08 23:38:32 +0800 | [diff] [blame] | 154 | writel(ctrl, pc->base + pc->data->regs.ctrl); |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 155 | } |
| 156 | |
David Wu | a900152 | 2017-03-01 19:10:55 +0800 | [diff] [blame] | 157 | static int rockchip_pwm_enable(struct pwm_chip *chip, |
David Wu | bc834d7 | 2017-08-08 23:38:32 +0800 | [diff] [blame] | 158 | struct pwm_device *pwm, |
David Wu | 831b279 | 2017-08-08 23:41:28 +0800 | [diff] [blame] | 159 | bool enable) |
David Wu | a900152 | 2017-03-01 19:10:55 +0800 | [diff] [blame] | 160 | { |
| 161 | struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); |
David Wu | 831b279 | 2017-08-08 23:41:28 +0800 | [diff] [blame] | 162 | u32 enable_conf = pc->data->enable_conf; |
David Wu | a900152 | 2017-03-01 19:10:55 +0800 | [diff] [blame] | 163 | int ret; |
David Wu | ed05469 | 2017-08-08 23:38:31 +0800 | [diff] [blame] | 164 | u32 val; |
David Wu | a900152 | 2017-03-01 19:10:55 +0800 | [diff] [blame] | 165 | |
| 166 | if (enable) { |
| 167 | ret = clk_enable(pc->clk); |
| 168 | if (ret) |
| 169 | return ret; |
| 170 | } |
| 171 | |
David Wu | ed05469 | 2017-08-08 23:38:31 +0800 | [diff] [blame] | 172 | val = readl_relaxed(pc->base + pc->data->regs.ctrl); |
| 173 | |
| 174 | if (enable) |
| 175 | val |= enable_conf; |
| 176 | else |
| 177 | val &= ~enable_conf; |
| 178 | |
| 179 | writel_relaxed(val, pc->base + pc->data->regs.ctrl); |
David Wu | a900152 | 2017-03-01 19:10:55 +0800 | [diff] [blame] | 180 | |
| 181 | if (!enable) |
| 182 | clk_disable(pc->clk); |
| 183 | |
| 184 | return 0; |
| 185 | } |
| 186 | |
David Wu | ed05469 | 2017-08-08 23:38:31 +0800 | [diff] [blame] | 187 | static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
Uwe Kleine-König | 71523d1 | 2019-08-24 17:37:07 +0200 | [diff] [blame] | 188 | const struct pwm_state *state) |
David Wu | ed05469 | 2017-08-08 23:38:31 +0800 | [diff] [blame] | 189 | { |
| 190 | struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); |
David Wu | 831b279 | 2017-08-08 23:41:28 +0800 | [diff] [blame] | 191 | struct pwm_state curstate; |
| 192 | bool enabled; |
| 193 | int ret = 0; |
David Wu | ed05469 | 2017-08-08 23:38:31 +0800 | [diff] [blame] | 194 | |
| 195 | ret = clk_enable(pc->pclk); |
| 196 | if (ret) |
| 197 | return ret; |
| 198 | |
Simon South | 11be938 | 2021-01-19 11:12:09 -0500 | [diff] [blame] | 199 | ret = clk_enable(pc->clk); |
| 200 | if (ret) |
| 201 | return ret; |
| 202 | |
David Wu | 831b279 | 2017-08-08 23:41:28 +0800 | [diff] [blame] | 203 | pwm_get_state(pwm, &curstate); |
| 204 | enabled = curstate.enabled; |
| 205 | |
David Wu | 3f9a363 | 2017-08-08 23:42:47 +0800 | [diff] [blame] | 206 | if (state->polarity != curstate.polarity && enabled && |
| 207 | !pc->data->supports_lock) { |
David Wu | 831b279 | 2017-08-08 23:41:28 +0800 | [diff] [blame] | 208 | ret = rockchip_pwm_enable(chip, pwm, false); |
| 209 | if (ret) |
| 210 | goto out; |
| 211 | enabled = false; |
| 212 | } |
| 213 | |
| 214 | rockchip_pwm_config(chip, pwm, state); |
| 215 | if (state->enabled != enabled) { |
| 216 | ret = rockchip_pwm_enable(chip, pwm, state->enabled); |
| 217 | if (ret) |
| 218 | goto out; |
| 219 | } |
David Wu | ed05469 | 2017-08-08 23:38:31 +0800 | [diff] [blame] | 220 | |
Boris Brezillon | 2bf1c98 | 2016-06-14 11:13:14 +0200 | [diff] [blame] | 221 | out: |
Simon South | 11be938 | 2021-01-19 11:12:09 -0500 | [diff] [blame] | 222 | clk_disable(pc->clk); |
David Wu | 27922ff5 | 2017-08-08 23:38:29 +0800 | [diff] [blame] | 223 | clk_disable(pc->pclk); |
Boris Brezillon | 2bf1c98 | 2016-06-14 11:13:14 +0200 | [diff] [blame] | 224 | |
| 225 | return ret; |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 226 | } |
| 227 | |
David Wu | 831b279 | 2017-08-08 23:41:28 +0800 | [diff] [blame] | 228 | static const struct pwm_ops rockchip_pwm_ops = { |
Boris Brezillon | 1ebb74c | 2016-06-14 11:13:12 +0200 | [diff] [blame] | 229 | .get_state = rockchip_pwm_get_state, |
Boris Brezillon | 2bf1c98 | 2016-06-14 11:13:14 +0200 | [diff] [blame] | 230 | .apply = rockchip_pwm_apply, |
Doug Anderson | 7264354 | 2014-08-25 15:59:25 -0700 | [diff] [blame] | 231 | }; |
| 232 | |
Caesar Wang | f630629 | 2014-08-08 15:28:49 +0800 | [diff] [blame] | 233 | static const struct rockchip_pwm_data pwm_data_v1 = { |
| 234 | .regs = { |
| 235 | .duty = 0x04, |
| 236 | .period = 0x08, |
| 237 | .cntr = 0x00, |
| 238 | .ctrl = 0x0c, |
| 239 | }, |
| 240 | .prescaler = 2, |
David Wu | 831b279 | 2017-08-08 23:41:28 +0800 | [diff] [blame] | 241 | .supports_polarity = false, |
David Wu | 3f9a363 | 2017-08-08 23:42:47 +0800 | [diff] [blame] | 242 | .supports_lock = false, |
David Wu | 831b279 | 2017-08-08 23:41:28 +0800 | [diff] [blame] | 243 | .enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN, |
Caesar Wang | f630629 | 2014-08-08 15:28:49 +0800 | [diff] [blame] | 244 | }; |
| 245 | |
| 246 | static const struct rockchip_pwm_data pwm_data_v2 = { |
| 247 | .regs = { |
| 248 | .duty = 0x08, |
| 249 | .period = 0x04, |
| 250 | .cntr = 0x00, |
| 251 | .ctrl = 0x0c, |
| 252 | }, |
| 253 | .prescaler = 1, |
Boris Brezillon | 2bf1c98 | 2016-06-14 11:13:14 +0200 | [diff] [blame] | 254 | .supports_polarity = true, |
David Wu | 3f9a363 | 2017-08-08 23:42:47 +0800 | [diff] [blame] | 255 | .supports_lock = false, |
David Wu | 831b279 | 2017-08-08 23:41:28 +0800 | [diff] [blame] | 256 | .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | |
| 257 | PWM_CONTINUOUS, |
Caesar Wang | f630629 | 2014-08-08 15:28:49 +0800 | [diff] [blame] | 258 | }; |
| 259 | |
| 260 | static const struct rockchip_pwm_data pwm_data_vop = { |
| 261 | .regs = { |
| 262 | .duty = 0x08, |
| 263 | .period = 0x04, |
| 264 | .cntr = 0x0c, |
| 265 | .ctrl = 0x00, |
| 266 | }, |
| 267 | .prescaler = 1, |
Boris Brezillon | 2bf1c98 | 2016-06-14 11:13:14 +0200 | [diff] [blame] | 268 | .supports_polarity = true, |
David Wu | 3f9a363 | 2017-08-08 23:42:47 +0800 | [diff] [blame] | 269 | .supports_lock = false, |
| 270 | .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | |
| 271 | PWM_CONTINUOUS, |
| 272 | }; |
| 273 | |
| 274 | static const struct rockchip_pwm_data pwm_data_v3 = { |
| 275 | .regs = { |
| 276 | .duty = 0x08, |
| 277 | .period = 0x04, |
| 278 | .cntr = 0x00, |
| 279 | .ctrl = 0x0c, |
| 280 | }, |
| 281 | .prescaler = 1, |
| 282 | .supports_polarity = true, |
| 283 | .supports_lock = true, |
David Wu | 831b279 | 2017-08-08 23:41:28 +0800 | [diff] [blame] | 284 | .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | |
| 285 | PWM_CONTINUOUS, |
Caesar Wang | f630629 | 2014-08-08 15:28:49 +0800 | [diff] [blame] | 286 | }; |
| 287 | |
| 288 | static const struct of_device_id rockchip_pwm_dt_ids[] = { |
| 289 | { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1}, |
| 290 | { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2}, |
| 291 | { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop}, |
David Wu | 3f9a363 | 2017-08-08 23:42:47 +0800 | [diff] [blame] | 292 | { .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3}, |
Caesar Wang | f630629 | 2014-08-08 15:28:49 +0800 | [diff] [blame] | 293 | { /* sentinel */ } |
| 294 | }; |
| 295 | MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids); |
| 296 | |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 297 | static int rockchip_pwm_probe(struct platform_device *pdev) |
| 298 | { |
Caesar Wang | f630629 | 2014-08-08 15:28:49 +0800 | [diff] [blame] | 299 | const struct of_device_id *id; |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 300 | struct rockchip_pwm_chip *pc; |
Simon South | 457f74a | 2020-09-19 15:33:06 -0400 | [diff] [blame] | 301 | u32 enable_conf, ctrl; |
Simon South | d21ba5d | 2021-01-19 11:12:08 -0500 | [diff] [blame] | 302 | bool enabled; |
David Wu | 27922ff5 | 2017-08-08 23:38:29 +0800 | [diff] [blame] | 303 | int ret, count; |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 304 | |
Caesar Wang | f630629 | 2014-08-08 15:28:49 +0800 | [diff] [blame] | 305 | id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev); |
| 306 | if (!id) |
| 307 | return -EINVAL; |
| 308 | |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 309 | pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); |
| 310 | if (!pc) |
| 311 | return -ENOMEM; |
| 312 | |
Yangtao Li | 5119ee9 | 2019-12-29 08:05:53 +0000 | [diff] [blame] | 313 | pc->base = devm_platform_ioremap_resource(pdev, 0); |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 314 | if (IS_ERR(pc->base)) |
| 315 | return PTR_ERR(pc->base); |
| 316 | |
David Wu | 27922ff5 | 2017-08-08 23:38:29 +0800 | [diff] [blame] | 317 | pc->clk = devm_clk_get(&pdev->dev, "pwm"); |
| 318 | if (IS_ERR(pc->clk)) { |
| 319 | pc->clk = devm_clk_get(&pdev->dev, NULL); |
Krzysztof Kozlowski | 836719f | 2020-08-26 16:47:44 +0200 | [diff] [blame] | 320 | if (IS_ERR(pc->clk)) |
| 321 | return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk), |
Simon South | c9f809d | 2021-01-19 11:12:07 -0500 | [diff] [blame] | 322 | "Can't get PWM clk\n"); |
David Wu | 27922ff5 | 2017-08-08 23:38:29 +0800 | [diff] [blame] | 323 | } |
| 324 | |
| 325 | count = of_count_phandle_with_args(pdev->dev.of_node, |
| 326 | "clocks", "#clock-cells"); |
| 327 | if (count == 2) |
| 328 | pc->pclk = devm_clk_get(&pdev->dev, "pclk"); |
| 329 | else |
| 330 | pc->pclk = pc->clk; |
| 331 | |
zhaoxiao | 4b8857c | 2022-08-22 16:18:48 +0800 | [diff] [blame] | 332 | if (IS_ERR(pc->pclk)) |
| 333 | return dev_err_probe(&pdev->dev, PTR_ERR(pc->pclk), "Can't get APB clk\n"); |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 334 | |
Boris Brezillon | 48cf973 | 2016-06-14 11:13:13 +0200 | [diff] [blame] | 335 | ret = clk_prepare_enable(pc->clk); |
zhaoxiao | 4b8857c | 2022-08-22 16:18:48 +0800 | [diff] [blame] | 336 | if (ret) |
| 337 | return dev_err_probe(&pdev->dev, ret, "Can't prepare enable PWM clk\n"); |
David Wu | 27922ff5 | 2017-08-08 23:38:29 +0800 | [diff] [blame] | 338 | |
Simon South | d9b657a | 2021-01-19 11:12:05 -0500 | [diff] [blame] | 339 | ret = clk_prepare_enable(pc->pclk); |
David Wu | 27922ff5 | 2017-08-08 23:38:29 +0800 | [diff] [blame] | 340 | if (ret) { |
zhaoxiao | 4b8857c | 2022-08-22 16:18:48 +0800 | [diff] [blame] | 341 | dev_err_probe(&pdev->dev, ret, "Can't prepare enable APB clk\n"); |
David Wu | 27922ff5 | 2017-08-08 23:38:29 +0800 | [diff] [blame] | 342 | goto err_clk; |
| 343 | } |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 344 | |
| 345 | platform_set_drvdata(pdev, pc); |
| 346 | |
Caesar Wang | f630629 | 2014-08-08 15:28:49 +0800 | [diff] [blame] | 347 | pc->data = id->data; |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 348 | pc->chip.dev = &pdev->dev; |
David Wu | 831b279 | 2017-08-08 23:41:28 +0800 | [diff] [blame] | 349 | pc->chip.ops = &rockchip_pwm_ops; |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 350 | pc->chip.npwm = 1; |
| 351 | |
Simon South | d21ba5d | 2021-01-19 11:12:08 -0500 | [diff] [blame] | 352 | enable_conf = pc->data->enable_conf; |
| 353 | ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl); |
| 354 | enabled = (ctrl & enable_conf) == enable_conf; |
| 355 | |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 356 | ret = pwmchip_add(&pc->chip); |
| 357 | if (ret < 0) { |
zhaoxiao | 4b8857c | 2022-08-22 16:18:48 +0800 | [diff] [blame] | 358 | dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n"); |
David Wu | 27922ff5 | 2017-08-08 23:38:29 +0800 | [diff] [blame] | 359 | goto err_pclk; |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 360 | } |
| 361 | |
Boris Brezillon | 48cf973 | 2016-06-14 11:13:13 +0200 | [diff] [blame] | 362 | /* Keep the PWM clk enabled if the PWM appears to be up and running. */ |
Simon South | d21ba5d | 2021-01-19 11:12:08 -0500 | [diff] [blame] | 363 | if (!enabled) |
Boris Brezillon | 48cf973 | 2016-06-14 11:13:13 +0200 | [diff] [blame] | 364 | clk_disable(pc->clk); |
| 365 | |
Simon South | d9b657a | 2021-01-19 11:12:05 -0500 | [diff] [blame] | 366 | clk_disable(pc->pclk); |
| 367 | |
David Wu | 27922ff5 | 2017-08-08 23:38:29 +0800 | [diff] [blame] | 368 | return 0; |
| 369 | |
| 370 | err_pclk: |
Simon South | d9b657a | 2021-01-19 11:12:05 -0500 | [diff] [blame] | 371 | clk_disable_unprepare(pc->pclk); |
David Wu | 27922ff5 | 2017-08-08 23:38:29 +0800 | [diff] [blame] | 372 | err_clk: |
| 373 | clk_disable_unprepare(pc->clk); |
| 374 | |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 375 | return ret; |
| 376 | } |
| 377 | |
Uwe Kleine-König | 18a95d3 | 2023-03-03 19:54:33 +0100 | [diff] [blame] | 378 | static void rockchip_pwm_remove(struct platform_device *pdev) |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 379 | { |
| 380 | struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev); |
| 381 | |
Uwe Kleine-König | 84ea61f | 2021-07-07 18:27:55 +0200 | [diff] [blame] | 382 | pwmchip_remove(&pc->chip); |
| 383 | |
David Wu | 27922ff5 | 2017-08-08 23:38:29 +0800 | [diff] [blame] | 384 | clk_unprepare(pc->pclk); |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 385 | clk_unprepare(pc->clk); |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 386 | } |
| 387 | |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 388 | static struct platform_driver rockchip_pwm_driver = { |
| 389 | .driver = { |
| 390 | .name = "rockchip-pwm", |
| 391 | .of_match_table = rockchip_pwm_dt_ids, |
| 392 | }, |
| 393 | .probe = rockchip_pwm_probe, |
Uwe Kleine-König | 18a95d3 | 2023-03-03 19:54:33 +0100 | [diff] [blame] | 394 | .remove_new = rockchip_pwm_remove, |
Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 395 | }; |
| 396 | module_platform_driver(rockchip_pwm_driver); |
| 397 | |
| 398 | MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>"); |
| 399 | MODULE_DESCRIPTION("Rockchip SoC PWM driver"); |
| 400 | MODULE_LICENSE("GPL v2"); |