blob: cce4381e188af0bfb7549db11de1d0819c893be6 [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Beniamino Galvani101353c2014-06-21 16:22:06 +02002/*
3 * PWM driver for Rockchip SoCs
4 *
5 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
Caesar Wangf6306292014-08-08 15:28:49 +08006 * Copyright (C) 2014 ROCKCHIP, Inc.
Beniamino Galvani101353c2014-06-21 16:22:06 +02007 */
8
9#include <linux/clk.h>
10#include <linux/io.h>
11#include <linux/module.h>
12#include <linux/of.h>
Caesar Wangf6306292014-08-08 15:28:49 +080013#include <linux/of_device.h>
Beniamino Galvani101353c2014-06-21 16:22:06 +020014#include <linux/platform_device.h>
15#include <linux/pwm.h>
16#include <linux/time.h>
17
Beniamino Galvani101353c2014-06-21 16:22:06 +020018#define PWM_CTRL_TIMER_EN (1 << 0)
19#define PWM_CTRL_OUTPUT_EN (1 << 3)
20
Caesar Wangf6306292014-08-08 15:28:49 +080021#define PWM_ENABLE (1 << 0)
22#define PWM_CONTINUOUS (1 << 1)
23#define PWM_DUTY_POSITIVE (1 << 3)
Doug Anderson72643542014-08-25 15:59:25 -070024#define PWM_DUTY_NEGATIVE (0 << 3)
Caesar Wangf6306292014-08-08 15:28:49 +080025#define PWM_INACTIVE_NEGATIVE (0 << 4)
Doug Anderson72643542014-08-25 15:59:25 -070026#define PWM_INACTIVE_POSITIVE (1 << 4)
David Wubc834d72017-08-08 23:38:32 +080027#define PWM_POLARITY_MASK (PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE)
Caesar Wangf6306292014-08-08 15:28:49 +080028#define PWM_OUTPUT_LEFT (0 << 5)
David Wu3f9a3632017-08-08 23:42:47 +080029#define PWM_LOCK_EN (1 << 6)
Caesar Wangf6306292014-08-08 15:28:49 +080030#define PWM_LP_DISABLE (0 << 8)
Beniamino Galvani101353c2014-06-21 16:22:06 +020031
32struct rockchip_pwm_chip {
33 struct pwm_chip chip;
34 struct clk *clk;
David Wu27922ff52017-08-08 23:38:29 +080035 struct clk *pclk;
Caesar Wangf6306292014-08-08 15:28:49 +080036 const struct rockchip_pwm_data *data;
Beniamino Galvani101353c2014-06-21 16:22:06 +020037 void __iomem *base;
38};
39
Caesar Wangf6306292014-08-08 15:28:49 +080040struct rockchip_pwm_regs {
41 unsigned long duty;
42 unsigned long period;
43 unsigned long cntr;
44 unsigned long ctrl;
45};
46
47struct rockchip_pwm_data {
48 struct rockchip_pwm_regs regs;
49 unsigned int prescaler;
Boris Brezillon2bf1c982016-06-14 11:13:14 +020050 bool supports_polarity;
David Wu3f9a3632017-08-08 23:42:47 +080051 bool supports_lock;
David Wu831b2792017-08-08 23:41:28 +080052 u32 enable_conf;
Caesar Wangf6306292014-08-08 15:28:49 +080053};
54
Uwe Kleine-König454a8f52023-07-14 22:56:20 +020055static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *chip)
Beniamino Galvani101353c2014-06-21 16:22:06 +020056{
Uwe Kleine-König454a8f52023-07-14 22:56:20 +020057 return container_of(chip, struct rockchip_pwm_chip, chip);
Beniamino Galvani101353c2014-06-21 16:22:06 +020058}
59
Uwe Kleine-König6c452cf2022-12-02 19:35:26 +010060static int rockchip_pwm_get_state(struct pwm_chip *chip,
61 struct pwm_device *pwm,
62 struct pwm_state *state)
Boris Brezillon1ebb74c2016-06-14 11:13:12 +020063{
64 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
David Wu831b2792017-08-08 23:41:28 +080065 u32 enable_conf = pc->data->enable_conf;
Boris Brezillon1ebb74c2016-06-14 11:13:12 +020066 unsigned long clk_rate;
67 u64 tmp;
David Wu831b2792017-08-08 23:41:28 +080068 u32 val;
Boris Brezillon1ebb74c2016-06-14 11:13:12 +020069 int ret;
70
David Wu27922ff52017-08-08 23:38:29 +080071 ret = clk_enable(pc->pclk);
Boris Brezillon1ebb74c2016-06-14 11:13:12 +020072 if (ret)
Uwe Kleine-König790a8ba2022-12-02 19:35:34 +010073 return ret;
Boris Brezillon1ebb74c2016-06-14 11:13:12 +020074
Simon South11be9382021-01-19 11:12:09 -050075 ret = clk_enable(pc->clk);
76 if (ret)
Uwe Kleine-König790a8ba2022-12-02 19:35:34 +010077 return ret;
Simon South11be9382021-01-19 11:12:09 -050078
Boris Brezillon1ebb74c2016-06-14 11:13:12 +020079 clk_rate = clk_get_rate(pc->clk);
80
81 tmp = readl_relaxed(pc->base + pc->data->regs.period);
82 tmp *= pc->data->prescaler * NSEC_PER_SEC;
83 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
84
85 tmp = readl_relaxed(pc->base + pc->data->regs.duty);
86 tmp *= pc->data->prescaler * NSEC_PER_SEC;
David Wu831b2792017-08-08 23:41:28 +080087 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
Boris Brezillon1ebb74c2016-06-14 11:13:12 +020088
David Wu831b2792017-08-08 23:41:28 +080089 val = readl_relaxed(pc->base + pc->data->regs.ctrl);
Rasmus Villemoescad0f292019-09-19 11:17:27 +020090 state->enabled = (val & enable_conf) == enable_conf;
David Wu831b2792017-08-08 23:41:28 +080091
Uwe Kleine-Königba73deb2019-09-02 16:39:41 +020092 if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE))
93 state->polarity = PWM_POLARITY_INVERSED;
94 else
95 state->polarity = PWM_POLARITY_NORMAL;
Boris Brezillon1ebb74c2016-06-14 11:13:12 +020096
Simon South11be9382021-01-19 11:12:09 -050097 clk_disable(pc->clk);
David Wu27922ff52017-08-08 23:38:29 +080098 clk_disable(pc->pclk);
Uwe Kleine-König6c452cf2022-12-02 19:35:26 +010099
100 return 0;
Boris Brezillon1ebb74c2016-06-14 11:13:12 +0200101}
102
David Wuf90df9c2017-08-08 23:38:30 +0800103static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
Uwe Kleine-König71523d12019-08-24 17:37:07 +0200104 const struct pwm_state *state)
Beniamino Galvani101353c2014-06-21 16:22:06 +0200105{
106 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
107 unsigned long period, duty;
108 u64 clk_rate, div;
David Wubc834d72017-08-08 23:38:32 +0800109 u32 ctrl;
Beniamino Galvani101353c2014-06-21 16:22:06 +0200110
111 clk_rate = clk_get_rate(pc->clk);
112
113 /*
114 * Since period and duty cycle registers have a width of 32
115 * bits, every possible input period can be obtained using the
116 * default prescaler value for all practical clock rate values.
117 */
David Wubc834d72017-08-08 23:38:32 +0800118 div = clk_rate * state->period;
Boris Brezillon12f9ce42016-06-14 11:13:11 +0200119 period = DIV_ROUND_CLOSEST_ULL(div,
120 pc->data->prescaler * NSEC_PER_SEC);
Beniamino Galvani101353c2014-06-21 16:22:06 +0200121
David Wubc834d72017-08-08 23:38:32 +0800122 div = clk_rate * state->duty_cycle;
Boris Brezillon12f9ce42016-06-14 11:13:11 +0200123 duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
Beniamino Galvani101353c2014-06-21 16:22:06 +0200124
David Wu3f9a3632017-08-08 23:42:47 +0800125 /*
126 * Lock the period and duty of previous configuration, then
127 * change the duty and period, that would not be effective.
128 */
129 ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
130 if (pc->data->supports_lock) {
131 ctrl |= PWM_LOCK_EN;
132 writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);
133 }
134
Caesar Wangf6306292014-08-08 15:28:49 +0800135 writel(period, pc->base + pc->data->regs.period);
136 writel(duty, pc->base + pc->data->regs.duty);
David Wubc834d72017-08-08 23:38:32 +0800137
David Wubc834d72017-08-08 23:38:32 +0800138 if (pc->data->supports_polarity) {
139 ctrl &= ~PWM_POLARITY_MASK;
140 if (state->polarity == PWM_POLARITY_INVERSED)
141 ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
142 else
143 ctrl |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
144 }
David Wu3f9a3632017-08-08 23:42:47 +0800145
146 /*
147 * Unlock and set polarity at the same time,
148 * the configuration of duty, period and polarity
149 * would be effective together at next period.
150 */
151 if (pc->data->supports_lock)
152 ctrl &= ~PWM_LOCK_EN;
153
David Wubc834d72017-08-08 23:38:32 +0800154 writel(ctrl, pc->base + pc->data->regs.ctrl);
Beniamino Galvani101353c2014-06-21 16:22:06 +0200155}
156
David Wua9001522017-03-01 19:10:55 +0800157static int rockchip_pwm_enable(struct pwm_chip *chip,
David Wubc834d72017-08-08 23:38:32 +0800158 struct pwm_device *pwm,
David Wu831b2792017-08-08 23:41:28 +0800159 bool enable)
David Wua9001522017-03-01 19:10:55 +0800160{
161 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
David Wu831b2792017-08-08 23:41:28 +0800162 u32 enable_conf = pc->data->enable_conf;
David Wua9001522017-03-01 19:10:55 +0800163 int ret;
David Wued054692017-08-08 23:38:31 +0800164 u32 val;
David Wua9001522017-03-01 19:10:55 +0800165
166 if (enable) {
167 ret = clk_enable(pc->clk);
168 if (ret)
169 return ret;
170 }
171
David Wued054692017-08-08 23:38:31 +0800172 val = readl_relaxed(pc->base + pc->data->regs.ctrl);
173
174 if (enable)
175 val |= enable_conf;
176 else
177 val &= ~enable_conf;
178
179 writel_relaxed(val, pc->base + pc->data->regs.ctrl);
David Wua9001522017-03-01 19:10:55 +0800180
181 if (!enable)
182 clk_disable(pc->clk);
183
184 return 0;
185}
186
David Wued054692017-08-08 23:38:31 +0800187static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
Uwe Kleine-König71523d12019-08-24 17:37:07 +0200188 const struct pwm_state *state)
David Wued054692017-08-08 23:38:31 +0800189{
190 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
David Wu831b2792017-08-08 23:41:28 +0800191 struct pwm_state curstate;
192 bool enabled;
193 int ret = 0;
David Wued054692017-08-08 23:38:31 +0800194
195 ret = clk_enable(pc->pclk);
196 if (ret)
197 return ret;
198
Simon South11be9382021-01-19 11:12:09 -0500199 ret = clk_enable(pc->clk);
200 if (ret)
201 return ret;
202
David Wu831b2792017-08-08 23:41:28 +0800203 pwm_get_state(pwm, &curstate);
204 enabled = curstate.enabled;
205
David Wu3f9a3632017-08-08 23:42:47 +0800206 if (state->polarity != curstate.polarity && enabled &&
207 !pc->data->supports_lock) {
David Wu831b2792017-08-08 23:41:28 +0800208 ret = rockchip_pwm_enable(chip, pwm, false);
209 if (ret)
210 goto out;
211 enabled = false;
212 }
213
214 rockchip_pwm_config(chip, pwm, state);
215 if (state->enabled != enabled) {
216 ret = rockchip_pwm_enable(chip, pwm, state->enabled);
217 if (ret)
218 goto out;
219 }
David Wued054692017-08-08 23:38:31 +0800220
Boris Brezillon2bf1c982016-06-14 11:13:14 +0200221out:
Simon South11be9382021-01-19 11:12:09 -0500222 clk_disable(pc->clk);
David Wu27922ff52017-08-08 23:38:29 +0800223 clk_disable(pc->pclk);
Boris Brezillon2bf1c982016-06-14 11:13:14 +0200224
225 return ret;
Beniamino Galvani101353c2014-06-21 16:22:06 +0200226}
227
David Wu831b2792017-08-08 23:41:28 +0800228static const struct pwm_ops rockchip_pwm_ops = {
Boris Brezillon1ebb74c2016-06-14 11:13:12 +0200229 .get_state = rockchip_pwm_get_state,
Boris Brezillon2bf1c982016-06-14 11:13:14 +0200230 .apply = rockchip_pwm_apply,
Doug Anderson72643542014-08-25 15:59:25 -0700231};
232
Caesar Wangf6306292014-08-08 15:28:49 +0800233static const struct rockchip_pwm_data pwm_data_v1 = {
234 .regs = {
235 .duty = 0x04,
236 .period = 0x08,
237 .cntr = 0x00,
238 .ctrl = 0x0c,
239 },
240 .prescaler = 2,
David Wu831b2792017-08-08 23:41:28 +0800241 .supports_polarity = false,
David Wu3f9a3632017-08-08 23:42:47 +0800242 .supports_lock = false,
David Wu831b2792017-08-08 23:41:28 +0800243 .enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
Caesar Wangf6306292014-08-08 15:28:49 +0800244};
245
246static const struct rockchip_pwm_data pwm_data_v2 = {
247 .regs = {
248 .duty = 0x08,
249 .period = 0x04,
250 .cntr = 0x00,
251 .ctrl = 0x0c,
252 },
253 .prescaler = 1,
Boris Brezillon2bf1c982016-06-14 11:13:14 +0200254 .supports_polarity = true,
David Wu3f9a3632017-08-08 23:42:47 +0800255 .supports_lock = false,
David Wu831b2792017-08-08 23:41:28 +0800256 .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
257 PWM_CONTINUOUS,
Caesar Wangf6306292014-08-08 15:28:49 +0800258};
259
260static const struct rockchip_pwm_data pwm_data_vop = {
261 .regs = {
262 .duty = 0x08,
263 .period = 0x04,
264 .cntr = 0x0c,
265 .ctrl = 0x00,
266 },
267 .prescaler = 1,
Boris Brezillon2bf1c982016-06-14 11:13:14 +0200268 .supports_polarity = true,
David Wu3f9a3632017-08-08 23:42:47 +0800269 .supports_lock = false,
270 .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
271 PWM_CONTINUOUS,
272};
273
274static const struct rockchip_pwm_data pwm_data_v3 = {
275 .regs = {
276 .duty = 0x08,
277 .period = 0x04,
278 .cntr = 0x00,
279 .ctrl = 0x0c,
280 },
281 .prescaler = 1,
282 .supports_polarity = true,
283 .supports_lock = true,
David Wu831b2792017-08-08 23:41:28 +0800284 .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
285 PWM_CONTINUOUS,
Caesar Wangf6306292014-08-08 15:28:49 +0800286};
287
288static const struct of_device_id rockchip_pwm_dt_ids[] = {
289 { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
290 { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
291 { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
David Wu3f9a3632017-08-08 23:42:47 +0800292 { .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3},
Caesar Wangf6306292014-08-08 15:28:49 +0800293 { /* sentinel */ }
294};
295MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
296
Beniamino Galvani101353c2014-06-21 16:22:06 +0200297static int rockchip_pwm_probe(struct platform_device *pdev)
298{
Caesar Wangf6306292014-08-08 15:28:49 +0800299 const struct of_device_id *id;
Beniamino Galvani101353c2014-06-21 16:22:06 +0200300 struct rockchip_pwm_chip *pc;
Simon South457f74a2020-09-19 15:33:06 -0400301 u32 enable_conf, ctrl;
Simon Southd21ba5d2021-01-19 11:12:08 -0500302 bool enabled;
David Wu27922ff52017-08-08 23:38:29 +0800303 int ret, count;
Beniamino Galvani101353c2014-06-21 16:22:06 +0200304
Caesar Wangf6306292014-08-08 15:28:49 +0800305 id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
306 if (!id)
307 return -EINVAL;
308
Beniamino Galvani101353c2014-06-21 16:22:06 +0200309 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
310 if (!pc)
311 return -ENOMEM;
312
Yangtao Li5119ee92019-12-29 08:05:53 +0000313 pc->base = devm_platform_ioremap_resource(pdev, 0);
Beniamino Galvani101353c2014-06-21 16:22:06 +0200314 if (IS_ERR(pc->base))
315 return PTR_ERR(pc->base);
316
David Wu27922ff52017-08-08 23:38:29 +0800317 pc->clk = devm_clk_get(&pdev->dev, "pwm");
318 if (IS_ERR(pc->clk)) {
319 pc->clk = devm_clk_get(&pdev->dev, NULL);
Krzysztof Kozlowski836719f2020-08-26 16:47:44 +0200320 if (IS_ERR(pc->clk))
321 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
Simon Southc9f809d2021-01-19 11:12:07 -0500322 "Can't get PWM clk\n");
David Wu27922ff52017-08-08 23:38:29 +0800323 }
324
325 count = of_count_phandle_with_args(pdev->dev.of_node,
326 "clocks", "#clock-cells");
327 if (count == 2)
328 pc->pclk = devm_clk_get(&pdev->dev, "pclk");
329 else
330 pc->pclk = pc->clk;
331
zhaoxiao4b8857c2022-08-22 16:18:48 +0800332 if (IS_ERR(pc->pclk))
333 return dev_err_probe(&pdev->dev, PTR_ERR(pc->pclk), "Can't get APB clk\n");
Beniamino Galvani101353c2014-06-21 16:22:06 +0200334
Boris Brezillon48cf9732016-06-14 11:13:13 +0200335 ret = clk_prepare_enable(pc->clk);
zhaoxiao4b8857c2022-08-22 16:18:48 +0800336 if (ret)
337 return dev_err_probe(&pdev->dev, ret, "Can't prepare enable PWM clk\n");
David Wu27922ff52017-08-08 23:38:29 +0800338
Simon Southd9b657a2021-01-19 11:12:05 -0500339 ret = clk_prepare_enable(pc->pclk);
David Wu27922ff52017-08-08 23:38:29 +0800340 if (ret) {
zhaoxiao4b8857c2022-08-22 16:18:48 +0800341 dev_err_probe(&pdev->dev, ret, "Can't prepare enable APB clk\n");
David Wu27922ff52017-08-08 23:38:29 +0800342 goto err_clk;
343 }
Beniamino Galvani101353c2014-06-21 16:22:06 +0200344
345 platform_set_drvdata(pdev, pc);
346
Caesar Wangf6306292014-08-08 15:28:49 +0800347 pc->data = id->data;
Beniamino Galvani101353c2014-06-21 16:22:06 +0200348 pc->chip.dev = &pdev->dev;
David Wu831b2792017-08-08 23:41:28 +0800349 pc->chip.ops = &rockchip_pwm_ops;
Beniamino Galvani101353c2014-06-21 16:22:06 +0200350 pc->chip.npwm = 1;
351
Simon Southd21ba5d2021-01-19 11:12:08 -0500352 enable_conf = pc->data->enable_conf;
353 ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
354 enabled = (ctrl & enable_conf) == enable_conf;
355
Beniamino Galvani101353c2014-06-21 16:22:06 +0200356 ret = pwmchip_add(&pc->chip);
357 if (ret < 0) {
zhaoxiao4b8857c2022-08-22 16:18:48 +0800358 dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n");
David Wu27922ff52017-08-08 23:38:29 +0800359 goto err_pclk;
Beniamino Galvani101353c2014-06-21 16:22:06 +0200360 }
361
Boris Brezillon48cf9732016-06-14 11:13:13 +0200362 /* Keep the PWM clk enabled if the PWM appears to be up and running. */
Simon Southd21ba5d2021-01-19 11:12:08 -0500363 if (!enabled)
Boris Brezillon48cf9732016-06-14 11:13:13 +0200364 clk_disable(pc->clk);
365
Simon Southd9b657a2021-01-19 11:12:05 -0500366 clk_disable(pc->pclk);
367
David Wu27922ff52017-08-08 23:38:29 +0800368 return 0;
369
370err_pclk:
Simon Southd9b657a2021-01-19 11:12:05 -0500371 clk_disable_unprepare(pc->pclk);
David Wu27922ff52017-08-08 23:38:29 +0800372err_clk:
373 clk_disable_unprepare(pc->clk);
374
Beniamino Galvani101353c2014-06-21 16:22:06 +0200375 return ret;
376}
377
Uwe Kleine-König18a95d32023-03-03 19:54:33 +0100378static void rockchip_pwm_remove(struct platform_device *pdev)
Beniamino Galvani101353c2014-06-21 16:22:06 +0200379{
380 struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
381
Uwe Kleine-König84ea61f2021-07-07 18:27:55 +0200382 pwmchip_remove(&pc->chip);
383
David Wu27922ff52017-08-08 23:38:29 +0800384 clk_unprepare(pc->pclk);
Beniamino Galvani101353c2014-06-21 16:22:06 +0200385 clk_unprepare(pc->clk);
Beniamino Galvani101353c2014-06-21 16:22:06 +0200386}
387
Beniamino Galvani101353c2014-06-21 16:22:06 +0200388static struct platform_driver rockchip_pwm_driver = {
389 .driver = {
390 .name = "rockchip-pwm",
391 .of_match_table = rockchip_pwm_dt_ids,
392 },
393 .probe = rockchip_pwm_probe,
Uwe Kleine-König18a95d32023-03-03 19:54:33 +0100394 .remove_new = rockchip_pwm_remove,
Beniamino Galvani101353c2014-06-21 16:22:06 +0200395};
396module_platform_driver(rockchip_pwm_driver);
397
398MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
399MODULE_DESCRIPTION("Rockchip SoC PWM driver");
400MODULE_LICENSE("GPL v2");