| Alexander Shiyan | 3c0f0f9 | 2013-12-11 19:52:35 +0400 | [diff] [blame] | 1 | * Cirrus Logic CLPS711X Universal Asynchronous Receiver/Transmitter (UART) |
| 2 | |
| 3 | Required properties: |
| Alexander Shiyan | d305345 | 2016-06-04 10:09:57 +0300 | [diff] [blame] | 4 | - compatible: Should be "cirrus,ep7209-uart". |
| Alexander Shiyan | 3c0f0f9 | 2013-12-11 19:52:35 +0400 | [diff] [blame] | 5 | - reg: Address and length of the register set for the device. |
| 6 | - interrupts: Should contain UART TX and RX interrupt. |
| 7 | - clocks: Should contain UART core clock number. |
| 8 | - syscon: Phandle to SYSCON node, which contain UART control bits. |
| 9 | |
| 10 | Optional properties: |
| Alexander Shiyan | 62b0a1b | 2014-09-06 07:20:15 +0400 | [diff] [blame] | 11 | - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD |
| 12 | line respectively. |
| Alexander Shiyan | 3c0f0f9 | 2013-12-11 19:52:35 +0400 | [diff] [blame] | 13 | |
| 14 | Note: Each UART port should have an alias correctly numbered |
| 15 | in "aliases" node. |
| 16 | |
| 17 | Example: |
| 18 | aliases { |
| 19 | serial0 = &uart1; |
| 20 | }; |
| 21 | |
| 22 | uart1: uart@80000480 { |
| Alexander Shiyan | d305345 | 2016-06-04 10:09:57 +0300 | [diff] [blame] | 23 | compatible = "cirrus,ep7312-uart","cirrus,ep7209-uart"; |
| Alexander Shiyan | 3c0f0f9 | 2013-12-11 19:52:35 +0400 | [diff] [blame] | 24 | reg = <0x80000480 0x80>; |
| 25 | interrupts = <12 13>; |
| 26 | clocks = <&clks 11>; |
| 27 | syscon = <&syscon1>; |
| Alexander Shiyan | 62b0a1b | 2014-09-06 07:20:15 +0400 | [diff] [blame] | 28 | cts-gpios = <&sysgpio 0 GPIO_ACTIVE_LOW>; |
| 29 | dsr-gpios = <&sysgpio 1 GPIO_ACTIVE_LOW>; |
| 30 | dcd-gpios = <&sysgpio 2 GPIO_ACTIVE_LOW>; |
| Alexander Shiyan | 3c0f0f9 | 2013-12-11 19:52:35 +0400 | [diff] [blame] | 31 | }; |
