blob: 406747f07dc0e32eb630b09dfc1b86f898988cd5 [file] [log] [blame]
Paul Mundt41504c32006-12-11 20:28:03 +09001/*
2 * SH7722 Setup
3 *
Paul Mundtb4d36a22008-10-28 18:40:19 +09004 * Copyright (C) 2006 - 2008 Paul Mundt
Paul Mundt41504c32006-12-11 20:28:03 +09005 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/platform_device.h>
11#include <linux/init.h>
12#include <linux/serial.h>
Paul Mundt96de1a82008-02-26 14:52:45 +090013#include <linux/serial_sci.h>
Paul Mundt520588f2007-06-06 17:58:56 +090014#include <linux/mm.h>
Magnus Damma55f6d22008-07-15 21:52:19 +090015#include <linux/uio_driver.h>
Magnus Damm424f59d2009-01-22 09:56:09 +000016#include <linux/sh_cmt.h>
Magnus Damm6c7d8262008-07-17 19:16:11 +090017#include <asm/clock.h>
Paul Mundt5bbeafc2007-06-06 19:05:11 +090018#include <asm/mmzone.h>
Paul Mundt41504c32006-12-11 20:28:03 +090019
Paul Mundtb4d36a22008-10-28 18:40:19 +090020static struct resource rtc_resources[] = {
21 [0] = {
22 .start = 0xa465fec0,
23 .end = 0xa465fec0 + 0x58 - 1,
24 .flags = IORESOURCE_IO,
25 },
26 [1] = {
27 /* Period IRQ */
28 .start = 45,
29 .flags = IORESOURCE_IRQ,
30 },
31 [2] = {
32 /* Carry IRQ */
33 .start = 46,
34 .flags = IORESOURCE_IRQ,
35 },
36 [3] = {
37 /* Alarm IRQ */
38 .start = 44,
39 .flags = IORESOURCE_IRQ,
40 },
41};
42
43static struct platform_device rtc_device = {
44 .name = "sh-rtc",
45 .id = -1,
46 .num_resources = ARRAY_SIZE(rtc_resources),
47 .resource = rtc_resources,
48};
49
Yoshihiro Shimoda262feaa2007-10-30 13:05:31 +090050static struct resource usbf_resources[] = {
51 [0] = {
Magnus Damm526c1c22008-05-22 22:15:31 +090052 .name = "m66592_udc",
Magnus Damma0d29792008-03-21 18:43:28 +090053 .start = 0x04480000,
54 .end = 0x044800FF,
Yoshihiro Shimoda262feaa2007-10-30 13:05:31 +090055 .flags = IORESOURCE_MEM,
56 },
57 [1] = {
Yoshihiro Shimoda262feaa2007-10-30 13:05:31 +090058 .start = 65,
59 .end = 65,
60 .flags = IORESOURCE_IRQ,
61 },
62};
63
64static struct platform_device usbf_device = {
65 .name = "m66592_udc",
Magnus Dammaf5be792008-10-31 20:22:13 +090066 .id = 0, /* "usbf0" clock */
Yoshihiro Shimoda262feaa2007-10-30 13:05:31 +090067 .dev = {
68 .dma_mask = NULL,
69 .coherent_dma_mask = 0xffffffff,
70 },
71 .num_resources = ARRAY_SIZE(usbf_resources),
72 .resource = usbf_resources,
73};
74
Magnus Dammef1b2322008-03-25 17:14:03 +090075static struct resource iic_resources[] = {
76 [0] = {
77 .name = "IIC",
78 .start = 0x04470000,
79 .end = 0x04470017,
80 .flags = IORESOURCE_MEM,
81 },
82 [1] = {
83 .start = 96,
84 .end = 99,
85 .flags = IORESOURCE_IRQ,
86 },
87};
88
89static struct platform_device iic_device = {
90 .name = "i2c-sh_mobile",
Magnus Damma5616bd2008-10-31 20:20:55 +090091 .id = 0, /* "i2c0" clock */
Magnus Dammef1b2322008-03-25 17:14:03 +090092 .num_resources = ARRAY_SIZE(iic_resources),
93 .resource = iic_resources,
94};
95
Magnus Damma55f6d22008-07-15 21:52:19 +090096static struct uio_info vpu_platform_data = {
97 .name = "VPU4",
98 .version = "0",
99 .irq = 60,
100};
101
102static struct resource vpu_resources[] = {
103 [0] = {
104 .name = "VPU",
105 .start = 0xfe900000,
106 .end = 0xfe9022eb,
107 .flags = IORESOURCE_MEM,
108 },
Magnus Damm1eca5c92008-07-16 19:02:54 +0900109 [1] = {
110 /* place holder for contiguous memory */
111 },
Magnus Damma55f6d22008-07-15 21:52:19 +0900112};
113
114static struct platform_device vpu_device = {
115 .name = "uio_pdrv_genirq",
116 .id = 0,
117 .dev = {
118 .platform_data = &vpu_platform_data,
119 },
120 .resource = vpu_resources,
121 .num_resources = ARRAY_SIZE(vpu_resources),
122};
123
124static struct uio_info veu_platform_data = {
125 .name = "VEU",
126 .version = "0",
127 .irq = 54,
128};
129
130static struct resource veu_resources[] = {
131 [0] = {
132 .name = "VEU",
133 .start = 0xfe920000,
134 .end = 0xfe9200b7,
135 .flags = IORESOURCE_MEM,
136 },
Magnus Damm1eca5c92008-07-16 19:02:54 +0900137 [1] = {
138 /* place holder for contiguous memory */
139 },
Magnus Damma55f6d22008-07-15 21:52:19 +0900140};
141
142static struct platform_device veu_device = {
143 .name = "uio_pdrv_genirq",
144 .id = 1,
145 .dev = {
146 .platform_data = &veu_platform_data,
147 },
148 .resource = veu_resources,
149 .num_resources = ARRAY_SIZE(veu_resources),
150};
151
Takanari Hayama7d91fcf2008-12-22 11:05:03 +0900152static struct uio_info jpu_platform_data = {
153 .name = "JPU",
154 .version = "0",
155 .irq = 27,
156};
157
158static struct resource jpu_resources[] = {
159 [0] = {
160 .name = "JPU",
161 .start = 0xfea00000,
Magnus Damm3442c0d2008-12-25 18:55:26 +0900162 .end = 0xfea102d3,
Takanari Hayama7d91fcf2008-12-22 11:05:03 +0900163 .flags = IORESOURCE_MEM,
164 },
165 [1] = {
166 /* place holder for contiguous memory */
167 },
168};
169
170static struct platform_device jpu_device = {
171 .name = "uio_pdrv_genirq",
172 .id = 2,
173 .dev = {
174 .platform_data = &jpu_platform_data,
175 },
176 .resource = jpu_resources,
177 .num_resources = ARRAY_SIZE(jpu_resources),
178};
179
Magnus Damm424f59d2009-01-22 09:56:09 +0000180static struct sh_cmt_config cmt_platform_data = {
181 .name = "CMT",
182 .channel_offset = 0x60,
183 .timer_bit = 5,
184 .clk = "cmt0",
185 .clockevent_rating = 125,
186 .clocksource_rating = 200,
187};
188
189static struct resource cmt_resources[] = {
190 [0] = {
191 .name = "CMT",
192 .start = 0x044a0060,
193 .end = 0x044a006b,
194 .flags = IORESOURCE_MEM,
195 },
196 [1] = {
197 .start = 104,
198 .flags = IORESOURCE_IRQ,
199 },
200};
201
202static struct platform_device cmt_device = {
203 .name = "sh_cmt",
204 .id = 0,
205 .dev = {
206 .platform_data = &cmt_platform_data,
207 },
208 .resource = cmt_resources,
209 .num_resources = ARRAY_SIZE(cmt_resources),
210};
211
Paul Mundt41504c32006-12-11 20:28:03 +0900212static struct plat_sci_port sci_platform_data[] = {
213 {
214 .mapbase = 0xffe00000,
215 .flags = UPF_BOOT_AUTOCONF,
216 .type = PORT_SCIF,
Magnus Damm53aba192007-07-17 18:10:11 +0900217 .irqs = { 80, 80, 80, 80 },
218 },
219 {
220 .mapbase = 0xffe10000,
221 .flags = UPF_BOOT_AUTOCONF,
222 .type = PORT_SCIF,
223 .irqs = { 81, 81, 81, 81 },
224 },
225 {
226 .mapbase = 0xffe20000,
227 .flags = UPF_BOOT_AUTOCONF,
228 .type = PORT_SCIF,
229 .irqs = { 82, 82, 82, 82 },
230 },
231 {
Paul Mundt41504c32006-12-11 20:28:03 +0900232 .flags = 0,
233 }
234};
235
236static struct platform_device sci_device = {
237 .name = "sh-sci",
238 .id = -1,
239 .dev = {
240 .platform_data = sci_platform_data,
241 },
242};
243
244static struct platform_device *sh7722_devices[] __initdata = {
Magnus Damm424f59d2009-01-22 09:56:09 +0000245 &cmt_device,
Paul Mundtb4d36a22008-10-28 18:40:19 +0900246 &rtc_device,
Yoshihiro Shimoda262feaa2007-10-30 13:05:31 +0900247 &usbf_device,
Magnus Dammef1b2322008-03-25 17:14:03 +0900248 &iic_device,
Paul Mundt41504c32006-12-11 20:28:03 +0900249 &sci_device,
Magnus Damma55f6d22008-07-15 21:52:19 +0900250 &vpu_device,
251 &veu_device,
Takanari Hayama7d91fcf2008-12-22 11:05:03 +0900252 &jpu_device,
Paul Mundt41504c32006-12-11 20:28:03 +0900253};
254
255static int __init sh7722_devices_setup(void)
256{
Magnus Dammef6aff62008-10-31 20:24:01 +0900257 clk_always_enable("uram0"); /* URAM */
258 clk_always_enable("xymem0"); /* XYMEM */
Magnus Dammef6aff62008-10-31 20:24:01 +0900259 clk_always_enable("veu0"); /* VEU */
260 clk_always_enable("vpu0"); /* VPU */
Takanari Hayama7d91fcf2008-12-22 11:05:03 +0900261 clk_always_enable("jpu0"); /* JPU */
Magnus Damm6c7d8262008-07-17 19:16:11 +0900262
Magnus Damm1eca5c92008-07-16 19:02:54 +0900263 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
264 platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
Takanari Hayama7d91fcf2008-12-22 11:05:03 +0900265 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
Magnus Damm6c7d8262008-07-17 19:16:11 +0900266
Paul Mundt41504c32006-12-11 20:28:03 +0900267 return platform_add_devices(sh7722_devices,
268 ARRAY_SIZE(sh7722_devices));
269}
270__initcall(sh7722_devices_setup);
271
Magnus Damm1b064282007-07-18 17:51:24 +0900272enum {
273 UNUSED=0,
274
275 /* interrupt sources */
276 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
277 HUDI,
278 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
279 RTC_ATI, RTC_PRI, RTC_CUI,
280 DMAC0, DMAC1, DMAC2, DMAC3,
281 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
282 VPU, TPU,
283 USB_USBI0, USB_USBI1,
284 DMAC4, DMAC5, DMAC_DADERR,
285 KEYSC,
286 SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
287 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
288 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
289 SDHI0, SDHI1, SDHI2, SDHI3,
290 CMT, TSIF, SIU, TWODG,
291 TMU0, TMU1, TMU2,
292 IRDA, JPU, LCDC,
293
294 /* interrupt groups */
Magnus Damm1b064282007-07-18 17:51:24 +0900295 SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
Paul Mundt41504c32006-12-11 20:28:03 +0900296};
297
Magnus Damm5c37e022007-08-17 00:45:35 +0900298static struct intc_vect vectors[] __initdata = {
Magnus Damm1b064282007-07-18 17:51:24 +0900299 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
300 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
301 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
302 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
303 INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
304 INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
305 INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
306 INTC_VECT(RTC_CUI, 0x7c0),
307 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
308 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
309 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
310 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
311 INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
312 INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
313 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
314 INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
315 INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
316 INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
317 INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
318 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
319 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
320 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
321 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
322 INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
323 INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
324 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
325 INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
326 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
327 INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
328 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
Paul Mundt41504c32006-12-11 20:28:03 +0900329};
330
Magnus Damm5c37e022007-08-17 00:45:35 +0900331static struct intc_group groups[] __initdata = {
Magnus Damm1b064282007-07-18 17:51:24 +0900332 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
333 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
334 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
335 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
336 INTC_GROUP(USB, USB_USBI0, USB_USBI1),
337 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
338 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
339 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
340 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
341 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
Magnus Damm68abdbb2007-06-15 18:56:19 +0900342};
Paul Mundt41504c32006-12-11 20:28:03 +0900343
Magnus Damm5c37e022007-08-17 00:45:35 +0900344static struct intc_mask_reg mask_registers[] __initdata = {
Magnus Damm1b064282007-07-18 17:51:24 +0900345 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
346 { } },
347 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
348 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
349 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
350 { 0, 0, 0, VPU, } },
351 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
352 { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
353 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
354 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
355 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
356 { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
357 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
358 { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
359 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
360 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
361 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
362 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
363 { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, TWODG, SIU } },
364 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
365 { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
366 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
367 { } },
368 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
369 { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
370 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
371 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
372};
373
Magnus Damm5c37e022007-08-17 00:45:35 +0900374static struct intc_prio_reg prio_registers[] __initdata = {
Magnus Damm6ef5fb22007-08-12 15:22:02 +0900375 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
376 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
377 { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
378 { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
379 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
380 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
381 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
382 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
383 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
384 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
385 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
386 { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
387 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
Magnus Damm1b064282007-07-18 17:51:24 +0900388 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
389};
390
Magnus Damm5c37e022007-08-17 00:45:35 +0900391static struct intc_sense_reg sense_registers[] __initdata = {
Magnus Damm1b064282007-07-18 17:51:24 +0900392 { 0xa414001c, 16, 2, /* ICR1 */
393 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
394};
395
Yoshihiro Shimoda6bdfb222008-07-04 12:37:12 +0900396static struct intc_mask_reg ack_registers[] __initdata = {
397 { 0xa4140024, 0, 8, /* INTREQ00 */
398 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
399};
400
401static DECLARE_INTC_DESC_ACK(intc_desc, "sh7722", vectors, groups,
402 mask_registers, prio_registers, sense_registers,
403 ack_registers);
Magnus Damm1b064282007-07-18 17:51:24 +0900404
Magnus Damm90015c82007-07-18 17:57:34 +0900405void __init plat_irq_setup(void)
Paul Mundt41504c32006-12-11 20:28:03 +0900406{
Magnus Damm1b064282007-07-18 17:51:24 +0900407 register_intc_controller(&intc_desc);
Paul Mundt41504c32006-12-11 20:28:03 +0900408}
Paul Mundt520588f2007-06-06 17:58:56 +0900409
410void __init plat_mem_setup(void)
411{
412 /* Register the URAM space as Node 1 */
413 setup_bootmem_node(1, 0x055f0000, 0x05610000);
414}