blob: 48abee4eee29d8589d9452029f109e102f63f91a [file] [log] [blame]
Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001// SPDX-License-Identifier: GPL-2.0
Adrian Bunkb00dc832008-05-19 16:52:27 -07002/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 * linux/arch/sparc64/kernel/setup.c
4 *
5 * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
7 */
8
9#include <linux/errno.h>
10#include <linux/sched.h>
11#include <linux/kernel.h>
12#include <linux/mm.h>
13#include <linux/stddef.h>
14#include <linux/unistd.h>
15#include <linux/ptrace.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070016#include <asm/smp.h>
17#include <linux/user.h>
Jon Smirl894673e2006-07-10 04:44:13 -070018#include <linux/screen_info.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070019#include <linux/delay.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020#include <linux/fs.h>
21#include <linux/seq_file.h>
22#include <linux/syscalls.h>
23#include <linux/kdev_t.h>
24#include <linux/major.h>
25#include <linux/string.h>
26#include <linux/init.h>
27#include <linux/inet.h>
28#include <linux/console.h>
29#include <linux/root_dev.h>
30#include <linux/interrupt.h>
31#include <linux/cpu.h>
32#include <linux/initrd.h>
David S. Millerac85fe82011-07-28 23:31:26 -070033#include <linux/module.h>
David S. Milleref3e0352014-10-23 12:58:13 -070034#include <linux/start_kernel.h>
Mike Rapoport57c8a662018-10-30 15:09:49 -070035#include <linux/memblock.h>
David Howellse262e32d2018-11-01 23:07:23 +000036#include <uapi/linux/mount.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070037
Linus Torvalds1da177e2005-04-16 15:20:36 -070038#include <asm/io.h>
39#include <asm/processor.h>
40#include <asm/oplib.h>
41#include <asm/page.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070042#include <asm/idprom.h>
43#include <asm/head.h>
44#include <asm/starfire.h>
45#include <asm/mmu_context.h>
46#include <asm/timer.h>
47#include <asm/sections.h>
48#include <asm/setup.h>
49#include <asm/mmu.h>
David S. Miller5cbc3072007-05-25 15:49:59 -070050#include <asm/ns87303.h>
David S. Millerc57ec522009-11-27 17:33:43 -080051#include <asm/btext.h>
David S. Millerac85fe82011-07-28 23:31:26 -070052#include <asm/elf.h>
53#include <asm/mdesc.h>
David Howellsd550bbd2012-03-28 18:30:03 +010054#include <asm/cacheflush.h>
Atish Patraebb99a42016-09-15 14:54:41 -060055#include <asm/dma.h>
56#include <asm/irq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070057
58#ifdef CONFIG_IP_PNP
59#include <net/ipconfig.h>
60#endif
61
David S. Miller3d5ae6b2008-03-25 21:51:40 -070062#include "entry.h"
Sam Ravnborg53ae3412008-12-07 00:02:08 -080063#include "kernel.h"
David S. Miller3d5ae6b2008-03-25 21:51:40 -070064
David S. Miller5cbc3072007-05-25 15:49:59 -070065/* Used to synchronize accesses to NatSemi SUPER I/O chip configure
66 * operations in asm/ns87303.h
67 */
68DEFINE_SPINLOCK(ns87303_lock);
Sam Ravnborg917c3662009-01-08 16:58:20 -080069EXPORT_SYMBOL(ns87303_lock);
David S. Miller5cbc3072007-05-25 15:49:59 -070070
Linus Torvalds1da177e2005-04-16 15:20:36 -070071struct screen_info screen_info = {
72 0, 0, /* orig-x, orig-y */
73 0, /* unused */
74 0, /* orig-video-page */
75 0, /* orig-video-mode */
76 128, /* orig-video-cols */
77 0, 0, 0, /* unused, ega_bx, unused */
78 54, /* orig-video-lines */
79 0, /* orig-video-isVGA */
80 16 /* orig-video-points */
81};
82
Linus Torvalds1da177e2005-04-16 15:20:36 -070083static void
Joe Perches9ef595d2016-03-10 15:21:43 -080084prom_console_write(struct console *con, const char *s, unsigned int n)
Linus Torvalds1da177e2005-04-16 15:20:36 -070085{
86 prom_write(s, n);
87}
88
Linus Torvalds1da177e2005-04-16 15:20:36 -070089/* Exported for mm/init.c:paging_init. */
90unsigned long cmdline_memory_size = 0;
91
David S. Miller3c62a2d2008-02-17 23:22:50 -080092static struct console prom_early_console = {
93 .name = "earlyprom",
Linus Torvalds1da177e2005-04-16 15:20:36 -070094 .write = prom_console_write,
David S. Millerdb9a7fb2008-04-23 22:22:29 -070095 .flags = CON_PRINTBUFFER | CON_BOOT | CON_ANYTIME,
Linus Torvalds1da177e2005-04-16 15:20:36 -070096 .index = -1,
97};
98
Pavel Tatashin68a79212017-06-12 16:41:41 -040099/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100 * Process kernel command line switches that are specific to the
101 * SPARC or that require special low-level processing.
102 */
103static void __init process_switch(char c)
104{
105 switch (c) {
106 case 'd':
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107 case 's':
Linus Torvalds1da177e2005-04-16 15:20:36 -0700108 break;
109 case 'h':
110 prom_printf("boot_flags_init: Halt!\n");
111 prom_halt();
112 break;
113 case 'p':
David S. Miller11032c12011-09-21 12:48:06 -0700114 prom_early_console.flags &= ~CON_BOOT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700115 break;
David S. Miller816242d2005-05-23 15:52:08 -0700116 case 'P':
117 /* Force UltraSPARC-III P-Cache on. */
118 if (tlb_type != cheetah) {
119 printk("BOOT: Ignoring P-Cache force option.\n");
120 break;
121 }
122 cheetah_pcache_forced_on = 1;
Rusty Russell373d4d02013-01-21 17:17:39 +1030123 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
David S. Miller816242d2005-05-23 15:52:08 -0700124 cheetah_enable_pcache();
125 break;
126
Linus Torvalds1da177e2005-04-16 15:20:36 -0700127 default:
128 printk("Unknown boot switch (-%c)\n", c);
129 break;
130 }
131}
132
Linus Torvalds1da177e2005-04-16 15:20:36 -0700133static void __init boot_flags_init(char *commands)
134{
135 while (*commands) {
136 /* Move to the start of the next "argument". */
David S. Miller8c644152017-05-03 08:28:48 -0700137 while (*commands == ' ')
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138 commands++;
139
140 /* Process any command switches, otherwise skip it. */
141 if (*commands == '\0')
142 break;
143 if (*commands == '-') {
144 commands++;
145 while (*commands && *commands != ' ')
146 process_switch(*commands++);
147 continue;
148 }
bob picco7c21d532014-09-16 09:29:54 -0400149 if (!strncmp(commands, "mem=", 4))
150 cmdline_memory_size = memparse(commands + 4, &commands);
151
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152 while (*commands && *commands != ' ')
153 commands++;
154 }
155}
156
Linus Torvalds1da177e2005-04-16 15:20:36 -0700157extern unsigned short root_flags;
158extern unsigned short root_dev;
159extern unsigned short ram_flags;
160#define RAMDISK_IMAGE_START_MASK 0x07FF
161#define RAMDISK_PROMPT_FLAG 0x8000
162#define RAMDISK_LOAD_FLAG 0x4000
163
164extern int root_mountflags;
165
166char reboot_command[COMMAND_LINE_SIZE];
167
David S. Milleref3e0352014-10-23 12:58:13 -0700168static void __init per_cpu_patch(void)
David S. Miller92704a12006-02-26 23:27:19 -0800169{
David S. Miller92704a12006-02-26 23:27:19 -0800170 struct cpuid_patch_entry *p;
171 unsigned long ver;
172 int is_jbus;
173
174 if (tlb_type == spitfire && !this_is_starfire)
175 return;
176
David S. Millerd82ace72006-02-09 02:52:44 -0800177 is_jbus = 0;
178 if (tlb_type != hypervisor) {
179 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
David S. Millerebd8c562006-02-17 08:38:06 -0800180 is_jbus = ((ver >> 32UL) == __JALAPENO_ID ||
181 (ver >> 32UL) == __SERRANO_ID);
David S. Millerd82ace72006-02-09 02:52:44 -0800182 }
David S. Miller92704a12006-02-26 23:27:19 -0800183
184 p = &__cpuid_patch;
185 while (p < &__cpuid_patch_end) {
186 unsigned long addr = p->addr;
187 unsigned int *insns;
188
189 switch (tlb_type) {
190 case spitfire:
191 insns = &p->starfire[0];
192 break;
193 case cheetah:
194 case cheetah_plus:
195 if (is_jbus)
196 insns = &p->cheetah_jbus[0];
197 else
198 insns = &p->cheetah_safari[0];
199 break;
David S. Millerd96b8152006-02-04 15:40:53 -0800200 case hypervisor:
201 insns = &p->sun4v[0];
202 break;
David S. Miller92704a12006-02-26 23:27:19 -0800203 default:
204 prom_printf("Unknown cpu type, halting.\n");
205 prom_halt();
Joe Perches6cb79b32011-06-03 14:45:23 +0000206 }
David S. Miller92704a12006-02-26 23:27:19 -0800207
208 *(unsigned int *) (addr + 0) = insns[0];
David S. Miller840aaef2006-02-06 15:52:05 -0800209 wmb();
David S. Miller92704a12006-02-26 23:27:19 -0800210 __asm__ __volatile__("flush %0" : : "r" (addr + 0));
211
212 *(unsigned int *) (addr + 4) = insns[1];
David S. Miller840aaef2006-02-06 15:52:05 -0800213 wmb();
David S. Miller92704a12006-02-26 23:27:19 -0800214 __asm__ __volatile__("flush %0" : : "r" (addr + 4));
215
216 *(unsigned int *) (addr + 8) = insns[2];
David S. Miller840aaef2006-02-06 15:52:05 -0800217 wmb();
David S. Miller92704a12006-02-26 23:27:19 -0800218 __asm__ __volatile__("flush %0" : : "r" (addr + 8));
219
220 *(unsigned int *) (addr + 12) = insns[3];
David S. Miller840aaef2006-02-06 15:52:05 -0800221 wmb();
David S. Miller92704a12006-02-26 23:27:19 -0800222 __asm__ __volatile__("flush %0" : : "r" (addr + 12));
223
224 p++;
225 }
David S. Miller92704a12006-02-26 23:27:19 -0800226}
227
David S. Miller0b641202011-11-17 22:44:58 -0800228void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start,
229 struct sun4v_1insn_patch_entry *end)
230{
231 while (start < end) {
232 unsigned long addr = start->addr;
233
234 *(unsigned int *) (addr + 0) = start->insn;
235 wmb();
236 __asm__ __volatile__("flush %0" : : "r" (addr + 0));
237
238 start++;
239 }
240}
241
242void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
243 struct sun4v_2insn_patch_entry *end)
244{
245 while (start < end) {
246 unsigned long addr = start->addr;
247
248 *(unsigned int *) (addr + 0) = start->insns[0];
249 wmb();
250 __asm__ __volatile__("flush %0" : : "r" (addr + 0));
251
252 *(unsigned int *) (addr + 4) = start->insns[1];
253 wmb();
254 __asm__ __volatile__("flush %0" : : "r" (addr + 4));
255
256 start++;
257 }
258}
259
Khalid Aziz494e5b62015-05-27 10:00:46 -0600260void sun_m7_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
261 struct sun4v_2insn_patch_entry *end)
262{
263 while (start < end) {
264 unsigned long addr = start->addr;
265
266 *(unsigned int *) (addr + 0) = start->insns[0];
267 wmb();
268 __asm__ __volatile__("flush %0" : : "r" (addr + 0));
269
270 *(unsigned int *) (addr + 4) = start->insns[1];
271 wmb();
272 __asm__ __volatile__("flush %0" : : "r" (addr + 4));
273
274 start++;
275 }
276}
277
David S. Milleref3e0352014-10-23 12:58:13 -0700278static void __init sun4v_patch(void)
David S. Miller936f4822006-02-05 21:29:28 -0800279{
David S. Millerc7754d42007-05-15 17:03:54 -0700280 extern void sun4v_hvapi_init(void);
David S. Miller936f4822006-02-05 21:29:28 -0800281
282 if (tlb_type != hypervisor)
283 return;
284
David S. Miller0b641202011-11-17 22:44:58 -0800285 sun4v_patch_1insn_range(&__sun4v_1insn_patch,
286 &__sun4v_1insn_patch_end);
David S. Miller936f4822006-02-05 21:29:28 -0800287
David S. Miller0b641202011-11-17 22:44:58 -0800288 sun4v_patch_2insn_range(&__sun4v_2insn_patch,
289 &__sun4v_2insn_patch_end);
Allen Pais7d484ac2017-07-24 11:44:18 +0530290
291 switch (sun4v_chip_type) {
292 case SUN4V_CHIP_SPARC_M7:
293 case SUN4V_CHIP_SPARC_M8:
294 case SUN4V_CHIP_SPARC_SN:
Khalid Aziz74a04962018-02-23 15:46:41 -0700295 sun4v_patch_1insn_range(&__sun_m7_1insn_patch,
296 &__sun_m7_1insn_patch_end);
Khalid Aziz494e5b62015-05-27 10:00:46 -0600297 sun_m7_patch_2insn_range(&__sun_m7_2insn_patch,
298 &__sun_m7_2insn_patch_end);
Allen Pais7d484ac2017-07-24 11:44:18 +0530299 break;
300 default:
301 break;
302 }
David S. Millerc7754d42007-05-15 17:03:54 -0700303
Anthony Yznagaa7159a82017-08-18 12:40:36 -0700304 if (sun4v_chip_type != SUN4V_CHIP_NIAGARA1) {
305 sun4v_patch_1insn_range(&__fast_win_ctrl_1insn_patch,
306 &__fast_win_ctrl_1insn_patch_end);
307 }
308
David S. Millerc7754d42007-05-15 17:03:54 -0700309 sun4v_hvapi_init();
David S. Miller936f4822006-02-05 21:29:28 -0800310}
311
David S. Milleref7c4d42011-07-29 09:42:07 -0700312static void __init popc_patch(void)
313{
314 struct popc_3insn_patch_entry *p3;
David S. Miller56d205c2011-08-02 20:23:34 -0700315 struct popc_6insn_patch_entry *p6;
David S. Milleref7c4d42011-07-29 09:42:07 -0700316
317 p3 = &__popc_3insn_patch;
318 while (p3 < &__popc_3insn_patch_end) {
David S. Miller56d205c2011-08-02 20:23:34 -0700319 unsigned long i, addr = p3->addr;
David S. Milleref7c4d42011-07-29 09:42:07 -0700320
David S. Miller56d205c2011-08-02 20:23:34 -0700321 for (i = 0; i < 3; i++) {
322 *(unsigned int *) (addr + (i * 4)) = p3->insns[i];
323 wmb();
324 __asm__ __volatile__("flush %0"
325 : : "r" (addr + (i * 4)));
326 }
David S. Milleref7c4d42011-07-29 09:42:07 -0700327
328 p3++;
329 }
David S. Miller56d205c2011-08-02 20:23:34 -0700330
331 p6 = &__popc_6insn_patch;
332 while (p6 < &__popc_6insn_patch_end) {
333 unsigned long i, addr = p6->addr;
334
335 for (i = 0; i < 6; i++) {
336 *(unsigned int *) (addr + (i * 4)) = p6->insns[i];
337 wmb();
338 __asm__ __volatile__("flush %0"
339 : : "r" (addr + (i * 4)));
340 }
341
342 p6++;
343 }
David S. Milleref7c4d42011-07-29 09:42:07 -0700344}
345
David S. Millere9b9eb52012-10-27 23:00:41 -0700346static void __init pause_patch(void)
347{
348 struct pause_patch_entry *p;
349
David S. Miller187818c2012-10-28 13:04:47 -0700350 p = &__pause_3insn_patch;
351 while (p < &__pause_3insn_patch_end) {
David S. Millere9b9eb52012-10-27 23:00:41 -0700352 unsigned long i, addr = p->addr;
353
354 for (i = 0; i < 3; i++) {
355 *(unsigned int *) (addr + (i * 4)) = p->insns[i];
356 wmb();
357 __asm__ __volatile__("flush %0"
358 : : "r" (addr + (i * 4)));
359 }
360
361 p++;
362 }
363}
364
David S. Milleref3e0352014-10-23 12:58:13 -0700365void __init start_early_boot(void)
David S. Miller951bc822006-05-31 01:24:02 -0700366{
David S. Milleref3e0352014-10-23 12:58:13 -0700367 int cpu;
368
369 check_if_starfire();
370 per_cpu_patch();
371 sun4v_patch();
Vijay Kumar8536e022017-07-21 10:23:57 -0600372 smp_init_cpu_poke();
David S. Milleref3e0352014-10-23 12:58:13 -0700373
374 cpu = hard_smp_processor_id();
375 if (cpu >= NR_CPUS) {
376 prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
377 cpu, NR_CPUS);
378 prom_halt();
379 }
380 current_thread_info()->cpu = cpu;
381
Pavel Tatashin83e8eb92017-06-12 16:41:46 -0400382 time_init_early();
David S. Milleref3e0352014-10-23 12:58:13 -0700383 prom_init_report();
384 start_kernel();
David S. Miller951bc822006-05-31 01:24:02 -0700385}
David S. Miller951bc822006-05-31 01:24:02 -0700386
David S. Millerac85fe82011-07-28 23:31:26 -0700387/* On Ultra, we support all of the v8 capabilities. */
388unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR |
389 HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV |
390 HWCAP_SPARC_V9);
391EXPORT_SYMBOL(sparc64_elf_hwcap);
392
393static const char *hwcaps[] = {
394 "flush", "stbar", "swap", "muldiv", "v9",
395 "ultra3", "blkinit", "n2",
396
397 /* These strings are as they appear in the machine description
398 * 'hwcap-list' property for cpu nodes.
399 */
400 "mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
401 "ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
Khalid Aziz82924e52015-12-17 10:33:50 -0700402 "ima", "cspare", "pause", "cbcond", NULL /*reserved for crypto */,
403 "adp",
David S. Miller6f859c02012-08-16 16:41:04 -0700404};
405
406static const char *crypto_hwcaps[] = {
407 "aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256",
408 "sha512", "mpmul", "montmul", "montsqr", "crc32c",
David S. Millerac85fe82011-07-28 23:31:26 -0700409};
410
411void cpucap_info(struct seq_file *m)
412{
413 unsigned long caps = sparc64_elf_hwcap;
414 int i, printed = 0;
415
416 seq_puts(m, "cpucaps\t\t: ");
417 for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
418 unsigned long bit = 1UL << i;
Khalid Aziz82924e52015-12-17 10:33:50 -0700419 if (hwcaps[i] && (caps & bit)) {
David S. Millerac85fe82011-07-28 23:31:26 -0700420 seq_printf(m, "%s%s",
421 printed ? "," : "", hwcaps[i]);
422 printed++;
423 }
424 }
David S. Miller6f859c02012-08-16 16:41:04 -0700425 if (caps & HWCAP_SPARC_CRYPTO) {
426 unsigned long cfr;
427
428 __asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
429 for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
430 unsigned long bit = 1UL << i;
431 if (cfr & bit) {
432 seq_printf(m, "%s%s",
433 printed ? "," : "", crypto_hwcaps[i]);
434 printed++;
435 }
436 }
437 }
David S. Millerac85fe82011-07-28 23:31:26 -0700438 seq_putc(m, '\n');
439}
440
David S. Miller6f859c02012-08-16 16:41:04 -0700441static void __init report_one_hwcap(int *printed, const char *name)
442{
443 if ((*printed) == 0)
444 printk(KERN_INFO "CPU CAPS: [");
445 printk(KERN_CONT "%s%s",
446 (*printed) ? "," : "", name);
447 if (++(*printed) == 8) {
448 printk(KERN_CONT "]\n");
449 *printed = 0;
450 }
451}
452
453static void __init report_crypto_hwcaps(int *printed)
454{
455 unsigned long cfr;
456 int i;
457
458 __asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
459
460 for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
461 unsigned long bit = 1UL << i;
462 if (cfr & bit)
463 report_one_hwcap(printed, crypto_hwcaps[i]);
464 }
465}
466
David S. Millerac85fe82011-07-28 23:31:26 -0700467static void __init report_hwcaps(unsigned long caps)
468{
469 int i, printed = 0;
470
David S. Millerac85fe82011-07-28 23:31:26 -0700471 for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
472 unsigned long bit = 1UL << i;
Khalid Aziz82924e52015-12-17 10:33:50 -0700473 if (hwcaps[i] && (caps & bit))
David S. Miller6f859c02012-08-16 16:41:04 -0700474 report_one_hwcap(&printed, hwcaps[i]);
David S. Millerac85fe82011-07-28 23:31:26 -0700475 }
David S. Miller6f859c02012-08-16 16:41:04 -0700476 if (caps & HWCAP_SPARC_CRYPTO)
477 report_crypto_hwcaps(&printed);
478 if (printed != 0)
479 printk(KERN_CONT "]\n");
David S. Millerac85fe82011-07-28 23:31:26 -0700480}
481
482static unsigned long __init mdesc_cpu_hwcap_list(void)
483{
484 struct mdesc_handle *hp;
485 unsigned long caps = 0;
486 const char *prop;
487 int len;
488 u64 pn;
489
490 hp = mdesc_grab();
491 if (!hp)
492 return 0;
493
494 pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu");
495 if (pn == MDESC_NODE_NULL)
496 goto out;
497
498 prop = mdesc_get_property(hp, pn, "hwcap-list", &len);
499 if (!prop)
500 goto out;
501
502 while (len) {
503 int i, plen;
504
505 for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
506 unsigned long bit = 1UL << i;
507
Khalid Aziz82924e52015-12-17 10:33:50 -0700508 if (hwcaps[i] && !strcmp(prop, hwcaps[i])) {
David S. Millerac85fe82011-07-28 23:31:26 -0700509 caps |= bit;
510 break;
511 }
512 }
David S. Miller6f859c02012-08-16 16:41:04 -0700513 for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
514 if (!strcmp(prop, crypto_hwcaps[i]))
515 caps |= HWCAP_SPARC_CRYPTO;
516 }
David S. Millerac85fe82011-07-28 23:31:26 -0700517
518 plen = strlen(prop) + 1;
519 prop += plen;
520 len -= plen;
521 }
522
523out:
524 mdesc_release(hp);
525 return caps;
526}
527
528/* This yields a mask that user programs can use to figure out what
529 * instruction set this cpu supports.
530 */
531static void __init init_sparc64_elf_hwcap(void)
532{
533 unsigned long cap = sparc64_elf_hwcap;
534 unsigned long mdesc_caps;
535
536 if (tlb_type == cheetah || tlb_type == cheetah_plus)
537 cap |= HWCAP_SPARC_ULTRA3;
538 else if (tlb_type == hypervisor) {
539 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
540 sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
David S. Miller08cefa92011-09-11 10:42:20 -0700541 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
542 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
Allen Pais4e963772013-07-23 16:50:38 +0530543 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
Allen Pais40831622014-09-08 11:48:55 +0530544 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
545 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
Allen Pais7d484ac2017-07-24 11:44:18 +0530546 sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
Khalid Azizc5b8b5b2016-04-19 11:12:54 -0600547 sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
Allen Pais4e963772013-07-23 16:50:38 +0530548 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
David S. Millerac85fe82011-07-28 23:31:26 -0700549 cap |= HWCAP_SPARC_BLKINIT;
550 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
David S. Miller08cefa92011-09-11 10:42:20 -0700551 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
552 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
Allen Pais4e963772013-07-23 16:50:38 +0530553 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
Allen Pais40831622014-09-08 11:48:55 +0530554 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
555 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
Allen Pais7d484ac2017-07-24 11:44:18 +0530556 sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
Khalid Azizc5b8b5b2016-04-19 11:12:54 -0600557 sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
Allen Pais4e963772013-07-23 16:50:38 +0530558 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
David S. Millerac85fe82011-07-28 23:31:26 -0700559 cap |= HWCAP_SPARC_N2;
560 }
561
562 cap |= (AV_SPARC_MUL32 | AV_SPARC_DIV32 | AV_SPARC_V8PLUS);
563
564 mdesc_caps = mdesc_cpu_hwcap_list();
565 if (!mdesc_caps) {
566 if (tlb_type == spitfire)
567 cap |= AV_SPARC_VIS;
568 if (tlb_type == cheetah || tlb_type == cheetah_plus)
569 cap |= AV_SPARC_VIS | AV_SPARC_VIS2;
David S. Miller1a8e0da2011-08-29 21:14:29 -0700570 if (tlb_type == cheetah_plus) {
571 unsigned long impl, ver;
572
573 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
574 impl = ((ver >> 32) & 0xffff);
575 if (impl == PANTHER_IMPL)
576 cap |= AV_SPARC_POPC;
577 }
David S. Millerac85fe82011-07-28 23:31:26 -0700578 if (tlb_type == hypervisor) {
579 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
580 cap |= AV_SPARC_ASI_BLK_INIT;
581 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
David S. Miller08cefa92011-09-11 10:42:20 -0700582 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
583 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
Allen Pais4e963772013-07-23 16:50:38 +0530584 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
Allen Pais40831622014-09-08 11:48:55 +0530585 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
586 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
Allen Pais7d484ac2017-07-24 11:44:18 +0530587 sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
Khalid Azizc5b8b5b2016-04-19 11:12:54 -0600588 sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
Allen Pais4e963772013-07-23 16:50:38 +0530589 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
David S. Millerac85fe82011-07-28 23:31:26 -0700590 cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
591 AV_SPARC_ASI_BLK_INIT |
592 AV_SPARC_POPC);
David S. Miller08cefa92011-09-11 10:42:20 -0700593 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
594 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
Allen Pais4e963772013-07-23 16:50:38 +0530595 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
Allen Pais40831622014-09-08 11:48:55 +0530596 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
597 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
Allen Pais7d484ac2017-07-24 11:44:18 +0530598 sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
Khalid Azizc5b8b5b2016-04-19 11:12:54 -0600599 sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
Allen Pais4e963772013-07-23 16:50:38 +0530600 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
David S. Millerac85fe82011-07-28 23:31:26 -0700601 cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
602 AV_SPARC_FMAF);
603 }
604 }
605 sparc64_elf_hwcap = cap | mdesc_caps;
606
607 report_hwcaps(sparc64_elf_hwcap);
David S. Milleref7c4d42011-07-29 09:42:07 -0700608
609 if (sparc64_elf_hwcap & AV_SPARC_POPC)
610 popc_patch();
David S. Millere9b9eb52012-10-27 23:00:41 -0700611 if (sparc64_elf_hwcap & AV_SPARC_PAUSE)
612 pause_patch();
David S. Millerac85fe82011-07-28 23:31:26 -0700613}
614
Atish Patraebb99a42016-09-15 14:54:41 -0600615void __init alloc_irqstack_bootmem(void)
616{
617 unsigned int i, node;
618
619 for_each_possible_cpu(i) {
620 node = cpu_to_node(i);
621
Mike Rapoportccfa2a02018-10-30 15:08:45 -0700622 softirq_stack[i] = memblock_alloc_node(THREAD_SIZE,
623 THREAD_SIZE, node);
Mike Rapoportb1e1c862019-03-11 23:30:10 -0700624 if (!softirq_stack[i])
625 panic("%s: Failed to allocate %lu bytes align=%lx nid=%d\n",
626 __func__, THREAD_SIZE, THREAD_SIZE, node);
Mike Rapoportccfa2a02018-10-30 15:08:45 -0700627 hardirq_stack[i] = memblock_alloc_node(THREAD_SIZE,
628 THREAD_SIZE, node);
Mike Rapoportb1e1c862019-03-11 23:30:10 -0700629 if (!hardirq_stack[i])
630 panic("%s: Failed to allocate %lu bytes align=%lx nid=%d\n",
631 __func__, THREAD_SIZE, THREAD_SIZE, node);
Atish Patraebb99a42016-09-15 14:54:41 -0600632 }
633}
634
Linus Torvalds1da177e2005-04-16 15:20:36 -0700635void __init setup_arch(char **cmdline_p)
636{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700637 /* Initialize PROM console and command line. */
638 *cmdline_p = prom_getbootargs();
Zhao Hongjiang117a0c52013-06-09 16:57:58 +0800639 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
David S. Millerce3b1d42008-03-19 03:54:09 -0700640 parse_early_param();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641
David S. Miller3c62a2d2008-02-17 23:22:50 -0800642 boot_flags_init(*cmdline_p);
David S. Millerc57ec522009-11-27 17:33:43 -0800643#ifdef CONFIG_EARLYFB
644 if (btext_find_display())
645#endif
646 register_console(&prom_early_console);
David S. Miller3c62a2d2008-02-17 23:22:50 -0800647
David S. Miller3a8c0692006-02-09 02:54:54 -0800648 if (tlb_type == hypervisor)
Corentin Labbeafaffac2018-12-11 12:11:09 +0000649 pr_info("ARCH: SUN4V\n");
David S. Miller3a8c0692006-02-09 02:54:54 -0800650 else
Corentin Labbeafaffac2018-12-11 12:11:09 +0000651 pr_info("ARCH: SUN4U\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700652
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653 idprom_init();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700654
655 if (!root_flags)
656 root_mountflags &= ~MS_RDONLY;
657 ROOT_DEV = old_decode_dev(root_dev);
Andrew Morton467418f2006-03-19 12:46:55 -0800658#ifdef CONFIG_BLK_DEV_RAM
Linus Torvalds1da177e2005-04-16 15:20:36 -0700659 rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700660#endif
661
Linus Torvalds1da177e2005-04-16 15:20:36 -0700662#ifdef CONFIG_IP_PNP
663 if (!ic_set_manually) {
Andres Salomon8d125562010-10-08 14:18:11 -0700664 phandle chosen = prom_finddevice("/chosen");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665 u32 cl, sv, gw;
Pavel Tatashin68a79212017-06-12 16:41:41 -0400666
Linus Torvalds1da177e2005-04-16 15:20:36 -0700667 cl = prom_getintdefault (chosen, "client-ip", 0);
668 sv = prom_getintdefault (chosen, "server-ip", 0);
669 gw = prom_getintdefault (chosen, "gateway-ip", 0);
670 if (cl && sv) {
671 ic_myaddr = cl;
672 ic_servaddr = sv;
673 if (gw)
674 ic_gateway = gw;
675#if defined(CONFIG_IP_PNP_BOOTP) || defined(CONFIG_IP_PNP_RARP)
676 ic_proto_enabled = 0;
677#endif
678 }
679 }
680#endif
681
David S. Miller56fb4df2006-02-26 23:24:22 -0800682 /* Get boot processor trap_block[] setup. */
David S. Miller72aff532006-02-17 01:29:17 -0800683 init_cur_cpu_trap(current_thread_info());
David S. Miller52845cd2006-02-26 23:32:33 -0800684
685 paging_init();
David S. Millerac85fe82011-07-28 23:31:26 -0700686 init_sparc64_elf_hwcap();
Atish Patra9b2f7532016-09-15 14:54:40 -0600687 smp_fill_in_cpu_possible_map();
Atish Patraebb99a42016-09-15 14:54:41 -0600688 /*
689 * Once the OF device tree and MDESC have been setup and nr_cpus has
690 * been parsed, we know the list of possible cpus. Therefore we can
691 * allocate the IRQ stacks.
692 */
693 alloc_irqstack_bootmem();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700694}
695
Linus Torvalds1da177e2005-04-16 15:20:36 -0700696extern int stop_a_enabled;
697
698void sun_do_break(void)
699{
700 if (!stop_a_enabled)
701 return;
702
703 prom_printf("\n");
704 flush_user_windows();
705
706 prom_cmdline();
707}
Sam Ravnborg917c3662009-01-08 16:58:20 -0800708EXPORT_SYMBOL(sun_do_break);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700709
Linus Torvalds1da177e2005-04-16 15:20:36 -0700710int stop_a_enabled = 1;
Sam Ravnborg917c3662009-01-08 16:58:20 -0800711EXPORT_SYMBOL(stop_a_enabled);