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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * STx GP3 board specific routines
3 *
4 * Dan Malek <dan@embeddededge.com>
5 * Copyright 2004 Embedded Edge, LLC
6 *
7 * Copied from mpc8560_ads.c
8 * Copyright 2002, 2003 Motorola Inc.
9 *
10 * Ported to 2.6, Matt Porter <mporter@kernel.crashing.org>
11 * Copyright 2004-2005 MontaVista Software, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19#include <linux/config.h>
20#include <linux/stddef.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/errno.h>
24#include <linux/reboot.h>
25#include <linux/pci.h>
26#include <linux/kdev_t.h>
27#include <linux/major.h>
28#include <linux/blkdev.h>
29#include <linux/console.h>
30#include <linux/delay.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070031#include <linux/root_dev.h>
32#include <linux/seq_file.h>
33#include <linux/serial.h>
34#include <linux/initrd.h>
35#include <linux/module.h>
36#include <linux/fsl_devices.h>
37#include <linux/interrupt.h>
Matt Porter2b0c28d7f2005-11-07 01:00:19 -080038#include <linux/rio.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070039
40#include <asm/system.h>
41#include <asm/pgtable.h>
42#include <asm/page.h>
43#include <asm/atomic.h>
44#include <asm/time.h>
45#include <asm/io.h>
46#include <asm/machdep.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#include <asm/open_pic.h>
48#include <asm/bootinfo.h>
49#include <asm/pci-bridge.h>
50#include <asm/mpc85xx.h>
51#include <asm/irq.h>
52#include <asm/immap_85xx.h>
Kumar Galad054b5a2005-07-27 11:44:06 -070053#include <asm/cpm2.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070054#include <asm/mpc85xx.h>
55#include <asm/ppc_sys.h>
56
57#include <syslib/cpm2_pic.h>
58#include <syslib/ppc85xx_common.h>
Matt Porter2b0c28d7f2005-11-07 01:00:19 -080059#include <syslib/ppc85xx_rio.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070060
Linus Torvalds1da177e2005-04-16 15:20:36 -070061
62unsigned char __res[sizeof(bd_t)];
63
64#ifndef CONFIG_PCI
65unsigned long isa_io_base = 0;
66unsigned long isa_mem_base = 0;
67unsigned long pci_dram_offset = 0;
68#endif
69
70/* Internal interrupts are all Level Sensitive, and Positive Polarity */
71static u8 gp3_openpic_initsenses[] __initdata = {
Kumar Gala65145e02005-06-21 17:15:25 -070072 MPC85XX_INTERNAL_IRQ_SENSES,
Linus Torvalds1da177e2005-04-16 15:20:36 -070073 0x0, /* External 0: */
74#if defined(CONFIG_PCI)
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI slot 0 */
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI slot 1 */
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI slot 2 */
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 4: PCI slot 3 */
79#else
80 0x0, /* External 1: */
81 0x0, /* External 2: */
82 0x0, /* External 3: */
83 0x0, /* External 4: */
84#endif
85 0x0, /* External 5: */
86 0x0, /* External 6: */
87 0x0, /* External 7: */
88 0x0, /* External 8: */
89 0x0, /* External 9: */
90 0x0, /* External 10: */
91 0x0, /* External 11: */
92};
93
94/*
95 * Setup the architecture
96 */
97static void __init
98gp3_setup_arch(void)
99{
100 bd_t *binfo = (bd_t *) __res;
101 unsigned int freq;
102 struct gianfar_platform_data *pdata;
Andy Flemingb37665e2005-10-28 17:46:27 -0700103 struct gianfar_mdio_data *mdata;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104
105 cpm2_reset();
106
107 /* get the core frequency */
108 freq = binfo->bi_intfreq;
109
110 if (ppc_md.progress)
111 ppc_md.progress("gp3_setup_arch()", 0);
112
113 /* Set loops_per_jiffy to a half-way reasonable value,
114 for use until calibrate_delay gets called. */
115 loops_per_jiffy = freq / HZ;
116
117#ifdef CONFIG_PCI
118 /* setup PCI host bridges */
119 mpc85xx_setup_hose();
120#endif
121
Andy Flemingb37665e2005-10-28 17:46:27 -0700122 /* setup the board related info for the MDIO bus */
123 mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
124
125 mdata->irq[2] = MPC85xx_IRQ_EXT5;
126 mdata->irq[4] = MPC85xx_IRQ_EXT5;
127 mdata->irq[31] = -1;
Andy Flemingb37665e2005-10-28 17:46:27 -0700128
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129 /* setup the board related information for the enet controllers */
130 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
Kumar Gala62aa7512005-06-25 14:54:36 -0700131 if (pdata) {
132 /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
Kumar Gala7e78e5e2006-01-12 21:04:23 -0600133 pdata->bus_id = 0;
134 pdata->phy_id = 2;
Kumar Gala62aa7512005-06-25 14:54:36 -0700135 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
136 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137
138 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
Kumar Gala62aa7512005-06-25 14:54:36 -0700139 if (pdata) {
140 /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
Kumar Gala7e78e5e2006-01-12 21:04:23 -0600141 pdata->bus_id = 0;
142 pdata->phy_id = 4;
Kumar Gala62aa7512005-06-25 14:54:36 -0700143 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
144 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700145
146#ifdef CONFIG_BLK_DEV_INITRD
147 if (initrd_start)
148 ROOT_DEV = Root_RAM0;
149 else
150#endif
151#ifdef CONFIG_ROOT_NFS
152 ROOT_DEV = Root_NFS;
153#else
154 ROOT_DEV = Root_HDA1;
155#endif
156
157 printk ("bi_immr_base = %8.8lx\n", binfo->bi_immr_base);
158}
159
160static irqreturn_t cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
161{
162 while ((irq = cpm2_get_irq(regs)) >= 0)
163 __do_IRQ(irq, regs);
164
165 return IRQ_HANDLED;
166}
167
168static struct irqaction cpm2_irqaction = {
169 .handler = cpm2_cascade,
170 .flags = SA_INTERRUPT,
171 .mask = CPU_MASK_NONE,
172 .name = "cpm2_cascade",
173};
174
175static void __init
176gp3_init_IRQ(void)
177{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700178 bd_t *binfo = (bd_t *) __res;
179
180 /*
181 * Setup OpenPIC
182 */
183
184 /* Determine the Physical Address of the OpenPIC regs */
185 phys_addr_t OpenPIC_PAddr =
186 binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
187 OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
188 OpenPIC_InitSenses = gp3_openpic_initsenses;
189 OpenPIC_NumInitSenses = sizeof (gp3_openpic_initsenses);
190
191 /* Skip reserved space and internal sources */
192 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
193
194 /* Map PIC IRQs 0-11 */
Kumar Gala65145e02005-06-21 17:15:25 -0700195 openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196
197 /*
198 * Let openpic interrupts starting from an offset, to
199 * leave space for cascading interrupts underneath.
200 */
201 openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
202
203 /* Setup CPM2 PIC */
204 cpm2_init_IRQ();
205
206 setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
207
208 return;
209}
210
211static int
212gp3_show_cpuinfo(struct seq_file *m)
213{
214 uint pvid, svid, phid1;
215 bd_t *binfo = (bd_t *) __res;
216 uint memsize;
217 unsigned int freq;
218 extern unsigned long total_memory; /* in mm/init */
219
220 /* get the core frequency */
221 freq = binfo->bi_intfreq;
222
223 pvid = mfspr(SPRN_PVR);
224 svid = mfspr(SPRN_SVR);
225
226 memsize = total_memory;
227
228 seq_printf(m, "Vendor\t\t: RPC Electronics STx \n");
229 seq_printf(m, "Machine\t\t: GP3 - MPC%s\n", cur_ppc_sys_spec->ppc_sys_name);
230 seq_printf(m, "bus freq\t: %u.%.6u MHz\n", freq / 1000000,
231 freq % 1000000);
232 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
233 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
234
235 /* Display cpu Pll setting */
236 phid1 = mfspr(SPRN_HID1);
237 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
238
239 /* Display the amount of memory */
240 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
241
242 return 0;
243}
244
245#ifdef CONFIG_PCI
246int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel,
247 unsigned char pin)
248{
249 static char pci_irq_table[][4] =
250 /*
251 * PCI IDSEL/INTPIN->INTLINE
252 * A B C D
253 */
254 {
255 {PIRQA, PIRQB, PIRQC, PIRQD},
256 {PIRQD, PIRQA, PIRQB, PIRQC},
257 {PIRQC, PIRQD, PIRQA, PIRQB},
258 {PIRQB, PIRQC, PIRQD, PIRQA},
259 };
260
261 const long min_idsel = 12, max_idsel = 15, irqs_per_slot = 4;
262 return PCI_IRQ_TABLE_LOOKUP;
263}
264
265int mpc85xx_exclude_device(u_char bus, u_char devfn)
266{
267 if (bus == 0 && PCI_SLOT(devfn) == 0)
268 return PCIBIOS_DEVICE_NOT_FOUND;
269 else
270 return PCIBIOS_SUCCESSFUL;
271}
272#endif /* CONFIG_PCI */
273
Matt Porter2b0c28d7f2005-11-07 01:00:19 -0800274#ifdef CONFIG_RAPIDIO
275void
276platform_rio_init(void)
277{
278 /*
279 * The STx firmware configures the RapidIO Local Access Window
280 * at 0xc0000000 with a size of 512MB.
281 */
282 mpc85xx_rio_setup(0xc0000000, 0x20000000);
283}
284#endif /* CONFIG_RAPIDIO */
285
Linus Torvalds1da177e2005-04-16 15:20:36 -0700286void __init
287platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
288 unsigned long r6, unsigned long r7)
289{
290 /* parse_bootinfo must always be called first */
291 parse_bootinfo(find_bootinfo());
292
293 /*
294 * If we were passed in a board information, copy it into the
295 * residual data area.
296 */
297 if (r3) {
298 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
299 sizeof (bd_t));
300
301 }
302#if defined(CONFIG_BLK_DEV_INITRD)
303 /*
304 * If the init RAM disk has been configured in, and there's a valid
305 * starting address for it, set it up.
306 */
307 if (r4) {
308 initrd_start = r4 + KERNELBASE;
309 initrd_end = r5 + KERNELBASE;
310 }
311#endif /* CONFIG_BLK_DEV_INITRD */
312
313 /* Copy the kernel command line arguments to a safe place. */
314
315 if (r6) {
316 *(char *) (r7 + KERNELBASE) = 0;
317 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
318 }
319
320 identify_ppc_sys_by_id(mfspr(SPRN_SVR));
321
322 /* setup the PowerPC module struct */
323 ppc_md.setup_arch = gp3_setup_arch;
324 ppc_md.show_cpuinfo = gp3_show_cpuinfo;
325
326 ppc_md.init_IRQ = gp3_init_IRQ;
327 ppc_md.get_irq = openpic_get_irq;
328
329 ppc_md.restart = mpc85xx_restart;
330 ppc_md.power_off = mpc85xx_power_off;
331 ppc_md.halt = mpc85xx_halt;
332
333 ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
334
335 ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
336
337 if (ppc_md.progress)
338 ppc_md.progress("platform_init(): exit", 0);
339
340 return;
341}