Ping-Ke Shih | a1b7163 | 2022-09-27 14:26:04 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause |
| 2 | /* Copyright(c) 2019-2022 Realtek Corporation |
| 3 | */ |
| 4 | |
Ping-Ke Shih | 08484e1 | 2022-09-28 16:43:33 +0800 | [diff] [blame] | 5 | #include "coex.h" |
| 6 | #include "fw.h" |
Ping-Ke Shih | 14b6e9f | 2022-09-27 14:26:06 +0800 | [diff] [blame] | 7 | #include "mac.h" |
Ping-Ke Shih | 08484e1 | 2022-09-28 16:43:33 +0800 | [diff] [blame] | 8 | #include "phy.h" |
Ping-Ke Shih | 14b6e9f | 2022-09-27 14:26:06 +0800 | [diff] [blame] | 9 | #include "reg.h" |
Ping-Ke Shih | 08484e1 | 2022-09-28 16:43:33 +0800 | [diff] [blame] | 10 | #include "rtw8852b.h" |
Ping-Ke Shih | 6b06989 | 2022-10-05 16:32:12 +0800 | [diff] [blame] | 11 | #include "rtw8852b_rfk.h" |
Ping-Ke Shih | 08484e1 | 2022-09-28 16:43:33 +0800 | [diff] [blame] | 12 | #include "rtw8852b_table.h" |
| 13 | #include "txrx.h" |
Ping-Ke Shih | 14b6e9f | 2022-09-27 14:26:06 +0800 | [diff] [blame] | 14 | |
Ping-Ke Shih | ffde7f3 | 2023-03-20 21:06:06 +0800 | [diff] [blame] | 15 | #define RTW8852B_FW_FORMAT_MAX 1 |
| 16 | #define RTW8852B_FW_BASENAME "rtw89/rtw8852b_fw" |
| 17 | #define RTW8852B_MODULE_FIRMWARE \ |
| 18 | RTW8852B_FW_BASENAME "-" __stringify(RTW8852B_FW_FORMAT_MAX) ".bin" |
| 19 | |
Ping-Ke Shih | 3e870b4 | 2022-10-05 16:32:10 +0800 | [diff] [blame] | 20 | static const struct rtw89_hfc_ch_cfg rtw8852b_hfc_chcfg_pcie[] = { |
Ping-Ke Shih | c0426c4 | 2023-04-26 11:47:37 +0800 | [diff] [blame] | 21 | {5, 341, grp_0}, /* ACH 0 */ |
| 22 | {5, 341, grp_0}, /* ACH 1 */ |
| 23 | {4, 342, grp_0}, /* ACH 2 */ |
| 24 | {4, 342, grp_0}, /* ACH 3 */ |
Ping-Ke Shih | 3e870b4 | 2022-10-05 16:32:10 +0800 | [diff] [blame] | 25 | {0, 0, grp_0}, /* ACH 4 */ |
| 26 | {0, 0, grp_0}, /* ACH 5 */ |
| 27 | {0, 0, grp_0}, /* ACH 6 */ |
| 28 | {0, 0, grp_0}, /* ACH 7 */ |
Ping-Ke Shih | c0426c4 | 2023-04-26 11:47:37 +0800 | [diff] [blame] | 29 | {4, 342, grp_0}, /* B0MGQ */ |
| 30 | {4, 342, grp_0}, /* B0HIQ */ |
Ping-Ke Shih | 3e870b4 | 2022-10-05 16:32:10 +0800 | [diff] [blame] | 31 | {0, 0, grp_0}, /* B1MGQ */ |
| 32 | {0, 0, grp_0}, /* B1HIQ */ |
| 33 | {40, 0, 0} /* FWCMDQ */ |
| 34 | }; |
| 35 | |
| 36 | static const struct rtw89_hfc_pub_cfg rtw8852b_hfc_pubcfg_pcie = { |
Ping-Ke Shih | c0426c4 | 2023-04-26 11:47:37 +0800 | [diff] [blame] | 37 | 446, /* Group 0 */ |
Ping-Ke Shih | 3e870b4 | 2022-10-05 16:32:10 +0800 | [diff] [blame] | 38 | 0, /* Group 1 */ |
Ping-Ke Shih | c0426c4 | 2023-04-26 11:47:37 +0800 | [diff] [blame] | 39 | 446, /* Public Max */ |
Ping-Ke Shih | 3e870b4 | 2022-10-05 16:32:10 +0800 | [diff] [blame] | 40 | 0 /* WP threshold */ |
| 41 | }; |
| 42 | |
| 43 | static const struct rtw89_hfc_param_ini rtw8852b_hfc_param_ini_pcie[] = { |
| 44 | [RTW89_QTA_SCC] = {rtw8852b_hfc_chcfg_pcie, &rtw8852b_hfc_pubcfg_pcie, |
| 45 | &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, |
| 46 | [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, |
| 47 | RTW89_HCIFC_POH}, |
| 48 | [RTW89_QTA_INVALID] = {NULL}, |
| 49 | }; |
| 50 | |
Ping-Ke Shih | a1cb097 | 2022-09-27 14:26:11 +0800 | [diff] [blame] | 51 | static const struct rtw89_dle_mem rtw8852b_dle_mem_pcie[] = { |
Ping-Ke Shih | c0426c4 | 2023-04-26 11:47:37 +0800 | [diff] [blame] | 52 | [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size7, |
| 53 | &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt7, |
| 54 | &rtw89_mac_size.wde_qt7, &rtw89_mac_size.ple_qt18, |
Ping-Ke Shih | a1cb097 | 2022-09-27 14:26:11 +0800 | [diff] [blame] | 55 | &rtw89_mac_size.ple_qt58}, |
Ping-Ke Shih | c0426c4 | 2023-04-26 11:47:37 +0800 | [diff] [blame] | 56 | [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size7, |
| 57 | &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt7, |
| 58 | &rtw89_mac_size.wde_qt7, &rtw89_mac_size.ple_qt18, |
Chin-Yen Lee | 6863ad9 | 2023-04-10 13:34:37 +0800 | [diff] [blame] | 59 | &rtw89_mac_size.ple_qt_52b_wow}, |
Ping-Ke Shih | a1cb097 | 2022-09-27 14:26:11 +0800 | [diff] [blame] | 60 | [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9, |
| 61 | &rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4, |
| 62 | &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13, |
| 63 | &rtw89_mac_size.ple_qt13}, |
| 64 | [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, |
| 65 | NULL}, |
| 66 | }; |
| 67 | |
Ping-Ke Shih | 572fd2a | 2022-10-09 20:54:02 +0800 | [diff] [blame] | 68 | static const struct rtw89_reg3_def rtw8852b_pmac_ht20_mcs7_tbl[] = { |
| 69 | {0x4580, 0x0000ffff, 0x0}, |
| 70 | {0x4580, 0xffff0000, 0x0}, |
| 71 | {0x4584, 0x0000ffff, 0x0}, |
| 72 | {0x4584, 0xffff0000, 0x0}, |
| 73 | {0x4580, 0x0000ffff, 0x1}, |
| 74 | {0x4578, 0x00ffffff, 0x2018b}, |
| 75 | {0x4570, 0x03ffffff, 0x7}, |
| 76 | {0x4574, 0x03ffffff, 0x32407}, |
| 77 | {0x45b8, 0x00000010, 0x0}, |
| 78 | {0x45b8, 0x00000100, 0x0}, |
| 79 | {0x45b8, 0x00000080, 0x0}, |
| 80 | {0x45b8, 0x00000008, 0x0}, |
| 81 | {0x45a0, 0x0000ff00, 0x0}, |
| 82 | {0x45a0, 0xff000000, 0x1}, |
| 83 | {0x45a4, 0x0000ff00, 0x2}, |
| 84 | {0x45a4, 0xff000000, 0x3}, |
| 85 | {0x45b8, 0x00000020, 0x0}, |
| 86 | {0x4568, 0xe0000000, 0x0}, |
| 87 | {0x45b8, 0x00000002, 0x1}, |
| 88 | {0x456c, 0xe0000000, 0x0}, |
| 89 | {0x45b4, 0x00006000, 0x0}, |
| 90 | {0x45b4, 0x00001800, 0x1}, |
| 91 | {0x45b8, 0x00000040, 0x0}, |
| 92 | {0x45b8, 0x00000004, 0x0}, |
| 93 | {0x45b8, 0x00000200, 0x0}, |
| 94 | {0x4598, 0xf8000000, 0x0}, |
| 95 | {0x45b8, 0x00100000, 0x0}, |
| 96 | {0x45a8, 0x00000fc0, 0x0}, |
| 97 | {0x45b8, 0x00200000, 0x0}, |
| 98 | {0x45b0, 0x00000038, 0x0}, |
| 99 | {0x45b0, 0x000001c0, 0x0}, |
| 100 | {0x45a0, 0x000000ff, 0x0}, |
| 101 | {0x45b8, 0x00400000, 0x0}, |
| 102 | {0x4590, 0x000007ff, 0x0}, |
| 103 | {0x45b0, 0x00000e00, 0x0}, |
| 104 | {0x45ac, 0x0000001f, 0x0}, |
| 105 | {0x45b8, 0x00800000, 0x0}, |
| 106 | {0x45a8, 0x0003f000, 0x0}, |
| 107 | {0x45b8, 0x01000000, 0x0}, |
| 108 | {0x45b0, 0x00007000, 0x0}, |
| 109 | {0x45b0, 0x00038000, 0x0}, |
| 110 | {0x45a0, 0x00ff0000, 0x0}, |
| 111 | {0x45b8, 0x02000000, 0x0}, |
| 112 | {0x4590, 0x003ff800, 0x0}, |
| 113 | {0x45b0, 0x001c0000, 0x0}, |
| 114 | {0x45ac, 0x000003e0, 0x0}, |
| 115 | {0x45b8, 0x04000000, 0x0}, |
| 116 | {0x45a8, 0x00fc0000, 0x0}, |
| 117 | {0x45b8, 0x08000000, 0x0}, |
| 118 | {0x45b0, 0x00e00000, 0x0}, |
| 119 | {0x45b0, 0x07000000, 0x0}, |
| 120 | {0x45a4, 0x000000ff, 0x0}, |
| 121 | {0x45b8, 0x10000000, 0x0}, |
| 122 | {0x4594, 0x000007ff, 0x0}, |
| 123 | {0x45b0, 0x38000000, 0x0}, |
| 124 | {0x45ac, 0x00007c00, 0x0}, |
| 125 | {0x45b8, 0x20000000, 0x0}, |
| 126 | {0x45a8, 0x3f000000, 0x0}, |
| 127 | {0x45b8, 0x40000000, 0x0}, |
| 128 | {0x45b4, 0x00000007, 0x0}, |
| 129 | {0x45b4, 0x00000038, 0x0}, |
| 130 | {0x45a4, 0x00ff0000, 0x0}, |
| 131 | {0x45b8, 0x80000000, 0x0}, |
| 132 | {0x4594, 0x003ff800, 0x0}, |
| 133 | {0x45b4, 0x000001c0, 0x0}, |
| 134 | {0x4598, 0xf8000000, 0x0}, |
| 135 | {0x45b8, 0x00100000, 0x0}, |
| 136 | {0x45a8, 0x00000fc0, 0x7}, |
| 137 | {0x45b8, 0x00200000, 0x0}, |
| 138 | {0x45b0, 0x00000038, 0x0}, |
| 139 | {0x45b0, 0x000001c0, 0x0}, |
| 140 | {0x45a0, 0x000000ff, 0x0}, |
| 141 | {0x45b4, 0x06000000, 0x0}, |
| 142 | {0x45b0, 0x00000007, 0x0}, |
| 143 | {0x45b8, 0x00080000, 0x0}, |
| 144 | {0x45a8, 0x0000003f, 0x0}, |
| 145 | {0x457c, 0xffe00000, 0x1}, |
| 146 | {0x4530, 0xffffffff, 0x0}, |
| 147 | {0x4588, 0x00003fff, 0x0}, |
| 148 | {0x4598, 0x000001ff, 0x0}, |
| 149 | {0x4534, 0xffffffff, 0x0}, |
| 150 | {0x4538, 0xffffffff, 0x0}, |
| 151 | {0x453c, 0xffffffff, 0x0}, |
| 152 | {0x4588, 0x0fffc000, 0x0}, |
| 153 | {0x4598, 0x0003fe00, 0x0}, |
| 154 | {0x4540, 0xffffffff, 0x0}, |
| 155 | {0x4544, 0xffffffff, 0x0}, |
| 156 | {0x4548, 0xffffffff, 0x0}, |
| 157 | {0x458c, 0x00003fff, 0x0}, |
| 158 | {0x4598, 0x07fc0000, 0x0}, |
| 159 | {0x454c, 0xffffffff, 0x0}, |
| 160 | {0x4550, 0xffffffff, 0x0}, |
| 161 | {0x4554, 0xffffffff, 0x0}, |
| 162 | {0x458c, 0x0fffc000, 0x0}, |
| 163 | {0x459c, 0x000001ff, 0x0}, |
| 164 | {0x4558, 0xffffffff, 0x0}, |
| 165 | {0x455c, 0xffffffff, 0x0}, |
| 166 | {0x4530, 0xffffffff, 0x4e790001}, |
| 167 | {0x4588, 0x00003fff, 0x0}, |
| 168 | {0x4598, 0x000001ff, 0x1}, |
| 169 | {0x4534, 0xffffffff, 0x0}, |
| 170 | {0x4538, 0xffffffff, 0x4b}, |
| 171 | {0x45ac, 0x38000000, 0x7}, |
| 172 | {0x4588, 0xf0000000, 0x0}, |
| 173 | {0x459c, 0x7e000000, 0x0}, |
| 174 | {0x45b8, 0x00040000, 0x0}, |
| 175 | {0x45b8, 0x00020000, 0x0}, |
| 176 | {0x4590, 0xffc00000, 0x0}, |
| 177 | {0x45b8, 0x00004000, 0x0}, |
| 178 | {0x4578, 0xff000000, 0x0}, |
| 179 | {0x45b8, 0x00000400, 0x0}, |
| 180 | {0x45b8, 0x00000800, 0x0}, |
| 181 | {0x45b8, 0x00001000, 0x0}, |
| 182 | {0x45b8, 0x00002000, 0x0}, |
| 183 | {0x45b4, 0x00018000, 0x0}, |
| 184 | {0x45ac, 0x07800000, 0x0}, |
| 185 | {0x45b4, 0x00000600, 0x2}, |
| 186 | {0x459c, 0x0001fe00, 0x80}, |
| 187 | {0x45ac, 0x00078000, 0x3}, |
| 188 | {0x459c, 0x01fe0000, 0x1}, |
| 189 | }; |
| 190 | |
Ping-Ke Shih | 98bf0dd | 2022-10-09 20:53:59 +0800 | [diff] [blame] | 191 | static const struct rtw89_reg3_def rtw8852b_btc_preagc_en_defs[] = { |
| 192 | {0x46D0, GENMASK(1, 0), 0x3}, |
| 193 | {0x4790, GENMASK(1, 0), 0x3}, |
| 194 | {0x4AD4, GENMASK(31, 0), 0xf}, |
| 195 | {0x4AE0, GENMASK(31, 0), 0xf}, |
| 196 | {0x4688, GENMASK(31, 24), 0x80}, |
| 197 | {0x476C, GENMASK(31, 24), 0x80}, |
| 198 | {0x4694, GENMASK(7, 0), 0x80}, |
| 199 | {0x4694, GENMASK(15, 8), 0x80}, |
| 200 | {0x4778, GENMASK(7, 0), 0x80}, |
| 201 | {0x4778, GENMASK(15, 8), 0x80}, |
| 202 | {0x4AE4, GENMASK(23, 0), 0x780D1E}, |
| 203 | {0x4AEC, GENMASK(23, 0), 0x780D1E}, |
| 204 | {0x469C, GENMASK(31, 26), 0x34}, |
| 205 | {0x49F0, GENMASK(31, 26), 0x34}, |
| 206 | }; |
| 207 | |
| 208 | static DECLARE_PHY_REG3_TBL(rtw8852b_btc_preagc_en_defs); |
| 209 | |
| 210 | static const struct rtw89_reg3_def rtw8852b_btc_preagc_dis_defs[] = { |
| 211 | {0x46D0, GENMASK(1, 0), 0x0}, |
| 212 | {0x4790, GENMASK(1, 0), 0x0}, |
| 213 | {0x4AD4, GENMASK(31, 0), 0x60}, |
| 214 | {0x4AE0, GENMASK(31, 0), 0x60}, |
| 215 | {0x4688, GENMASK(31, 24), 0x1a}, |
| 216 | {0x476C, GENMASK(31, 24), 0x1a}, |
| 217 | {0x4694, GENMASK(7, 0), 0x2a}, |
| 218 | {0x4694, GENMASK(15, 8), 0x2a}, |
| 219 | {0x4778, GENMASK(7, 0), 0x2a}, |
| 220 | {0x4778, GENMASK(15, 8), 0x2a}, |
| 221 | {0x4AE4, GENMASK(23, 0), 0x79E99E}, |
| 222 | {0x4AEC, GENMASK(23, 0), 0x79E99E}, |
| 223 | {0x469C, GENMASK(31, 26), 0x26}, |
| 224 | {0x49F0, GENMASK(31, 26), 0x26}, |
| 225 | }; |
| 226 | |
| 227 | static DECLARE_PHY_REG3_TBL(rtw8852b_btc_preagc_dis_defs); |
| 228 | |
Ping-Ke Shih | b8fe87b | 2022-10-09 20:54:03 +0800 | [diff] [blame] | 229 | static const u32 rtw8852b_h2c_regs[RTW89_H2CREG_MAX] = { |
| 230 | R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2, |
| 231 | R_AX_H2CREG_DATA3 |
| 232 | }; |
| 233 | |
| 234 | static const u32 rtw8852b_c2h_regs[RTW89_C2HREG_MAX] = { |
| 235 | R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2, |
| 236 | R_AX_C2HREG_DATA3 |
| 237 | }; |
| 238 | |
| 239 | static const struct rtw89_page_regs rtw8852b_page_regs = { |
| 240 | .hci_fc_ctrl = R_AX_HCI_FC_CTRL, |
| 241 | .ch_page_ctrl = R_AX_CH_PAGE_CTRL, |
| 242 | .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL, |
| 243 | .ach_page_info = R_AX_ACH0_PAGE_INFO, |
| 244 | .pub_page_info3 = R_AX_PUB_PAGE_INFO3, |
| 245 | .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1, |
| 246 | .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2, |
| 247 | .pub_page_info1 = R_AX_PUB_PAGE_INFO1, |
| 248 | .pub_page_info2 = R_AX_PUB_PAGE_INFO2, |
| 249 | .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1, |
| 250 | .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2, |
| 251 | .wp_page_info1 = R_AX_WP_PAGE_INFO1, |
| 252 | }; |
| 253 | |
| 254 | static const struct rtw89_reg_def rtw8852b_dcfo_comp = { |
| 255 | R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK |
| 256 | }; |
| 257 | |
| 258 | static const struct rtw89_imr_info rtw8852b_imr_info = { |
| 259 | .wdrls_imr_set = B_AX_WDRLS_IMR_SET, |
| 260 | .wsec_imr_reg = R_AX_SEC_DEBUG, |
| 261 | .wsec_imr_set = B_AX_IMR_ERROR, |
| 262 | .mpdu_tx_imr_set = 0, |
| 263 | .mpdu_rx_imr_set = 0, |
| 264 | .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, |
| 265 | .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR, |
| 266 | .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR, |
| 267 | .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET, |
| 268 | .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1, |
| 269 | .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR, |
| 270 | .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET, |
| 271 | .wde_imr_clr = B_AX_WDE_IMR_CLR, |
| 272 | .wde_imr_set = B_AX_WDE_IMR_SET, |
| 273 | .ple_imr_clr = B_AX_PLE_IMR_CLR, |
| 274 | .ple_imr_set = B_AX_PLE_IMR_SET, |
| 275 | .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR, |
| 276 | .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET, |
| 277 | .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR, |
| 278 | .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET, |
| 279 | .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR, |
| 280 | .other_disp_imr_set = 0, |
| 281 | .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR, |
| 282 | .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR, |
| 283 | .bbrpt_err_imr_set = 0, |
| 284 | .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR, |
| 285 | .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_ALL, |
| 286 | .ptcl_imr_set = B_AX_PTCL_IMR_SET, |
| 287 | .cdma_imr_0_reg = R_AX_DLE_CTRL, |
| 288 | .cdma_imr_0_clr = B_AX_DLE_IMR_CLR, |
| 289 | .cdma_imr_0_set = B_AX_DLE_IMR_SET, |
| 290 | .cdma_imr_1_reg = 0, |
| 291 | .cdma_imr_1_clr = 0, |
| 292 | .cdma_imr_1_set = 0, |
| 293 | .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR, |
| 294 | .phy_intf_imr_clr = 0, |
| 295 | .phy_intf_imr_set = 0, |
| 296 | .rmac_imr_reg = R_AX_RMAC_ERR_ISR, |
| 297 | .rmac_imr_clr = B_AX_RMAC_IMR_CLR, |
| 298 | .rmac_imr_set = B_AX_RMAC_IMR_SET, |
| 299 | .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR, |
| 300 | .tmac_imr_clr = B_AX_TMAC_IMR_CLR, |
| 301 | .tmac_imr_set = B_AX_TMAC_IMR_SET, |
| 302 | }; |
| 303 | |
| 304 | static const struct rtw89_rrsr_cfgs rtw8852b_rrsr_cfgs = { |
| 305 | .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, |
| 306 | .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2}, |
| 307 | }; |
| 308 | |
| 309 | static const struct rtw89_dig_regs rtw8852b_dig_regs = { |
| 310 | .seg0_pd_reg = R_SEG0R_PD_V1, |
| 311 | .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, |
| 312 | .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1, |
| 313 | .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK}, |
| 314 | .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK}, |
| 315 | .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1}, |
| 316 | .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1}, |
| 317 | .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1}, |
| 318 | .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1}, |
| 319 | .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2, |
| 320 | B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, |
| 321 | .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2, |
| 322 | B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, |
| 323 | .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2, |
| 324 | B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, |
| 325 | .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2, |
| 326 | B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, |
| 327 | }; |
| 328 | |
| 329 | static const struct rtw89_btc_rf_trx_para rtw89_btc_8852b_rf_ul[] = { |
Ping-Ke Shih | 79ca91a | 2022-11-17 14:18:32 +0800 | [diff] [blame] | 330 | {255, 0, 0, 7}, /* 0 -> original */ |
| 331 | {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ |
| 332 | {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ |
| 333 | {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ |
| 334 | {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ |
Ching-Te Ku | 36ef71d | 2023-04-12 09:28:28 +0800 | [diff] [blame] | 335 | {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ |
Ping-Ke Shih | b8fe87b | 2022-10-09 20:54:03 +0800 | [diff] [blame] | 336 | {6, 1, 0, 7}, |
| 337 | {13, 1, 0, 7}, |
| 338 | {13, 1, 0, 7} |
| 339 | }; |
| 340 | |
| 341 | static const struct rtw89_btc_rf_trx_para rtw89_btc_8852b_rf_dl[] = { |
Ping-Ke Shih | 79ca91a | 2022-11-17 14:18:32 +0800 | [diff] [blame] | 342 | {255, 0, 0, 7}, /* 0 -> original */ |
| 343 | {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ |
| 344 | {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ |
| 345 | {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ |
| 346 | {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ |
Ching-Te Ku | 36ef71d | 2023-04-12 09:28:28 +0800 | [diff] [blame] | 347 | {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ |
Ping-Ke Shih | 79ca91a | 2022-11-17 14:18:32 +0800 | [diff] [blame] | 348 | {255, 1, 0, 7}, |
| 349 | {255, 1, 0, 7}, |
| 350 | {255, 1, 0, 7} |
Ping-Ke Shih | b8fe87b | 2022-10-09 20:54:03 +0800 | [diff] [blame] | 351 | }; |
| 352 | |
| 353 | static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852b_mon_reg[] = { |
| 354 | RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), |
| 355 | RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28), |
| 356 | RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c), |
| 357 | RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), |
| 358 | RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), |
| 359 | RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10), |
| 360 | RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20), |
| 361 | RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), |
| 362 | RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4), |
| 363 | RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424), |
| 364 | RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200), |
| 365 | RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220), |
| 366 | RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), |
Ching-Te Ku | 9fde305 | 2023-04-12 09:28:29 +0800 | [diff] [blame] | 367 | RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4738), |
| 368 | RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4688), |
| 369 | RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4694), |
Ping-Ke Shih | b8fe87b | 2022-10-09 20:54:03 +0800 | [diff] [blame] | 370 | }; |
| 371 | |
| 372 | static const u8 rtw89_btc_8852b_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {70, 60, 50, 40}; |
| 373 | static const u8 rtw89_btc_8852b_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20}; |
| 374 | |
Ping-Ke Shih | b23b36e | 2022-10-09 20:53:56 +0800 | [diff] [blame] | 375 | static int rtw8852b_pwr_on_func(struct rtw89_dev *rtwdev) |
| 376 | { |
| 377 | u32 val32; |
| 378 | u32 ret; |
| 379 | |
| 380 | rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN | |
| 381 | B_AX_AFSM_PCIE_SUS_EN); |
| 382 | rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC); |
| 383 | rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC); |
| 384 | rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN); |
| 385 | rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); |
| 386 | |
| 387 | ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR, |
| 388 | 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); |
| 389 | if (ret) |
| 390 | return ret; |
| 391 | |
| 392 | rtw89_write32_set(rtwdev, R_AX_AFE_LDO_CTRL, B_AX_AON_OFF_PC_EN); |
| 393 | ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_AON_OFF_PC_EN, |
| 394 | 1000, 20000, false, rtwdev, R_AX_AFE_LDO_CTRL); |
| 395 | if (ret) |
| 396 | return ret; |
| 397 | |
| 398 | rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C1_L1_MASK, 0x1); |
| 399 | rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C3_L1_MASK, 0x3); |
| 400 | rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); |
| 401 | rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); |
| 402 | |
| 403 | ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC), |
| 404 | 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); |
| 405 | if (ret) |
| 406 | return ret; |
| 407 | |
| 408 | rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); |
| 409 | rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); |
| 410 | rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); |
| 411 | rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); |
| 412 | |
| 413 | rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); |
| 414 | rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1); |
| 415 | |
| 416 | rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); |
| 417 | |
| 418 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, |
| 419 | XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL); |
| 420 | if (ret) |
| 421 | return ret; |
| 422 | |
| 423 | rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); |
| 424 | |
| 425 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, |
| 426 | XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL); |
| 427 | if (ret) |
| 428 | return ret; |
| 429 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI, |
| 430 | XTAL_SI_OFF_WEI); |
| 431 | if (ret) |
| 432 | return ret; |
| 433 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI, |
| 434 | XTAL_SI_OFF_EI); |
| 435 | if (ret) |
| 436 | return ret; |
| 437 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF); |
| 438 | if (ret) |
| 439 | return ret; |
| 440 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI, |
| 441 | XTAL_SI_PON_WEI); |
| 442 | if (ret) |
| 443 | return ret; |
| 444 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI, |
| 445 | XTAL_SI_PON_EI); |
| 446 | if (ret) |
| 447 | return ret; |
| 448 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC); |
| 449 | if (ret) |
| 450 | return ret; |
| 451 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS); |
| 452 | if (ret) |
| 453 | return ret; |
| 454 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS); |
| 455 | if (ret) |
| 456 | return ret; |
| 457 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP); |
| 458 | if (ret) |
| 459 | return ret; |
| 460 | |
| 461 | rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); |
| 462 | rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE); |
| 463 | rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15); |
| 464 | |
| 465 | fsleep(1000); |
| 466 | |
| 467 | rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14); |
| 468 | rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); |
| 469 | |
| 470 | if (!rtwdev->efuse.valid || rtwdev->efuse.power_k_valid) |
| 471 | goto func_en; |
| 472 | |
| 473 | rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VOL_L1_MASK, 0x9); |
| 474 | rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VREFPFM_L_MASK, 0xA); |
| 475 | |
| 476 | if (rtwdev->hal.cv == CHIP_CBV) { |
| 477 | rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); |
| 478 | rtw89_write16_mask(rtwdev, R_AX_HCI_LDO_CTRL, B_AX_R_AX_VADJ_MASK, 0xA); |
| 479 | rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); |
| 480 | } |
| 481 | |
| 482 | func_en: |
| 483 | rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, |
| 484 | B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN | |
| 485 | B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN | |
| 486 | B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN | |
| 487 | B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN | |
| 488 | B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN | |
| 489 | B_AX_DMACREG_GCKEN); |
| 490 | rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN, |
| 491 | B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | |
| 492 | B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | |
| 493 | B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | B_AX_TMAC_EN | |
| 494 | B_AX_RMAC_EN); |
| 495 | |
| 496 | rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK, |
| 497 | PINMUX_EESK_FUNC_SEL_BT_LOG); |
| 498 | |
| 499 | return 0; |
| 500 | } |
| 501 | |
| 502 | static int rtw8852b_pwr_off_func(struct rtw89_dev *rtwdev) |
| 503 | { |
| 504 | u32 val32; |
| 505 | u32 ret; |
| 506 | |
| 507 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF, |
| 508 | XTAL_SI_RFC2RF); |
| 509 | if (ret) |
| 510 | return ret; |
| 511 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI); |
| 512 | if (ret) |
| 513 | return ret; |
| 514 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI); |
| 515 | if (ret) |
| 516 | return ret; |
| 517 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00); |
| 518 | if (ret) |
| 519 | return ret; |
| 520 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10); |
| 521 | if (ret) |
| 522 | return ret; |
| 523 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC, |
| 524 | XTAL_SI_SRAM2RFC); |
| 525 | if (ret) |
| 526 | return ret; |
| 527 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI); |
| 528 | if (ret) |
| 529 | return ret; |
| 530 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI); |
| 531 | if (ret) |
| 532 | return ret; |
| 533 | |
| 534 | rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); |
| 535 | rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB); |
| 536 | rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); |
| 537 | |
| 538 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL); |
| 539 | if (ret) |
| 540 | return ret; |
| 541 | |
| 542 | rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); |
| 543 | |
| 544 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL); |
| 545 | if (ret) |
| 546 | return ret; |
| 547 | |
| 548 | rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC); |
| 549 | |
| 550 | ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC), |
| 551 | 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); |
| 552 | if (ret) |
| 553 | return ret; |
| 554 | |
| 555 | rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION); |
| 556 | rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ); |
| 557 | rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x3); |
| 558 | rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); |
| 559 | |
| 560 | return 0; |
| 561 | } |
| 562 | |
Ping-Ke Shih | 132dc4f | 2022-09-28 16:43:34 +0800 | [diff] [blame] | 563 | static void rtw8852be_efuse_parsing(struct rtw89_efuse *efuse, |
| 564 | struct rtw8852b_efuse *map) |
| 565 | { |
| 566 | ether_addr_copy(efuse->addr, map->e.mac_addr); |
| 567 | efuse->rfe_type = map->rfe_type; |
| 568 | efuse->xtal_cap = map->xtal_k; |
| 569 | } |
| 570 | |
| 571 | static void rtw8852b_efuse_parsing_tssi(struct rtw89_dev *rtwdev, |
| 572 | struct rtw8852b_efuse *map) |
| 573 | { |
| 574 | struct rtw89_tssi_info *tssi = &rtwdev->tssi; |
| 575 | struct rtw8852b_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; |
| 576 | u8 i, j; |
| 577 | |
| 578 | tssi->thermal[RF_PATH_A] = map->path_a_therm; |
| 579 | tssi->thermal[RF_PATH_B] = map->path_b_therm; |
| 580 | |
| 581 | for (i = 0; i < RF_PATH_NUM_8852B; i++) { |
| 582 | memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, |
| 583 | sizeof(ofst[i]->cck_tssi)); |
| 584 | |
| 585 | for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) |
| 586 | rtw89_debug(rtwdev, RTW89_DBG_TSSI, |
| 587 | "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", |
| 588 | i, j, tssi->tssi_cck[i][j]); |
| 589 | |
| 590 | memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, |
| 591 | sizeof(ofst[i]->bw40_tssi)); |
| 592 | memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, |
| 593 | ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); |
| 594 | |
| 595 | for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) |
| 596 | rtw89_debug(rtwdev, RTW89_DBG_TSSI, |
| 597 | "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", |
| 598 | i, j, tssi->tssi_mcs[i][j]); |
| 599 | } |
| 600 | } |
| 601 | |
| 602 | static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low) |
| 603 | { |
| 604 | if (high) |
| 605 | *high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3); |
| 606 | if (low) |
| 607 | *low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3); |
| 608 | |
| 609 | return data != 0xff; |
| 610 | } |
| 611 | |
| 612 | static void rtw8852b_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev, |
| 613 | struct rtw8852b_efuse *map) |
| 614 | { |
| 615 | struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; |
| 616 | bool valid = false; |
| 617 | |
| 618 | valid |= _decode_efuse_gain(map->rx_gain_2g_cck, |
| 619 | &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK], |
| 620 | &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]); |
| 621 | valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm, |
| 622 | &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM], |
| 623 | &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]); |
| 624 | valid |= _decode_efuse_gain(map->rx_gain_5g_low, |
| 625 | &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW], |
| 626 | &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]); |
| 627 | valid |= _decode_efuse_gain(map->rx_gain_5g_mid, |
| 628 | &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID], |
| 629 | &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]); |
| 630 | valid |= _decode_efuse_gain(map->rx_gain_5g_high, |
| 631 | &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH], |
| 632 | &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]); |
| 633 | |
| 634 | gain->offset_valid = valid; |
| 635 | } |
| 636 | |
| 637 | static int rtw8852b_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map) |
| 638 | { |
| 639 | struct rtw89_efuse *efuse = &rtwdev->efuse; |
| 640 | struct rtw8852b_efuse *map; |
| 641 | |
| 642 | map = (struct rtw8852b_efuse *)log_map; |
| 643 | |
| 644 | efuse->country_code[0] = map->country_code[0]; |
| 645 | efuse->country_code[1] = map->country_code[1]; |
| 646 | rtw8852b_efuse_parsing_tssi(rtwdev, map); |
| 647 | rtw8852b_efuse_parsing_gain_offset(rtwdev, map); |
| 648 | |
| 649 | switch (rtwdev->hci.type) { |
| 650 | case RTW89_HCI_TYPE_PCIE: |
| 651 | rtw8852be_efuse_parsing(efuse, map); |
| 652 | break; |
| 653 | default: |
| 654 | return -EOPNOTSUPP; |
| 655 | } |
| 656 | |
| 657 | rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); |
| 658 | |
| 659 | return 0; |
| 660 | } |
| 661 | |
Ping-Ke Shih | 134cf7c | 2022-09-28 16:43:35 +0800 | [diff] [blame] | 662 | static void rtw8852b_phycap_parsing_power_cal(struct rtw89_dev *rtwdev, u8 *phycap_map) |
| 663 | { |
| 664 | #define PWR_K_CHK_OFFSET 0x5E9 |
| 665 | #define PWR_K_CHK_VALUE 0xAA |
| 666 | u32 offset = PWR_K_CHK_OFFSET - rtwdev->chip->phycap_addr; |
| 667 | |
| 668 | if (phycap_map[offset] == PWR_K_CHK_VALUE) |
| 669 | rtwdev->efuse.power_k_valid = true; |
| 670 | } |
| 671 | |
| 672 | static void rtw8852b_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) |
| 673 | { |
| 674 | struct rtw89_tssi_info *tssi = &rtwdev->tssi; |
| 675 | static const u32 tssi_trim_addr[RF_PATH_NUM_8852B] = {0x5D6, 0x5AB}; |
| 676 | u32 addr = rtwdev->chip->phycap_addr; |
| 677 | bool pg = false; |
| 678 | u32 ofst; |
| 679 | u8 i, j; |
| 680 | |
| 681 | for (i = 0; i < RF_PATH_NUM_8852B; i++) { |
| 682 | for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { |
| 683 | /* addrs are in decreasing order */ |
| 684 | ofst = tssi_trim_addr[i] - addr - j; |
| 685 | tssi->tssi_trim[i][j] = phycap_map[ofst]; |
| 686 | |
| 687 | if (phycap_map[ofst] != 0xff) |
| 688 | pg = true; |
| 689 | } |
| 690 | } |
| 691 | |
| 692 | if (!pg) { |
| 693 | memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); |
| 694 | rtw89_debug(rtwdev, RTW89_DBG_TSSI, |
| 695 | "[TSSI][TRIM] no PG, set all trim info to 0\n"); |
| 696 | } |
| 697 | |
| 698 | for (i = 0; i < RF_PATH_NUM_8852B; i++) |
| 699 | for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) |
| 700 | rtw89_debug(rtwdev, RTW89_DBG_TSSI, |
| 701 | "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", |
| 702 | i, j, tssi->tssi_trim[i][j], |
| 703 | tssi_trim_addr[i] - j); |
| 704 | } |
| 705 | |
| 706 | static void rtw8852b_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, |
| 707 | u8 *phycap_map) |
| 708 | { |
| 709 | struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; |
| 710 | static const u32 thm_trim_addr[RF_PATH_NUM_8852B] = {0x5DF, 0x5DC}; |
| 711 | u32 addr = rtwdev->chip->phycap_addr; |
| 712 | u8 i; |
| 713 | |
| 714 | for (i = 0; i < RF_PATH_NUM_8852B; i++) { |
| 715 | info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; |
| 716 | |
| 717 | rtw89_debug(rtwdev, RTW89_DBG_RFK, |
| 718 | "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", |
| 719 | i, info->thermal_trim[i]); |
| 720 | |
| 721 | if (info->thermal_trim[i] != 0xff) |
| 722 | info->pg_thermal_trim = true; |
| 723 | } |
| 724 | } |
| 725 | |
| 726 | static void rtw8852b_thermal_trim(struct rtw89_dev *rtwdev) |
| 727 | { |
| 728 | #define __thm_setting(raw) \ |
| 729 | ({ \ |
| 730 | u8 __v = (raw); \ |
| 731 | ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ |
| 732 | }) |
| 733 | struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; |
| 734 | u8 i, val; |
| 735 | |
| 736 | if (!info->pg_thermal_trim) { |
| 737 | rtw89_debug(rtwdev, RTW89_DBG_RFK, |
| 738 | "[THERMAL][TRIM] no PG, do nothing\n"); |
| 739 | |
| 740 | return; |
| 741 | } |
| 742 | |
| 743 | for (i = 0; i < RF_PATH_NUM_8852B; i++) { |
| 744 | val = __thm_setting(info->thermal_trim[i]); |
| 745 | rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); |
| 746 | |
| 747 | rtw89_debug(rtwdev, RTW89_DBG_RFK, |
| 748 | "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", |
| 749 | i, val); |
| 750 | } |
| 751 | #undef __thm_setting |
| 752 | } |
| 753 | |
| 754 | static void rtw8852b_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, |
| 755 | u8 *phycap_map) |
| 756 | { |
| 757 | struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; |
| 758 | static const u32 pabias_trim_addr[RF_PATH_NUM_8852B] = {0x5DE, 0x5DB}; |
| 759 | u32 addr = rtwdev->chip->phycap_addr; |
| 760 | u8 i; |
| 761 | |
| 762 | for (i = 0; i < RF_PATH_NUM_8852B; i++) { |
| 763 | info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; |
| 764 | |
| 765 | rtw89_debug(rtwdev, RTW89_DBG_RFK, |
| 766 | "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", |
| 767 | i, info->pa_bias_trim[i]); |
| 768 | |
| 769 | if (info->pa_bias_trim[i] != 0xff) |
| 770 | info->pg_pa_bias_trim = true; |
| 771 | } |
| 772 | } |
| 773 | |
| 774 | static void rtw8852b_pa_bias_trim(struct rtw89_dev *rtwdev) |
| 775 | { |
| 776 | struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; |
| 777 | u8 pabias_2g, pabias_5g; |
| 778 | u8 i; |
| 779 | |
| 780 | if (!info->pg_pa_bias_trim) { |
| 781 | rtw89_debug(rtwdev, RTW89_DBG_RFK, |
| 782 | "[PA_BIAS][TRIM] no PG, do nothing\n"); |
| 783 | |
| 784 | return; |
| 785 | } |
| 786 | |
| 787 | for (i = 0; i < RF_PATH_NUM_8852B; i++) { |
| 788 | pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); |
| 789 | pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); |
| 790 | |
| 791 | rtw89_debug(rtwdev, RTW89_DBG_RFK, |
| 792 | "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", |
| 793 | i, pabias_2g, pabias_5g); |
| 794 | |
| 795 | rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); |
| 796 | rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); |
| 797 | } |
| 798 | } |
| 799 | |
| 800 | static void rtw8852b_phycap_parsing_gain_comp(struct rtw89_dev *rtwdev, u8 *phycap_map) |
| 801 | { |
| 802 | static const u32 comp_addrs[][RTW89_SUBBAND_2GHZ_5GHZ_NR] = { |
| 803 | {0x5BB, 0x5BA, 0, 0x5B9, 0x5B8}, |
| 804 | {0x590, 0x58F, 0, 0x58E, 0x58D}, |
| 805 | }; |
| 806 | struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; |
| 807 | u32 phycap_addr = rtwdev->chip->phycap_addr; |
| 808 | bool valid = false; |
| 809 | int path, i; |
| 810 | u8 data; |
| 811 | |
| 812 | for (path = 0; path < 2; path++) |
| 813 | for (i = 0; i < RTW89_SUBBAND_2GHZ_5GHZ_NR; i++) { |
| 814 | if (comp_addrs[path][i] == 0) |
| 815 | continue; |
| 816 | |
| 817 | data = phycap_map[comp_addrs[path][i] - phycap_addr]; |
| 818 | valid |= _decode_efuse_gain(data, NULL, |
| 819 | &gain->comp[path][i]); |
| 820 | } |
| 821 | |
| 822 | gain->comp_valid = valid; |
| 823 | } |
| 824 | |
| 825 | static int rtw8852b_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) |
| 826 | { |
| 827 | rtw8852b_phycap_parsing_power_cal(rtwdev, phycap_map); |
| 828 | rtw8852b_phycap_parsing_tssi(rtwdev, phycap_map); |
| 829 | rtw8852b_phycap_parsing_thermal_trim(rtwdev, phycap_map); |
| 830 | rtw8852b_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); |
| 831 | rtw8852b_phycap_parsing_gain_comp(rtwdev, phycap_map); |
| 832 | |
| 833 | return 0; |
| 834 | } |
| 835 | |
| 836 | static void rtw8852b_power_trim(struct rtw89_dev *rtwdev) |
| 837 | { |
| 838 | rtw8852b_thermal_trim(rtwdev); |
| 839 | rtw8852b_pa_bias_trim(rtwdev); |
| 840 | } |
| 841 | |
Ping-Ke Shih | 6b06989 | 2022-10-05 16:32:12 +0800 | [diff] [blame] | 842 | static void rtw8852b_set_channel_mac(struct rtw89_dev *rtwdev, |
| 843 | const struct rtw89_chan *chan, |
| 844 | u8 mac_idx) |
| 845 | { |
| 846 | u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx); |
| 847 | u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx); |
| 848 | u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx); |
| 849 | u8 txsc20 = 0, txsc40 = 0; |
| 850 | |
| 851 | switch (chan->band_width) { |
| 852 | case RTW89_CHANNEL_WIDTH_80: |
| 853 | txsc40 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_40); |
| 854 | fallthrough; |
| 855 | case RTW89_CHANNEL_WIDTH_40: |
| 856 | txsc20 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_20); |
| 857 | break; |
| 858 | default: |
| 859 | break; |
| 860 | } |
| 861 | |
| 862 | switch (chan->band_width) { |
| 863 | case RTW89_CHANNEL_WIDTH_80: |
| 864 | rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1)); |
| 865 | rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4)); |
| 866 | break; |
| 867 | case RTW89_CHANNEL_WIDTH_40: |
| 868 | rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0)); |
| 869 | rtw89_write32(rtwdev, sub_carr, txsc20); |
| 870 | break; |
| 871 | case RTW89_CHANNEL_WIDTH_20: |
| 872 | rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK); |
| 873 | rtw89_write32(rtwdev, sub_carr, 0); |
| 874 | break; |
| 875 | default: |
| 876 | break; |
| 877 | } |
| 878 | |
| 879 | if (chan->channel > 14) { |
| 880 | rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE); |
| 881 | rtw89_write8_set(rtwdev, chk_rate, |
| 882 | B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); |
| 883 | } else { |
| 884 | rtw89_write8_set(rtwdev, chk_rate, B_AX_BAND_MODE); |
| 885 | rtw89_write8_clr(rtwdev, chk_rate, |
| 886 | B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); |
| 887 | } |
| 888 | } |
| 889 | |
| 890 | static const u32 rtw8852b_sco_barker_threshold[14] = { |
| 891 | 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6, |
| 892 | 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4 |
| 893 | }; |
| 894 | |
| 895 | static const u32 rtw8852b_sco_cck_threshold[14] = { |
| 896 | 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724, |
| 897 | 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed |
| 898 | }; |
| 899 | |
| 900 | static void rtw8852b_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 primary_ch) |
| 901 | { |
| 902 | u8 ch_element = primary_ch - 1; |
| 903 | |
| 904 | rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH, |
| 905 | rtw8852b_sco_barker_threshold[ch_element]); |
| 906 | rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH, |
| 907 | rtw8852b_sco_cck_threshold[ch_element]); |
| 908 | } |
| 909 | |
| 910 | static u8 rtw8852b_sco_mapping(u8 central_ch) |
| 911 | { |
| 912 | if (central_ch == 1) |
| 913 | return 109; |
| 914 | else if (central_ch >= 2 && central_ch <= 6) |
| 915 | return 108; |
| 916 | else if (central_ch >= 7 && central_ch <= 10) |
| 917 | return 107; |
| 918 | else if (central_ch >= 11 && central_ch <= 14) |
| 919 | return 106; |
| 920 | else if (central_ch == 36 || central_ch == 38) |
| 921 | return 51; |
| 922 | else if (central_ch >= 40 && central_ch <= 58) |
| 923 | return 50; |
| 924 | else if (central_ch >= 60 && central_ch <= 64) |
| 925 | return 49; |
| 926 | else if (central_ch == 100 || central_ch == 102) |
| 927 | return 48; |
| 928 | else if (central_ch >= 104 && central_ch <= 126) |
| 929 | return 47; |
| 930 | else if (central_ch >= 128 && central_ch <= 151) |
| 931 | return 46; |
| 932 | else if (central_ch >= 153 && central_ch <= 177) |
| 933 | return 45; |
| 934 | else |
| 935 | return 0; |
| 936 | } |
| 937 | |
| 938 | struct rtw8852b_bb_gain { |
| 939 | u32 gain_g[BB_PATH_NUM_8852B]; |
| 940 | u32 gain_a[BB_PATH_NUM_8852B]; |
| 941 | u32 gain_mask; |
| 942 | }; |
| 943 | |
| 944 | static const struct rtw8852b_bb_gain bb_gain_lna[LNA_GAIN_NUM] = { |
| 945 | { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, |
| 946 | .gain_mask = 0x00ff0000 }, |
| 947 | { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, |
| 948 | .gain_mask = 0xff000000 }, |
| 949 | { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, |
| 950 | .gain_mask = 0x000000ff }, |
| 951 | { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, |
| 952 | .gain_mask = 0x0000ff00 }, |
| 953 | { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, |
| 954 | .gain_mask = 0x00ff0000 }, |
| 955 | { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, |
| 956 | .gain_mask = 0xff000000 }, |
| 957 | { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, |
| 958 | .gain_mask = 0x000000ff }, |
| 959 | }; |
| 960 | |
| 961 | static const struct rtw8852b_bb_gain bb_gain_tia[TIA_GAIN_NUM] = { |
| 962 | { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, |
| 963 | .gain_mask = 0x00ff0000 }, |
| 964 | { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, |
| 965 | .gain_mask = 0xff000000 }, |
| 966 | }; |
| 967 | |
| 968 | static void rtw8852b_set_gain_error(struct rtw89_dev *rtwdev, |
| 969 | enum rtw89_subband subband, |
| 970 | enum rtw89_rf_path path) |
| 971 | { |
| 972 | const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; |
| 973 | u8 gain_band = rtw89_subband_to_bb_gain_band(subband); |
| 974 | s32 val; |
| 975 | u32 reg; |
| 976 | u32 mask; |
| 977 | int i; |
| 978 | |
| 979 | for (i = 0; i < LNA_GAIN_NUM; i++) { |
| 980 | if (subband == RTW89_CH_2G) |
| 981 | reg = bb_gain_lna[i].gain_g[path]; |
| 982 | else |
| 983 | reg = bb_gain_lna[i].gain_a[path]; |
| 984 | |
| 985 | mask = bb_gain_lna[i].gain_mask; |
| 986 | val = gain->lna_gain[gain_band][path][i]; |
| 987 | rtw89_phy_write32_mask(rtwdev, reg, mask, val); |
| 988 | } |
| 989 | |
| 990 | for (i = 0; i < TIA_GAIN_NUM; i++) { |
| 991 | if (subband == RTW89_CH_2G) |
| 992 | reg = bb_gain_tia[i].gain_g[path]; |
| 993 | else |
| 994 | reg = bb_gain_tia[i].gain_a[path]; |
| 995 | |
| 996 | mask = bb_gain_tia[i].gain_mask; |
| 997 | val = gain->tia_gain[gain_band][path][i]; |
| 998 | rtw89_phy_write32_mask(rtwdev, reg, mask, val); |
| 999 | } |
| 1000 | } |
| 1001 | |
| 1002 | static void rtw8852b_set_gain_offset(struct rtw89_dev *rtwdev, |
| 1003 | enum rtw89_subband subband, |
| 1004 | enum rtw89_phy_idx phy_idx) |
| 1005 | { |
| 1006 | static const u32 gain_err_addr[2] = {R_P0_AGC_RSVD, R_P1_AGC_RSVD}; |
| 1007 | static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA1_LNA6_OP1DB_V1, |
| 1008 | R_PATH1_G_TIA1_LNA6_OP1DB_V1}; |
| 1009 | struct rtw89_hal *hal = &rtwdev->hal; |
| 1010 | struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain; |
| 1011 | enum rtw89_gain_offset gain_ofdm_band; |
| 1012 | s32 offset_a, offset_b; |
| 1013 | s32 offset_ofdm, offset_cck; |
| 1014 | s32 tmp; |
| 1015 | u8 path; |
| 1016 | |
| 1017 | if (!efuse_gain->comp_valid) |
| 1018 | goto next; |
| 1019 | |
| 1020 | for (path = RF_PATH_A; path < BB_PATH_NUM_8852B; path++) { |
| 1021 | tmp = efuse_gain->comp[path][subband]; |
| 1022 | tmp = clamp_t(s32, tmp << 2, S8_MIN, S8_MAX); |
| 1023 | rtw89_phy_write32_mask(rtwdev, gain_err_addr[path], MASKBYTE0, tmp); |
| 1024 | } |
| 1025 | |
| 1026 | next: |
| 1027 | if (!efuse_gain->offset_valid) |
| 1028 | return; |
| 1029 | |
| 1030 | gain_ofdm_band = rtw89_subband_to_gain_offset_band_of_ofdm(subband); |
| 1031 | |
| 1032 | offset_a = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band]; |
| 1033 | offset_b = -efuse_gain->offset[RF_PATH_B][gain_ofdm_band]; |
| 1034 | |
| 1035 | tmp = -((offset_a << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2)); |
| 1036 | tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); |
| 1037 | rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_A], B_PATH0_R_G_OFST_MASK, tmp); |
| 1038 | |
| 1039 | tmp = -((offset_b << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2)); |
| 1040 | tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); |
| 1041 | rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_B], B_PATH0_R_G_OFST_MASK, tmp); |
| 1042 | |
| 1043 | if (hal->antenna_rx == RF_B) { |
| 1044 | offset_ofdm = -efuse_gain->offset[RF_PATH_B][gain_ofdm_band]; |
| 1045 | offset_cck = -efuse_gain->offset[RF_PATH_B][0]; |
| 1046 | } else { |
| 1047 | offset_ofdm = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band]; |
| 1048 | offset_cck = -efuse_gain->offset[RF_PATH_A][0]; |
| 1049 | } |
| 1050 | |
| 1051 | tmp = (offset_ofdm << 4) + efuse_gain->offset_base[RTW89_PHY_0]; |
| 1052 | tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); |
| 1053 | rtw89_phy_write32_idx(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx); |
| 1054 | |
| 1055 | tmp = (offset_ofdm << 4) + efuse_gain->rssi_base[RTW89_PHY_0]; |
| 1056 | tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); |
| 1057 | rtw89_phy_write32_idx(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx); |
| 1058 | |
| 1059 | if (subband == RTW89_CH_2G) { |
| 1060 | tmp = (offset_cck << 3) + (efuse_gain->offset_base[RTW89_PHY_0] >> 1); |
| 1061 | tmp = clamp_t(s32, tmp, S8_MIN >> 1, S8_MAX >> 1); |
| 1062 | rtw89_phy_write32_mask(rtwdev, R_RX_RPL_OFST, |
| 1063 | B_RX_RPL_OFST_CCK_MASK, tmp); |
| 1064 | } |
| 1065 | } |
| 1066 | |
| 1067 | static |
| 1068 | void rtw8852b_set_rxsc_rpl_comp(struct rtw89_dev *rtwdev, enum rtw89_subband subband) |
| 1069 | { |
| 1070 | const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; |
| 1071 | u8 band = rtw89_subband_to_bb_gain_band(subband); |
| 1072 | u32 val; |
| 1073 | |
| 1074 | val = FIELD_PREP(B_P0_RPL1_20_MASK, (gain->rpl_ofst_20[band][RF_PATH_A] + |
| 1075 | gain->rpl_ofst_20[band][RF_PATH_B]) / 2) | |
| 1076 | FIELD_PREP(B_P0_RPL1_40_MASK, (gain->rpl_ofst_40[band][RF_PATH_A][0] + |
| 1077 | gain->rpl_ofst_40[band][RF_PATH_B][0]) / 2) | |
| 1078 | FIELD_PREP(B_P0_RPL1_41_MASK, (gain->rpl_ofst_40[band][RF_PATH_A][1] + |
| 1079 | gain->rpl_ofst_40[band][RF_PATH_B][1]) / 2); |
| 1080 | val >>= B_P0_RPL1_SHIFT; |
| 1081 | rtw89_phy_write32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_MASK, val); |
| 1082 | rtw89_phy_write32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_MASK, val); |
| 1083 | |
| 1084 | val = FIELD_PREP(B_P0_RTL2_42_MASK, (gain->rpl_ofst_40[band][RF_PATH_A][2] + |
| 1085 | gain->rpl_ofst_40[band][RF_PATH_B][2]) / 2) | |
| 1086 | FIELD_PREP(B_P0_RTL2_80_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][0] + |
| 1087 | gain->rpl_ofst_80[band][RF_PATH_B][0]) / 2) | |
| 1088 | FIELD_PREP(B_P0_RTL2_81_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][1] + |
| 1089 | gain->rpl_ofst_80[band][RF_PATH_B][1]) / 2) | |
| 1090 | FIELD_PREP(B_P0_RTL2_8A_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][10] + |
| 1091 | gain->rpl_ofst_80[band][RF_PATH_B][10]) / 2); |
| 1092 | rtw89_phy_write32(rtwdev, R_P0_RPL2, val); |
| 1093 | rtw89_phy_write32(rtwdev, R_P1_RPL2, val); |
| 1094 | |
| 1095 | val = FIELD_PREP(B_P0_RTL3_82_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][2] + |
| 1096 | gain->rpl_ofst_80[band][RF_PATH_B][2]) / 2) | |
| 1097 | FIELD_PREP(B_P0_RTL3_83_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][3] + |
| 1098 | gain->rpl_ofst_80[band][RF_PATH_B][3]) / 2) | |
| 1099 | FIELD_PREP(B_P0_RTL3_84_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][4] + |
| 1100 | gain->rpl_ofst_80[band][RF_PATH_B][4]) / 2) | |
| 1101 | FIELD_PREP(B_P0_RTL3_89_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][9] + |
| 1102 | gain->rpl_ofst_80[band][RF_PATH_B][9]) / 2); |
| 1103 | rtw89_phy_write32(rtwdev, R_P0_RPL3, val); |
| 1104 | rtw89_phy_write32(rtwdev, R_P1_RPL3, val); |
| 1105 | } |
| 1106 | |
| 1107 | static void rtw8852b_ctrl_ch(struct rtw89_dev *rtwdev, |
| 1108 | const struct rtw89_chan *chan, |
| 1109 | enum rtw89_phy_idx phy_idx) |
| 1110 | { |
| 1111 | u8 central_ch = chan->channel; |
| 1112 | u8 subband = chan->subband_type; |
| 1113 | u8 sco_comp; |
| 1114 | bool is_2g = central_ch <= 14; |
| 1115 | |
| 1116 | /* Path A */ |
| 1117 | if (is_2g) |
| 1118 | rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, |
| 1119 | B_PATH0_BAND_SEL_MSK_V1, 1, phy_idx); |
| 1120 | else |
| 1121 | rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, |
| 1122 | B_PATH0_BAND_SEL_MSK_V1, 0, phy_idx); |
| 1123 | |
| 1124 | /* Path B */ |
| 1125 | if (is_2g) |
| 1126 | rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, |
| 1127 | B_PATH1_BAND_SEL_MSK_V1, 1, phy_idx); |
| 1128 | else |
| 1129 | rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, |
| 1130 | B_PATH1_BAND_SEL_MSK_V1, 0, phy_idx); |
| 1131 | |
| 1132 | /* SCO compensate FC setting */ |
| 1133 | sco_comp = rtw8852b_sco_mapping(central_ch); |
| 1134 | rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_INV, sco_comp, phy_idx); |
| 1135 | |
| 1136 | if (chan->band_type == RTW89_BAND_6G) |
| 1137 | return; |
| 1138 | |
| 1139 | /* CCK parameters */ |
| 1140 | if (central_ch == 14) { |
| 1141 | rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3b13ff); |
| 1142 | rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x1c42de); |
| 1143 | rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfdb0ad); |
| 1144 | rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xf60f6e); |
| 1145 | rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xfd8f92); |
| 1146 | rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011); |
| 1147 | rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c); |
| 1148 | rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xfff00a); |
| 1149 | } else { |
| 1150 | rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3d23ff); |
| 1151 | rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x29b354); |
| 1152 | rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8); |
| 1153 | rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xfdb053); |
| 1154 | rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xf86f9a); |
| 1155 | rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0xfaef92); |
| 1156 | rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0xfe5fcc); |
| 1157 | rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xffdff5); |
| 1158 | } |
| 1159 | |
| 1160 | rtw8852b_set_gain_error(rtwdev, subband, RF_PATH_A); |
| 1161 | rtw8852b_set_gain_error(rtwdev, subband, RF_PATH_B); |
| 1162 | rtw8852b_set_gain_offset(rtwdev, subband, phy_idx); |
| 1163 | rtw8852b_set_rxsc_rpl_comp(rtwdev, subband); |
| 1164 | } |
| 1165 | |
| 1166 | static void rtw8852b_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) |
| 1167 | { |
| 1168 | static const u32 adc_sel[2] = {0xC0EC, 0xC1EC}; |
| 1169 | static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4}; |
| 1170 | |
| 1171 | switch (bw) { |
| 1172 | case RTW89_CHANNEL_WIDTH_5: |
| 1173 | rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); |
| 1174 | rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); |
| 1175 | break; |
| 1176 | case RTW89_CHANNEL_WIDTH_10: |
| 1177 | rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); |
| 1178 | rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); |
| 1179 | break; |
| 1180 | case RTW89_CHANNEL_WIDTH_20: |
| 1181 | rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); |
| 1182 | rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); |
| 1183 | break; |
| 1184 | case RTW89_CHANNEL_WIDTH_40: |
| 1185 | rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); |
| 1186 | rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); |
| 1187 | break; |
| 1188 | case RTW89_CHANNEL_WIDTH_80: |
| 1189 | rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); |
| 1190 | rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); |
| 1191 | break; |
| 1192 | default: |
| 1193 | rtw89_warn(rtwdev, "Fail to set ADC\n"); |
| 1194 | } |
| 1195 | } |
| 1196 | |
| 1197 | static void rtw8852b_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, |
| 1198 | enum rtw89_phy_idx phy_idx) |
| 1199 | { |
| 1200 | u32 rx_path_0; |
| 1201 | |
| 1202 | switch (bw) { |
| 1203 | case RTW89_CHANNEL_WIDTH_5: |
| 1204 | rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx); |
| 1205 | rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x1, phy_idx); |
| 1206 | rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx); |
| 1207 | |
| 1208 | /*Set RF mode at 3 */ |
| 1209 | rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, |
| 1210 | B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx); |
| 1211 | rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, |
| 1212 | B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx); |
| 1213 | break; |
| 1214 | case RTW89_CHANNEL_WIDTH_10: |
| 1215 | rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx); |
| 1216 | rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x2, phy_idx); |
| 1217 | rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx); |
| 1218 | |
| 1219 | /*Set RF mode at 3 */ |
| 1220 | rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, |
| 1221 | B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx); |
| 1222 | rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, |
| 1223 | B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx); |
| 1224 | break; |
| 1225 | case RTW89_CHANNEL_WIDTH_20: |
| 1226 | rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx); |
| 1227 | rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx); |
| 1228 | rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx); |
| 1229 | |
| 1230 | /*Set RF mode at 3 */ |
| 1231 | rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, |
| 1232 | B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx); |
| 1233 | rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, |
| 1234 | B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx); |
| 1235 | break; |
| 1236 | case RTW89_CHANNEL_WIDTH_40: |
| 1237 | rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x1, phy_idx); |
| 1238 | rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx); |
| 1239 | rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, |
| 1240 | pri_ch, phy_idx); |
| 1241 | |
| 1242 | /*Set RF mode at 3 */ |
| 1243 | rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, |
| 1244 | B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx); |
| 1245 | rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, |
| 1246 | B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx); |
| 1247 | /*CCK primary channel */ |
| 1248 | if (pri_ch == RTW89_SC_20_UPPER) |
| 1249 | rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1); |
| 1250 | else |
| 1251 | rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0); |
| 1252 | |
| 1253 | break; |
| 1254 | case RTW89_CHANNEL_WIDTH_80: |
| 1255 | rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x2, phy_idx); |
| 1256 | rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx); |
| 1257 | rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, |
| 1258 | pri_ch, phy_idx); |
| 1259 | |
| 1260 | /*Set RF mode at A */ |
| 1261 | rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, |
| 1262 | B_P0_RFMODE_ORI_RX_ALL, 0xaaa, phy_idx); |
| 1263 | rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, |
| 1264 | B_P1_RFMODE_ORI_RX_ALL, 0xaaa, phy_idx); |
| 1265 | break; |
| 1266 | default: |
| 1267 | rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, |
| 1268 | pri_ch); |
| 1269 | } |
| 1270 | |
| 1271 | rtw8852b_bw_setting(rtwdev, bw, RF_PATH_A); |
| 1272 | rtw8852b_bw_setting(rtwdev, bw, RF_PATH_B); |
| 1273 | |
| 1274 | rx_path_0 = rtw89_phy_read32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, |
| 1275 | phy_idx); |
| 1276 | if (rx_path_0 == 0x1) |
| 1277 | rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, |
| 1278 | B_P1_RFMODE_ORI_RX_ALL, 0x111, phy_idx); |
| 1279 | else if (rx_path_0 == 0x2) |
| 1280 | rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, |
| 1281 | B_P0_RFMODE_ORI_RX_ALL, 0x111, phy_idx); |
| 1282 | } |
| 1283 | |
| 1284 | static void rtw8852b_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en) |
| 1285 | { |
| 1286 | if (cck_en) { |
| 1287 | rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1); |
| 1288 | rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0); |
| 1289 | } else { |
| 1290 | rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0); |
| 1291 | rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1); |
| 1292 | } |
| 1293 | } |
| 1294 | |
| 1295 | static void rtw8852b_5m_mask(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, |
| 1296 | enum rtw89_phy_idx phy_idx) |
| 1297 | { |
Eric Huang | d33fc8d | 2023-04-06 15:28:41 +0800 | [diff] [blame] | 1298 | u8 pri_ch = chan->pri_ch_idx; |
Ping-Ke Shih | 6b06989 | 2022-10-05 16:32:12 +0800 | [diff] [blame] | 1299 | bool mask_5m_low; |
| 1300 | bool mask_5m_en; |
| 1301 | |
| 1302 | switch (chan->band_width) { |
| 1303 | case RTW89_CHANNEL_WIDTH_40: |
| 1304 | /* Prich=1: Mask 5M High, Prich=2: Mask 5M Low */ |
| 1305 | mask_5m_en = true; |
Eric Huang | d33fc8d | 2023-04-06 15:28:41 +0800 | [diff] [blame] | 1306 | mask_5m_low = pri_ch == RTW89_SC_20_LOWER; |
Ping-Ke Shih | 6b06989 | 2022-10-05 16:32:12 +0800 | [diff] [blame] | 1307 | break; |
| 1308 | case RTW89_CHANNEL_WIDTH_80: |
| 1309 | /* Prich=3: Mask 5M High, Prich=4: Mask 5M Low, Else: Disable */ |
Eric Huang | d33fc8d | 2023-04-06 15:28:41 +0800 | [diff] [blame] | 1310 | mask_5m_en = pri_ch == RTW89_SC_20_UPMOST || |
| 1311 | pri_ch == RTW89_SC_20_LOWEST; |
| 1312 | mask_5m_low = pri_ch == RTW89_SC_20_LOWEST; |
Ping-Ke Shih | 6b06989 | 2022-10-05 16:32:12 +0800 | [diff] [blame] | 1313 | break; |
| 1314 | default: |
| 1315 | mask_5m_en = false; |
| 1316 | break; |
| 1317 | } |
| 1318 | |
| 1319 | if (!mask_5m_en) { |
| 1320 | rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x0); |
| 1321 | rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x0); |
| 1322 | rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1, |
| 1323 | B_ASSIGN_SBD_OPT_EN_V1, 0x0, phy_idx); |
| 1324 | return; |
| 1325 | } |
| 1326 | |
| 1327 | if (mask_5m_low) { |
| 1328 | rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x4); |
| 1329 | rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1); |
| 1330 | rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x0); |
| 1331 | rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x1); |
| 1332 | rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_TH, 0x4); |
| 1333 | rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x1); |
| 1334 | rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB2, 0x0); |
| 1335 | rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB0, 0x1); |
| 1336 | } else { |
| 1337 | rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x4); |
| 1338 | rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1); |
| 1339 | rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x1); |
| 1340 | rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x0); |
| 1341 | rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_TH, 0x4); |
| 1342 | rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x1); |
| 1343 | rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB2, 0x1); |
| 1344 | rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB0, 0x0); |
| 1345 | } |
| 1346 | rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1, |
| 1347 | B_ASSIGN_SBD_OPT_EN_V1, 0x1, phy_idx); |
| 1348 | } |
| 1349 | |
| 1350 | static void rtw8852b_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) |
| 1351 | { |
| 1352 | rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); |
| 1353 | rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); |
| 1354 | fsleep(1); |
| 1355 | rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx); |
| 1356 | rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx); |
| 1357 | rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); |
| 1358 | rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); |
| 1359 | rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx); |
| 1360 | } |
| 1361 | |
Ping-Ke Shih | d0a95ef | 2022-10-09 20:53:55 +0800 | [diff] [blame] | 1362 | static void rtw8852b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band, |
| 1363 | enum rtw89_phy_idx phy_idx, bool en) |
| 1364 | { |
| 1365 | if (en) { |
| 1366 | rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, |
| 1367 | B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); |
| 1368 | rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, |
| 1369 | B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); |
| 1370 | rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx); |
| 1371 | if (band == RTW89_BAND_2G) |
| 1372 | rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0); |
| 1373 | rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0); |
| 1374 | } else { |
| 1375 | rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1); |
| 1376 | rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1); |
| 1377 | rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, |
| 1378 | B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); |
| 1379 | rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, |
| 1380 | B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); |
| 1381 | fsleep(1); |
| 1382 | rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx); |
| 1383 | } |
| 1384 | } |
| 1385 | |
Ping-Ke Shih | a804479 | 2022-10-09 20:53:57 +0800 | [diff] [blame] | 1386 | static void rtw8852b_bb_reset(struct rtw89_dev *rtwdev, |
| 1387 | enum rtw89_phy_idx phy_idx) |
| 1388 | { |
| 1389 | rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); |
| 1390 | rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); |
| 1391 | rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); |
| 1392 | rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); |
| 1393 | rtw8852b_bb_reset_all(rtwdev, phy_idx); |
| 1394 | rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); |
| 1395 | rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); |
| 1396 | rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); |
| 1397 | rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); |
| 1398 | } |
| 1399 | |
| 1400 | static void rtw8852b_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, |
| 1401 | enum rtw89_phy_idx phy_idx) |
| 1402 | { |
| 1403 | u32 addr; |
| 1404 | |
| 1405 | for (addr = R_AX_PWR_MACID_LMT_TABLE0; |
| 1406 | addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) |
| 1407 | rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); |
| 1408 | } |
| 1409 | |
| 1410 | static void rtw8852b_bb_sethw(struct rtw89_dev *rtwdev) |
| 1411 | { |
| 1412 | struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; |
| 1413 | |
| 1414 | rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP); |
| 1415 | rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP); |
| 1416 | |
| 1417 | rtw8852b_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); |
| 1418 | |
| 1419 | /* read these registers after loading BB parameters */ |
| 1420 | gain->offset_base[RTW89_PHY_0] = |
| 1421 | rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK); |
| 1422 | gain->rssi_base[RTW89_PHY_0] = |
| 1423 | rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK); |
| 1424 | } |
| 1425 | |
Ping-Ke Shih | a215b2b | 2022-11-25 15:24:16 +0800 | [diff] [blame] | 1426 | static void rtw8852b_bb_set_pop(struct rtw89_dev *rtwdev) |
| 1427 | { |
| 1428 | if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) |
| 1429 | rtw89_phy_write32_clr(rtwdev, R_PKT_CTRL, B_PKT_POP_EN); |
| 1430 | } |
| 1431 | |
Ping-Ke Shih | 6b06989 | 2022-10-05 16:32:12 +0800 | [diff] [blame] | 1432 | static void rtw8852b_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, |
| 1433 | enum rtw89_phy_idx phy_idx) |
| 1434 | { |
| 1435 | bool cck_en = chan->channel <= 14; |
| 1436 | u8 pri_ch_idx = chan->pri_ch_idx; |
Po-Hao Huang | 4f24d7a | 2023-02-20 15:02:00 +0800 | [diff] [blame] | 1437 | u8 band = chan->band_type, chan_idx; |
Ping-Ke Shih | 6b06989 | 2022-10-05 16:32:12 +0800 | [diff] [blame] | 1438 | |
| 1439 | if (cck_en) |
| 1440 | rtw8852b_ctrl_sco_cck(rtwdev, chan->primary_channel); |
| 1441 | |
| 1442 | rtw8852b_ctrl_ch(rtwdev, chan, phy_idx); |
| 1443 | rtw8852b_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); |
| 1444 | rtw8852b_ctrl_cck_en(rtwdev, cck_en); |
| 1445 | if (chan->band_type == RTW89_BAND_5G) { |
| 1446 | rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, |
| 1447 | B_PATH0_BT_SHARE_V1, 0x0); |
| 1448 | rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, |
| 1449 | B_PATH0_BTG_PATH_V1, 0x0); |
| 1450 | rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, |
| 1451 | B_PATH1_BT_SHARE_V1, 0x0); |
| 1452 | rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, |
| 1453 | B_PATH1_BTG_PATH_V1, 0x0); |
| 1454 | rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0); |
| 1455 | rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0); |
| 1456 | rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1, |
| 1457 | B_BT_DYN_DC_EST_EN_MSK, 0x0); |
| 1458 | rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0); |
| 1459 | } |
Po-Hao Huang | 4f24d7a | 2023-02-20 15:02:00 +0800 | [diff] [blame] | 1460 | chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band); |
| 1461 | rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx); |
Ping-Ke Shih | 6b06989 | 2022-10-05 16:32:12 +0800 | [diff] [blame] | 1462 | rtw8852b_5m_mask(rtwdev, chan, phy_idx); |
Ping-Ke Shih | a215b2b | 2022-11-25 15:24:16 +0800 | [diff] [blame] | 1463 | rtw8852b_bb_set_pop(rtwdev); |
Ping-Ke Shih | 6b06989 | 2022-10-05 16:32:12 +0800 | [diff] [blame] | 1464 | rtw8852b_bb_reset_all(rtwdev, phy_idx); |
| 1465 | } |
| 1466 | |
| 1467 | static void rtw8852b_set_channel(struct rtw89_dev *rtwdev, |
| 1468 | const struct rtw89_chan *chan, |
| 1469 | enum rtw89_mac_idx mac_idx, |
| 1470 | enum rtw89_phy_idx phy_idx) |
| 1471 | { |
| 1472 | rtw8852b_set_channel_mac(rtwdev, chan, mac_idx); |
| 1473 | rtw8852b_set_channel_bb(rtwdev, chan, phy_idx); |
| 1474 | rtw8852b_set_channel_rf(rtwdev, chan, phy_idx); |
| 1475 | } |
| 1476 | |
Ping-Ke Shih | d0a95ef | 2022-10-09 20:53:55 +0800 | [diff] [blame] | 1477 | static void rtw8852b_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, |
| 1478 | enum rtw89_rf_path path) |
| 1479 | { |
| 1480 | static const u32 tssi_trk[2] = {R_P0_TSSI_TRK, R_P1_TSSI_TRK}; |
| 1481 | static const u32 ctrl_bbrst[2] = {R_P0_TXPW_RSTB, R_P1_TXPW_RSTB}; |
| 1482 | |
| 1483 | if (en) { |
| 1484 | rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x0); |
| 1485 | rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x0); |
| 1486 | } else { |
| 1487 | rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x1); |
| 1488 | rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x1); |
| 1489 | } |
| 1490 | } |
| 1491 | |
| 1492 | static void rtw8852b_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, |
| 1493 | u8 phy_idx) |
| 1494 | { |
| 1495 | if (!rtwdev->dbcc_en) { |
| 1496 | rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_A); |
| 1497 | rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_B); |
| 1498 | } else { |
| 1499 | if (phy_idx == RTW89_PHY_0) |
| 1500 | rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_A); |
| 1501 | else |
| 1502 | rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_B); |
| 1503 | } |
| 1504 | } |
| 1505 | |
| 1506 | static void rtw8852b_adc_en(struct rtw89_dev *rtwdev, bool en) |
| 1507 | { |
| 1508 | if (en) |
| 1509 | rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0); |
| 1510 | else |
| 1511 | rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf); |
| 1512 | } |
| 1513 | |
| 1514 | static void rtw8852b_set_channel_help(struct rtw89_dev *rtwdev, bool enter, |
| 1515 | struct rtw89_channel_help_params *p, |
| 1516 | const struct rtw89_chan *chan, |
| 1517 | enum rtw89_mac_idx mac_idx, |
| 1518 | enum rtw89_phy_idx phy_idx) |
| 1519 | { |
| 1520 | if (enter) { |
| 1521 | rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL); |
| 1522 | rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); |
| 1523 | rtw8852b_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0); |
| 1524 | rtw8852b_adc_en(rtwdev, false); |
| 1525 | fsleep(40); |
| 1526 | rtw8852b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false); |
| 1527 | } else { |
| 1528 | rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); |
| 1529 | rtw8852b_adc_en(rtwdev, true); |
| 1530 | rtw8852b_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0); |
| 1531 | rtw8852b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true); |
| 1532 | rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en); |
| 1533 | } |
| 1534 | } |
| 1535 | |
Ping-Ke Shih | ef8acbc | 2022-10-14 14:02:35 +0800 | [diff] [blame] | 1536 | static void rtw8852b_rfk_init(struct rtw89_dev *rtwdev) |
| 1537 | { |
| 1538 | rtwdev->is_tssi_mode[RF_PATH_A] = false; |
| 1539 | rtwdev->is_tssi_mode[RF_PATH_B] = false; |
| 1540 | |
| 1541 | rtw8852b_dpk_init(rtwdev); |
| 1542 | rtw8852b_rck(rtwdev); |
| 1543 | rtw8852b_dack(rtwdev); |
| 1544 | rtw8852b_rx_dck(rtwdev, RTW89_PHY_0); |
| 1545 | } |
| 1546 | |
| 1547 | static void rtw8852b_rfk_channel(struct rtw89_dev *rtwdev) |
| 1548 | { |
| 1549 | enum rtw89_phy_idx phy_idx = RTW89_PHY_0; |
| 1550 | |
| 1551 | rtw8852b_rx_dck(rtwdev, phy_idx); |
| 1552 | rtw8852b_iqk(rtwdev, phy_idx); |
| 1553 | rtw8852b_tssi(rtwdev, phy_idx, true); |
| 1554 | rtw8852b_dpk(rtwdev, phy_idx); |
| 1555 | } |
| 1556 | |
| 1557 | static void rtw8852b_rfk_band_changed(struct rtw89_dev *rtwdev, |
| 1558 | enum rtw89_phy_idx phy_idx) |
| 1559 | { |
| 1560 | rtw8852b_tssi_scan(rtwdev, phy_idx); |
| 1561 | } |
| 1562 | |
| 1563 | static void rtw8852b_rfk_scan(struct rtw89_dev *rtwdev, bool start) |
| 1564 | { |
| 1565 | rtw8852b_wifi_scan_notify(rtwdev, start, RTW89_PHY_0); |
| 1566 | } |
| 1567 | |
| 1568 | static void rtw8852b_rfk_track(struct rtw89_dev *rtwdev) |
| 1569 | { |
| 1570 | rtw8852b_dpk_track(rtwdev); |
| 1571 | } |
| 1572 | |
Ping-Ke Shih | 08484e1 | 2022-09-28 16:43:33 +0800 | [diff] [blame] | 1573 | static u32 rtw8852b_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, |
| 1574 | enum rtw89_phy_idx phy_idx, s16 ref) |
| 1575 | { |
| 1576 | const u16 tssi_16dbm_cw = 0x12c; |
| 1577 | const u8 base_cw_0db = 0x27; |
| 1578 | const s8 ofst_int = 0; |
| 1579 | s16 pwr_s10_3; |
| 1580 | s16 rf_pwr_cw; |
| 1581 | u16 bb_pwr_cw; |
| 1582 | u32 pwr_cw; |
| 1583 | u32 tssi_ofst_cw; |
| 1584 | |
| 1585 | pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); |
| 1586 | bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); |
| 1587 | rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); |
| 1588 | rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); |
| 1589 | pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; |
| 1590 | |
| 1591 | tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); |
| 1592 | rtw89_debug(rtwdev, RTW89_DBG_TXPWR, |
| 1593 | "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", |
| 1594 | tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); |
| 1595 | |
| 1596 | return FIELD_PREP(B_DPD_TSSI_CW, tssi_ofst_cw) | |
| 1597 | FIELD_PREP(B_DPD_PWR_CW, pwr_cw) | |
| 1598 | FIELD_PREP(B_DPD_REF, ref); |
| 1599 | } |
| 1600 | |
| 1601 | static void rtw8852b_set_txpwr_ref(struct rtw89_dev *rtwdev, |
| 1602 | enum rtw89_phy_idx phy_idx) |
| 1603 | { |
| 1604 | static const u32 addr[RF_PATH_NUM_8852B] = {0x5800, 0x7800}; |
| 1605 | const u32 mask = B_DPD_TSSI_CW | B_DPD_PWR_CW | B_DPD_REF; |
| 1606 | const u8 ofst_ofdm = 0x4; |
| 1607 | const u8 ofst_cck = 0x8; |
| 1608 | const s16 ref_ofdm = 0; |
| 1609 | const s16 ref_cck = 0; |
| 1610 | u32 val; |
| 1611 | u8 i; |
| 1612 | |
| 1613 | rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); |
| 1614 | |
| 1615 | rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, |
| 1616 | B_AX_PWR_REF, 0x0); |
| 1617 | |
| 1618 | rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); |
| 1619 | val = rtw8852b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); |
| 1620 | |
| 1621 | for (i = 0; i < RF_PATH_NUM_8852B; i++) |
| 1622 | rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, |
| 1623 | phy_idx); |
| 1624 | |
| 1625 | rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); |
| 1626 | val = rtw8852b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); |
| 1627 | |
| 1628 | for (i = 0; i < RF_PATH_NUM_8852B; i++) |
| 1629 | rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, |
| 1630 | phy_idx); |
| 1631 | } |
| 1632 | |
| 1633 | static void rtw8852b_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev, |
Zong-Zhe Yang | 764f07f | 2023-02-01 11:20:57 +0800 | [diff] [blame] | 1634 | const struct rtw89_chan *chan, |
Ping-Ke Shih | 08484e1 | 2022-09-28 16:43:33 +0800 | [diff] [blame] | 1635 | u8 tx_shape_idx, |
| 1636 | enum rtw89_phy_idx phy_idx) |
| 1637 | { |
| 1638 | #define __DFIR_CFG_ADDR(i) (R_TXFIR0 + ((i) << 2)) |
| 1639 | #define __DFIR_CFG_MASK 0xffffffff |
| 1640 | #define __DFIR_CFG_NR 8 |
| 1641 | #define __DECL_DFIR_PARAM(_name, _val...) \ |
| 1642 | static const u32 param_ ## _name[] = {_val}; \ |
| 1643 | static_assert(ARRAY_SIZE(param_ ## _name) == __DFIR_CFG_NR) |
| 1644 | |
| 1645 | __DECL_DFIR_PARAM(flat, |
| 1646 | 0x023D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053, |
| 1647 | 0x00F86F9A, 0x06FAEF92, 0x00FE5FCC, 0x00FFDFF5); |
| 1648 | __DECL_DFIR_PARAM(sharp, |
| 1649 | 0x023D83FF, 0x002C636A, 0x0013F204, 0x00008090, |
| 1650 | 0x00F87FB0, 0x06F99F83, 0x00FDBFBA, 0x00003FF5); |
| 1651 | __DECL_DFIR_PARAM(sharp_14, |
| 1652 | 0x023B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E, |
| 1653 | 0x00FD8F92, 0x0602D011, 0x0001C02C, 0x00FFF00A); |
Ping-Ke Shih | 08484e1 | 2022-09-28 16:43:33 +0800 | [diff] [blame] | 1654 | u8 ch = chan->channel; |
| 1655 | const u32 *param; |
| 1656 | u32 addr; |
| 1657 | int i; |
| 1658 | |
| 1659 | if (ch > 14) { |
| 1660 | rtw89_warn(rtwdev, |
| 1661 | "set tx shape dfir by unknown ch: %d on 2G\n", ch); |
| 1662 | return; |
| 1663 | } |
| 1664 | |
| 1665 | if (ch == 14) |
| 1666 | param = param_sharp_14; |
| 1667 | else |
| 1668 | param = tx_shape_idx == 0 ? param_flat : param_sharp; |
| 1669 | |
| 1670 | for (i = 0; i < __DFIR_CFG_NR; i++) { |
| 1671 | addr = __DFIR_CFG_ADDR(i); |
| 1672 | rtw89_debug(rtwdev, RTW89_DBG_TXPWR, |
| 1673 | "set tx shape dfir: 0x%x: 0x%x\n", addr, param[i]); |
| 1674 | rtw89_phy_write32_idx(rtwdev, addr, __DFIR_CFG_MASK, param[i], |
| 1675 | phy_idx); |
| 1676 | } |
| 1677 | |
| 1678 | #undef __DECL_DFIR_PARAM |
| 1679 | #undef __DFIR_CFG_NR |
| 1680 | #undef __DFIR_CFG_MASK |
| 1681 | #undef __DECL_CFG_ADDR |
| 1682 | } |
| 1683 | |
| 1684 | static void rtw8852b_set_tx_shape(struct rtw89_dev *rtwdev, |
| 1685 | const struct rtw89_chan *chan, |
| 1686 | enum rtw89_phy_idx phy_idx) |
| 1687 | { |
| 1688 | u8 band = chan->band_type; |
| 1689 | u8 regd = rtw89_regd_get(rtwdev, band); |
| 1690 | u8 tx_shape_cck = rtw89_8852b_tx_shape[band][RTW89_RS_CCK][regd]; |
| 1691 | u8 tx_shape_ofdm = rtw89_8852b_tx_shape[band][RTW89_RS_OFDM][regd]; |
| 1692 | |
| 1693 | if (band == RTW89_BAND_2G) |
Zong-Zhe Yang | 764f07f | 2023-02-01 11:20:57 +0800 | [diff] [blame] | 1694 | rtw8852b_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx); |
Ping-Ke Shih | 08484e1 | 2022-09-28 16:43:33 +0800 | [diff] [blame] | 1695 | |
| 1696 | rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG, |
| 1697 | tx_shape_ofdm); |
| 1698 | } |
| 1699 | |
| 1700 | static void rtw8852b_set_txpwr(struct rtw89_dev *rtwdev, |
| 1701 | const struct rtw89_chan *chan, |
| 1702 | enum rtw89_phy_idx phy_idx) |
| 1703 | { |
| 1704 | rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); |
| 1705 | rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); |
| 1706 | rtw8852b_set_tx_shape(rtwdev, chan, phy_idx); |
| 1707 | rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); |
| 1708 | rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); |
| 1709 | } |
| 1710 | |
| 1711 | static void rtw8852b_set_txpwr_ctrl(struct rtw89_dev *rtwdev, |
| 1712 | enum rtw89_phy_idx phy_idx) |
| 1713 | { |
| 1714 | rtw8852b_set_txpwr_ref(rtwdev, phy_idx); |
| 1715 | } |
| 1716 | |
| 1717 | static |
| 1718 | void rtw8852b_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, |
| 1719 | s8 pw_ofst, enum rtw89_mac_idx mac_idx) |
| 1720 | { |
| 1721 | u32 reg; |
| 1722 | |
| 1723 | if (pw_ofst < -16 || pw_ofst > 15) { |
| 1724 | rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst); |
| 1725 | return; |
| 1726 | } |
| 1727 | |
| 1728 | reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_CTRL, mac_idx); |
| 1729 | rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN); |
| 1730 | |
| 1731 | reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx); |
| 1732 | rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst); |
| 1733 | |
| 1734 | pw_ofst = max_t(s8, pw_ofst - 3, -16); |
| 1735 | reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx); |
Ping-Ke Shih | 5466ee9 | 2023-02-03 14:49:07 +0800 | [diff] [blame] | 1736 | rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst); |
Ping-Ke Shih | 08484e1 | 2022-09-28 16:43:33 +0800 | [diff] [blame] | 1737 | } |
| 1738 | |
| 1739 | static int |
| 1740 | rtw8852b_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) |
| 1741 | { |
| 1742 | int ret; |
| 1743 | |
| 1744 | ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); |
| 1745 | if (ret) |
| 1746 | return ret; |
| 1747 | |
| 1748 | ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000); |
| 1749 | if (ret) |
| 1750 | return ret; |
| 1751 | |
| 1752 | ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); |
| 1753 | if (ret) |
| 1754 | return ret; |
| 1755 | |
| 1756 | rtw8852b_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ? |
| 1757 | RTW89_MAC_1 : RTW89_MAC_0); |
| 1758 | |
| 1759 | return 0; |
| 1760 | } |
| 1761 | |
Ping-Ke Shih | 572fd2a | 2022-10-09 20:54:02 +0800 | [diff] [blame] | 1762 | void rtw8852b_bb_set_plcp_tx(struct rtw89_dev *rtwdev) |
| 1763 | { |
| 1764 | const struct rtw89_reg3_def *def = rtw8852b_pmac_ht20_mcs7_tbl; |
| 1765 | u8 i; |
| 1766 | |
| 1767 | for (i = 0; i < ARRAY_SIZE(rtw8852b_pmac_ht20_mcs7_tbl); i++, def++) |
| 1768 | rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); |
| 1769 | } |
| 1770 | |
| 1771 | static void rtw8852b_stop_pmac_tx(struct rtw89_dev *rtwdev, |
| 1772 | struct rtw8852b_bb_pmac_info *tx_info, |
| 1773 | enum rtw89_phy_idx idx) |
| 1774 | { |
| 1775 | rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx"); |
| 1776 | if (tx_info->mode == CONT_TX) |
| 1777 | rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0, idx); |
| 1778 | else if (tx_info->mode == PKTS_TX) |
| 1779 | rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0, idx); |
| 1780 | } |
| 1781 | |
| 1782 | static void rtw8852b_start_pmac_tx(struct rtw89_dev *rtwdev, |
| 1783 | struct rtw8852b_bb_pmac_info *tx_info, |
| 1784 | enum rtw89_phy_idx idx) |
| 1785 | { |
| 1786 | enum rtw8852b_pmac_mode mode = tx_info->mode; |
| 1787 | u32 pkt_cnt = tx_info->tx_cnt; |
| 1788 | u16 period = tx_info->period; |
| 1789 | |
| 1790 | if (mode == CONT_TX && !tx_info->is_cck) { |
| 1791 | rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1, idx); |
| 1792 | rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start"); |
| 1793 | } else if (mode == PKTS_TX) { |
| 1794 | rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1, idx); |
| 1795 | rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, |
| 1796 | B_PMAC_TX_PRD_MSK, period, idx); |
| 1797 | rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK, |
| 1798 | pkt_cnt, idx); |
| 1799 | rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start"); |
| 1800 | } |
| 1801 | |
| 1802 | rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx); |
| 1803 | rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx); |
| 1804 | } |
| 1805 | |
| 1806 | void rtw8852b_bb_set_pmac_tx(struct rtw89_dev *rtwdev, |
| 1807 | struct rtw8852b_bb_pmac_info *tx_info, |
| 1808 | enum rtw89_phy_idx idx) |
| 1809 | { |
| 1810 | const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); |
| 1811 | |
| 1812 | if (!tx_info->en_pmac_tx) { |
| 1813 | rtw8852b_stop_pmac_tx(rtwdev, tx_info, idx); |
| 1814 | rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx); |
| 1815 | if (chan->band_type == RTW89_BAND_2G) |
| 1816 | rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS); |
| 1817 | return; |
| 1818 | } |
| 1819 | |
| 1820 | rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable"); |
| 1821 | |
| 1822 | rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx); |
| 1823 | rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx); |
| 1824 | rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f, idx); |
| 1825 | rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx); |
| 1826 | rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx); |
| 1827 | rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS); |
| 1828 | rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx); |
| 1829 | |
| 1830 | rtw8852b_start_pmac_tx(rtwdev, tx_info, idx); |
| 1831 | } |
| 1832 | |
| 1833 | void rtw8852b_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, |
| 1834 | u16 tx_cnt, u16 period, u16 tx_time, |
| 1835 | enum rtw89_phy_idx idx) |
| 1836 | { |
| 1837 | struct rtw8852b_bb_pmac_info tx_info = {0}; |
| 1838 | |
| 1839 | tx_info.en_pmac_tx = enable; |
| 1840 | tx_info.is_cck = 0; |
| 1841 | tx_info.mode = PKTS_TX; |
| 1842 | tx_info.tx_cnt = tx_cnt; |
| 1843 | tx_info.period = period; |
| 1844 | tx_info.tx_time = tx_time; |
| 1845 | |
| 1846 | rtw8852b_bb_set_pmac_tx(rtwdev, &tx_info, idx); |
| 1847 | } |
| 1848 | |
| 1849 | void rtw8852b_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, |
| 1850 | enum rtw89_phy_idx idx) |
| 1851 | { |
| 1852 | rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm); |
| 1853 | |
| 1854 | rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx); |
| 1855 | rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx); |
| 1856 | } |
| 1857 | |
| 1858 | void rtw8852b_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path) |
| 1859 | { |
| 1860 | rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0); |
| 1861 | |
| 1862 | rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path); |
| 1863 | |
| 1864 | if (tx_path == RF_PATH_A) { |
| 1865 | rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 1); |
| 1866 | rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0); |
| 1867 | } else if (tx_path == RF_PATH_B) { |
| 1868 | rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2); |
| 1869 | rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0); |
| 1870 | } else if (tx_path == RF_PATH_AB) { |
| 1871 | rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 3); |
| 1872 | rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4); |
| 1873 | } else { |
| 1874 | rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path"); |
| 1875 | } |
| 1876 | } |
| 1877 | |
| 1878 | void rtw8852b_bb_tx_mode_switch(struct rtw89_dev *rtwdev, |
| 1879 | enum rtw89_phy_idx idx, u8 mode) |
| 1880 | { |
| 1881 | if (mode != 0) |
| 1882 | return; |
| 1883 | |
| 1884 | rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch"); |
| 1885 | |
| 1886 | rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx); |
| 1887 | rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx); |
| 1888 | rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx); |
| 1889 | rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx); |
| 1890 | rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx); |
| 1891 | rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx); |
| 1892 | rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx); |
| 1893 | } |
| 1894 | |
| 1895 | void rtw8852b_bb_backup_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx, |
| 1896 | struct rtw8852b_bb_tssi_bak *bak) |
| 1897 | { |
| 1898 | s32 tmp; |
| 1899 | |
| 1900 | bak->tx_path = rtw89_phy_read32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, idx); |
| 1901 | bak->rx_path = rtw89_phy_read32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, idx); |
| 1902 | bak->p0_rfmode = rtw89_phy_read32_idx(rtwdev, R_P0_RFMODE, MASKDWORD, idx); |
| 1903 | bak->p0_rfmode_ftm = rtw89_phy_read32_idx(rtwdev, R_P0_RFMODE_FTM_RX, MASKDWORD, idx); |
| 1904 | bak->p1_rfmode = rtw89_phy_read32_idx(rtwdev, R_P1_RFMODE, MASKDWORD, idx); |
| 1905 | bak->p1_rfmode_ftm = rtw89_phy_read32_idx(rtwdev, R_P1_RFMODE_FTM_RX, MASKDWORD, idx); |
| 1906 | tmp = rtw89_phy_read32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, idx); |
| 1907 | bak->tx_pwr = sign_extend32(tmp, 8); |
| 1908 | } |
| 1909 | |
| 1910 | void rtw8852b_bb_restore_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx, |
| 1911 | const struct rtw8852b_bb_tssi_bak *bak) |
| 1912 | { |
| 1913 | rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, bak->tx_path, idx); |
| 1914 | if (bak->tx_path == RF_AB) |
| 1915 | rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0x4); |
| 1916 | else |
| 1917 | rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0x0); |
| 1918 | rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, bak->rx_path, idx); |
| 1919 | rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx); |
| 1920 | rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE, MASKDWORD, bak->p0_rfmode, idx); |
| 1921 | rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_FTM_RX, MASKDWORD, bak->p0_rfmode_ftm, idx); |
| 1922 | rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE, MASKDWORD, bak->p1_rfmode, idx); |
| 1923 | rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_FTM_RX, MASKDWORD, bak->p1_rfmode_ftm, idx); |
| 1924 | rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, bak->tx_pwr, idx); |
| 1925 | } |
| 1926 | |
Ping-Ke Shih | 98bf0dd | 2022-10-09 20:53:59 +0800 | [diff] [blame] | 1927 | static void rtw8852b_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en) |
| 1928 | { |
| 1929 | rtw89_phy_write_reg3_tbl(rtwdev, bt_en ? &rtw8852b_btc_preagc_en_defs_tbl : |
| 1930 | &rtw8852b_btc_preagc_dis_defs_tbl); |
| 1931 | } |
| 1932 | |
| 1933 | static void rtw8852b_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) |
| 1934 | { |
| 1935 | if (btg) { |
| 1936 | rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, |
| 1937 | B_PATH0_BT_SHARE_V1, 0x1); |
| 1938 | rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, |
| 1939 | B_PATH0_BTG_PATH_V1, 0x0); |
| 1940 | rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, |
| 1941 | B_PATH1_G_LNA6_OP1DB_V1, 0x20); |
| 1942 | rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, |
| 1943 | B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30); |
| 1944 | rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, |
| 1945 | B_PATH1_BT_SHARE_V1, 0x1); |
| 1946 | rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, |
| 1947 | B_PATH1_BTG_PATH_V1, 0x1); |
| 1948 | rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); |
| 1949 | rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x1); |
| 1950 | rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x2); |
| 1951 | rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1, |
| 1952 | B_BT_DYN_DC_EST_EN_MSK, 0x1); |
| 1953 | rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x1); |
| 1954 | } else { |
| 1955 | rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, |
| 1956 | B_PATH0_BT_SHARE_V1, 0x0); |
| 1957 | rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, |
| 1958 | B_PATH0_BTG_PATH_V1, 0x0); |
| 1959 | rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, |
| 1960 | B_PATH1_G_LNA6_OP1DB_V1, 0x1a); |
| 1961 | rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, |
| 1962 | B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); |
| 1963 | rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, |
| 1964 | B_PATH1_BT_SHARE_V1, 0x0); |
| 1965 | rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, |
| 1966 | B_PATH1_BTG_PATH_V1, 0x0); |
| 1967 | rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc); |
| 1968 | rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0); |
| 1969 | rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0); |
| 1970 | rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1, |
| 1971 | B_BT_DYN_DC_EST_EN_MSK, 0x1); |
| 1972 | rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0); |
| 1973 | } |
| 1974 | } |
| 1975 | |
Ping-Ke Shih | 8915a25 | 2022-10-09 20:54:01 +0800 | [diff] [blame] | 1976 | void rtw8852b_bb_ctrl_rx_path(struct rtw89_dev *rtwdev, |
| 1977 | enum rtw89_rf_path_bit rx_path) |
| 1978 | { |
| 1979 | const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); |
| 1980 | u32 rst_mask0; |
| 1981 | u32 rst_mask1; |
| 1982 | |
| 1983 | if (rx_path == RF_A) { |
| 1984 | rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 1); |
| 1985 | rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 1); |
| 1986 | rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 1); |
| 1987 | rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); |
| 1988 | rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); |
| 1989 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4); |
| 1990 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); |
| 1991 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); |
| 1992 | } else if (rx_path == RF_B) { |
| 1993 | rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 2); |
| 1994 | rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 2); |
| 1995 | rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 2); |
| 1996 | rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); |
| 1997 | rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); |
| 1998 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4); |
| 1999 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); |
| 2000 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); |
| 2001 | } else if (rx_path == RF_AB) { |
| 2002 | rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 3); |
| 2003 | rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 3); |
| 2004 | rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 3); |
| 2005 | rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1); |
| 2006 | rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1); |
| 2007 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4); |
| 2008 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1); |
| 2009 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1); |
| 2010 | } |
| 2011 | |
| 2012 | rtw8852b_set_gain_offset(rtwdev, chan->subband_type, RTW89_PHY_0); |
| 2013 | |
| 2014 | if (chan->band_type == RTW89_BAND_2G && |
| 2015 | (rx_path == RF_B || rx_path == RF_AB)) |
| 2016 | rtw8852b_ctrl_btg(rtwdev, true); |
| 2017 | else |
| 2018 | rtw8852b_ctrl_btg(rtwdev, false); |
| 2019 | |
| 2020 | rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; |
| 2021 | rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; |
| 2022 | if (rx_path == RF_A) { |
| 2023 | rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); |
| 2024 | rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); |
| 2025 | } else { |
| 2026 | rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); |
| 2027 | rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); |
| 2028 | } |
| 2029 | } |
| 2030 | |
| 2031 | static void rtw8852b_bb_ctrl_rf_mode_rx_path(struct rtw89_dev *rtwdev, |
| 2032 | enum rtw89_rf_path_bit rx_path) |
| 2033 | { |
| 2034 | if (rx_path == RF_A) { |
| 2035 | rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, |
| 2036 | B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1233312); |
| 2037 | rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX, |
| 2038 | B_P0_RFMODE_FTM_RX, 0x333); |
| 2039 | rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, |
| 2040 | B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1111111); |
| 2041 | rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX, |
| 2042 | B_P1_RFMODE_FTM_RX, 0x111); |
| 2043 | } else if (rx_path == RF_B) { |
| 2044 | rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, |
| 2045 | B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1111111); |
| 2046 | rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX, |
| 2047 | B_P0_RFMODE_FTM_RX, 0x111); |
| 2048 | rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, |
| 2049 | B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1233312); |
| 2050 | rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX, |
| 2051 | B_P1_RFMODE_FTM_RX, 0x333); |
| 2052 | } else if (rx_path == RF_AB) { |
| 2053 | rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, |
| 2054 | B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1233312); |
| 2055 | rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX, |
| 2056 | B_P0_RFMODE_FTM_RX, 0x333); |
| 2057 | rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, |
| 2058 | B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1233312); |
| 2059 | rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX, |
| 2060 | B_P1_RFMODE_FTM_RX, 0x333); |
| 2061 | } |
| 2062 | } |
| 2063 | |
| 2064 | static void rtw8852b_bb_cfg_txrx_path(struct rtw89_dev *rtwdev) |
| 2065 | { |
| 2066 | struct rtw89_hal *hal = &rtwdev->hal; |
| 2067 | enum rtw89_rf_path_bit rx_path = hal->antenna_rx ? hal->antenna_rx : RF_AB; |
| 2068 | |
| 2069 | rtw8852b_bb_ctrl_rx_path(rtwdev, rx_path); |
| 2070 | rtw8852b_bb_ctrl_rf_mode_rx_path(rtwdev, rx_path); |
| 2071 | |
| 2072 | if (rtwdev->hal.rx_nss == 1) { |
| 2073 | rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); |
| 2074 | rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); |
| 2075 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); |
| 2076 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); |
| 2077 | } else { |
| 2078 | rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1); |
| 2079 | rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1); |
| 2080 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1); |
| 2081 | rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1); |
| 2082 | } |
| 2083 | |
| 2084 | rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0); |
| 2085 | } |
| 2086 | |
Ping-Ke Shih | 8f88474 | 2022-10-09 20:53:58 +0800 | [diff] [blame] | 2087 | static u8 rtw8852b_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) |
| 2088 | { |
| 2089 | if (rtwdev->is_tssi_mode[rf_path]) { |
| 2090 | u32 addr = 0x1c10 + (rf_path << 13); |
| 2091 | |
| 2092 | return rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000); |
| 2093 | } |
| 2094 | |
| 2095 | rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); |
| 2096 | rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); |
| 2097 | rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); |
| 2098 | |
| 2099 | fsleep(200); |
| 2100 | |
| 2101 | return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); |
| 2102 | } |
| 2103 | |
Ping-Ke Shih | 98bf0dd | 2022-10-09 20:53:59 +0800 | [diff] [blame] | 2104 | static void rtw8852b_btc_set_rfe(struct rtw89_dev *rtwdev) |
| 2105 | { |
| 2106 | struct rtw89_btc *btc = &rtwdev->btc; |
| 2107 | struct rtw89_btc_module *module = &btc->mdinfo; |
| 2108 | |
| 2109 | module->rfe_type = rtwdev->efuse.rfe_type; |
| 2110 | module->cv = rtwdev->hal.cv; |
| 2111 | module->bt_solo = 0; |
| 2112 | module->switch_type = BTC_SWITCH_INTERNAL; |
| 2113 | |
| 2114 | if (module->rfe_type > 0) |
| 2115 | module->ant.num = module->rfe_type % 2 ? 2 : 3; |
| 2116 | else |
| 2117 | module->ant.num = 2; |
| 2118 | |
| 2119 | module->ant.diversity = 0; |
| 2120 | module->ant.isolation = 10; |
| 2121 | |
| 2122 | if (module->ant.num == 3) { |
| 2123 | module->ant.type = BTC_ANT_DEDICATED; |
| 2124 | module->bt_pos = BTC_BT_ALONE; |
| 2125 | } else { |
| 2126 | module->ant.type = BTC_ANT_SHARED; |
| 2127 | module->bt_pos = BTC_BT_BTG; |
| 2128 | } |
| 2129 | } |
| 2130 | |
| 2131 | static |
| 2132 | void rtw8852b_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) |
| 2133 | { |
| 2134 | rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000); |
| 2135 | rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group); |
| 2136 | rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val); |
| 2137 | rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0); |
| 2138 | } |
| 2139 | |
| 2140 | static void rtw8852b_btc_init_cfg(struct rtw89_dev *rtwdev) |
| 2141 | { |
| 2142 | struct rtw89_btc *btc = &rtwdev->btc; |
| 2143 | struct rtw89_btc_module *module = &btc->mdinfo; |
| 2144 | const struct rtw89_chip_info *chip = rtwdev->chip; |
| 2145 | const struct rtw89_mac_ax_coex coex_params = { |
| 2146 | .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, |
| 2147 | .direction = RTW89_MAC_AX_COEX_INNER, |
| 2148 | }; |
| 2149 | |
| 2150 | /* PTA init */ |
| 2151 | rtw89_mac_coex_init(rtwdev, &coex_params); |
| 2152 | |
| 2153 | /* set WL Tx response = Hi-Pri */ |
| 2154 | chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); |
| 2155 | chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); |
| 2156 | |
| 2157 | /* set rf gnt debug off */ |
| 2158 | rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0); |
| 2159 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0); |
| 2160 | |
| 2161 | /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ |
| 2162 | if (module->ant.type == BTC_ANT_SHARED) { |
| 2163 | rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); |
| 2164 | rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); |
| 2165 | /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ |
| 2166 | rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); |
| 2167 | rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_TX_GROUP, 0x55f); |
| 2168 | } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ |
| 2169 | rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); |
| 2170 | rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); |
| 2171 | rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); |
| 2172 | rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_TX_GROUP, 0x5ff); |
| 2173 | } |
| 2174 | |
| 2175 | /* set PTA break table */ |
| 2176 | rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM); |
| 2177 | |
| 2178 | /* enable BT counter 0xda40[16,2] = 2b'11 */ |
| 2179 | rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN); |
| 2180 | btc->cx.wl.status.map.init_ok = true; |
| 2181 | } |
| 2182 | |
| 2183 | static |
| 2184 | void rtw8852b_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) |
| 2185 | { |
| 2186 | u32 bitmap; |
| 2187 | u32 reg; |
| 2188 | |
| 2189 | switch (map) { |
| 2190 | case BTC_PRI_MASK_TX_RESP: |
| 2191 | reg = R_BTC_BT_COEX_MSK_TABLE; |
| 2192 | bitmap = B_BTC_PRI_MASK_TX_RESP_V1; |
| 2193 | break; |
| 2194 | case BTC_PRI_MASK_BEACON: |
| 2195 | reg = R_AX_WL_PRI_MSK; |
| 2196 | bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ; |
| 2197 | break; |
| 2198 | case BTC_PRI_MASK_RX_CCK: |
| 2199 | reg = R_BTC_BT_COEX_MSK_TABLE; |
| 2200 | bitmap = B_BTC_PRI_MASK_RXCCK_V1; |
| 2201 | break; |
| 2202 | default: |
| 2203 | return; |
| 2204 | } |
| 2205 | |
| 2206 | if (state) |
| 2207 | rtw89_write32_set(rtwdev, reg, bitmap); |
| 2208 | else |
| 2209 | rtw89_write32_clr(rtwdev, reg, bitmap); |
| 2210 | } |
| 2211 | |
| 2212 | union rtw8852b_btc_wl_txpwr_ctrl { |
| 2213 | u32 txpwr_val; |
| 2214 | struct { |
| 2215 | union { |
| 2216 | u16 ctrl_all_time; |
| 2217 | struct { |
| 2218 | s16 data:9; |
| 2219 | u16 rsvd:6; |
| 2220 | u16 flag:1; |
| 2221 | } all_time; |
| 2222 | }; |
| 2223 | union { |
| 2224 | u16 ctrl_gnt_bt; |
| 2225 | struct { |
| 2226 | s16 data:9; |
| 2227 | u16 rsvd:7; |
| 2228 | } gnt_bt; |
| 2229 | }; |
| 2230 | }; |
| 2231 | } __packed; |
| 2232 | |
| 2233 | static void |
| 2234 | rtw8852b_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) |
| 2235 | { |
| 2236 | union rtw8852b_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val }; |
| 2237 | s32 val; |
| 2238 | |
| 2239 | #define __write_ctrl(_reg, _msk, _val, _en, _cond) \ |
| 2240 | do { \ |
| 2241 | u32 _wrt = FIELD_PREP(_msk, _val); \ |
| 2242 | BUILD_BUG_ON(!!(_msk & _en)); \ |
| 2243 | if (_cond) \ |
| 2244 | _wrt |= _en; \ |
| 2245 | else \ |
| 2246 | _wrt &= ~_en; \ |
| 2247 | rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \ |
| 2248 | _msk | _en, _wrt); \ |
| 2249 | } while (0) |
| 2250 | |
| 2251 | switch (arg.ctrl_all_time) { |
| 2252 | case 0xffff: |
| 2253 | val = 0; |
| 2254 | break; |
| 2255 | default: |
| 2256 | val = arg.all_time.data; |
| 2257 | break; |
| 2258 | } |
| 2259 | |
| 2260 | __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK, |
| 2261 | val, B_AX_FORCE_PWR_BY_RATE_EN, |
| 2262 | arg.ctrl_all_time != 0xffff); |
| 2263 | |
| 2264 | switch (arg.ctrl_gnt_bt) { |
| 2265 | case 0xffff: |
| 2266 | val = 0; |
| 2267 | break; |
| 2268 | default: |
| 2269 | val = arg.gnt_bt.data; |
| 2270 | break; |
| 2271 | } |
| 2272 | |
| 2273 | __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val, |
| 2274 | B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff); |
| 2275 | |
| 2276 | #undef __write_ctrl |
| 2277 | } |
| 2278 | |
| 2279 | static |
| 2280 | s8 rtw8852b_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) |
| 2281 | { |
Ching-Te Ku | 2380a220 | 2023-04-12 09:28:30 +0800 | [diff] [blame] | 2282 | /* +6 for compensate offset */ |
| 2283 | return clamp_t(s8, val + 6, -100, 0) + 100; |
Ping-Ke Shih | 98bf0dd | 2022-10-09 20:53:59 +0800 | [diff] [blame] | 2284 | } |
| 2285 | |
| 2286 | static |
| 2287 | void rtw8852b_btc_update_bt_cnt(struct rtw89_dev *rtwdev) |
| 2288 | { |
| 2289 | /* Feature move to firmware */ |
| 2290 | } |
| 2291 | |
| 2292 | static void rtw8852b_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) |
| 2293 | { |
| 2294 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); |
| 2295 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); |
| 2296 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x31); |
| 2297 | |
| 2298 | /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ |
| 2299 | if (state) |
Ching-Te Ku | 20595db | 2023-03-14 10:06:15 +0800 | [diff] [blame] | 2300 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x179); |
Ping-Ke Shih | 98bf0dd | 2022-10-09 20:53:59 +0800 | [diff] [blame] | 2301 | else |
| 2302 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x20); |
| 2303 | |
| 2304 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); |
| 2305 | } |
| 2306 | |
Ching-Te Ku | 20595db | 2023-03-14 10:06:15 +0800 | [diff] [blame] | 2307 | static void rtw8852b_btc_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level) |
| 2308 | { |
| 2309 | switch (level) { |
| 2310 | case 0: /* default */ |
| 2311 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); |
| 2312 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); |
| 2313 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); |
| 2314 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); |
| 2315 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); |
| 2316 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); |
| 2317 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); |
| 2318 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); |
| 2319 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); |
| 2320 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); |
| 2321 | break; |
| 2322 | case 1: /* Fix LNA2=5 */ |
| 2323 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); |
| 2324 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); |
| 2325 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); |
| 2326 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); |
| 2327 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); |
| 2328 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); |
| 2329 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); |
| 2330 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); |
| 2331 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); |
| 2332 | rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); |
| 2333 | break; |
| 2334 | } |
| 2335 | } |
| 2336 | |
Ping-Ke Shih | 98bf0dd | 2022-10-09 20:53:59 +0800 | [diff] [blame] | 2337 | static void rtw8852b_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) |
| 2338 | { |
Ching-Te Ku | 20595db | 2023-03-14 10:06:15 +0800 | [diff] [blame] | 2339 | struct rtw89_btc *btc = &rtwdev->btc; |
| 2340 | |
| 2341 | switch (level) { |
| 2342 | case 0: /* original */ |
| 2343 | default: |
| 2344 | rtw8852b_bb_ctrl_btc_preagc(rtwdev, false); |
| 2345 | btc->dm.wl_lna2 = 0; |
| 2346 | break; |
| 2347 | case 1: /* for FDD free-run */ |
| 2348 | rtw8852b_bb_ctrl_btc_preagc(rtwdev, true); |
| 2349 | btc->dm.wl_lna2 = 0; |
| 2350 | break; |
| 2351 | case 2: /* for BTG Co-Rx*/ |
| 2352 | rtw8852b_bb_ctrl_btc_preagc(rtwdev, false); |
| 2353 | btc->dm.wl_lna2 = 1; |
| 2354 | break; |
| 2355 | } |
| 2356 | |
| 2357 | rtw8852b_btc_set_wl_lna2(rtwdev, btc->dm.wl_lna2); |
Ping-Ke Shih | 98bf0dd | 2022-10-09 20:53:59 +0800 | [diff] [blame] | 2358 | } |
| 2359 | |
Ping-Ke Shih | bf958f7 | 2022-10-09 20:54:00 +0800 | [diff] [blame] | 2360 | static void rtw8852b_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, |
| 2361 | struct rtw89_rx_phy_ppdu *phy_ppdu, |
| 2362 | struct ieee80211_rx_status *status) |
| 2363 | { |
| 2364 | u16 chan = phy_ppdu->chan_idx; |
Po-Hao Huang | 4f24d7a | 2023-02-20 15:02:00 +0800 | [diff] [blame] | 2365 | enum nl80211_band band; |
| 2366 | u8 ch; |
Ping-Ke Shih | bf958f7 | 2022-10-09 20:54:00 +0800 | [diff] [blame] | 2367 | |
| 2368 | if (chan == 0) |
| 2369 | return; |
| 2370 | |
Po-Hao Huang | 4f24d7a | 2023-02-20 15:02:00 +0800 | [diff] [blame] | 2371 | rtw89_decode_chan_idx(rtwdev, chan, &ch, &band); |
| 2372 | status->freq = ieee80211_channel_to_frequency(ch, band); |
Ping-Ke Shih | bf958f7 | 2022-10-09 20:54:00 +0800 | [diff] [blame] | 2373 | status->band = band; |
| 2374 | } |
| 2375 | |
| 2376 | static void rtw8852b_query_ppdu(struct rtw89_dev *rtwdev, |
| 2377 | struct rtw89_rx_phy_ppdu *phy_ppdu, |
| 2378 | struct ieee80211_rx_status *status) |
| 2379 | { |
| 2380 | u8 path; |
| 2381 | u8 *rx_power = phy_ppdu->rssi; |
| 2382 | |
| 2383 | status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B])); |
| 2384 | for (path = 0; path < rtwdev->chip->rf_path_num; path++) { |
| 2385 | status->chains |= BIT(path); |
| 2386 | status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); |
| 2387 | } |
| 2388 | if (phy_ppdu->valid) |
| 2389 | rtw8852b_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); |
| 2390 | } |
| 2391 | |
Ping-Ke Shih | 14b6e9f | 2022-09-27 14:26:06 +0800 | [diff] [blame] | 2392 | static int rtw8852b_mac_enable_bb_rf(struct rtw89_dev *rtwdev) |
| 2393 | { |
| 2394 | int ret; |
| 2395 | |
| 2396 | rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, |
| 2397 | B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); |
| 2398 | rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x1); |
| 2399 | rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); |
| 2400 | rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); |
| 2401 | rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); |
| 2402 | |
| 2403 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC7, |
| 2404 | FULL_BIT_MASK); |
| 2405 | if (ret) |
| 2406 | return ret; |
| 2407 | |
| 2408 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC7, |
| 2409 | FULL_BIT_MASK); |
| 2410 | if (ret) |
| 2411 | return ret; |
| 2412 | |
| 2413 | rtw89_write8(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_XYN_CYCLE); |
| 2414 | |
| 2415 | return 0; |
| 2416 | } |
| 2417 | |
| 2418 | static int rtw8852b_mac_disable_bb_rf(struct rtw89_dev *rtwdev) |
| 2419 | { |
| 2420 | u8 wl_rfc_s0; |
| 2421 | u8 wl_rfc_s1; |
| 2422 | int ret; |
| 2423 | |
| 2424 | rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, |
| 2425 | B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); |
| 2426 | |
| 2427 | ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, &wl_rfc_s0); |
| 2428 | if (ret) |
| 2429 | return ret; |
| 2430 | wl_rfc_s0 &= ~XTAL_SI_RF00S_EN; |
| 2431 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, wl_rfc_s0, |
| 2432 | FULL_BIT_MASK); |
| 2433 | if (ret) |
| 2434 | return ret; |
| 2435 | |
| 2436 | ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, &wl_rfc_s1); |
| 2437 | if (ret) |
| 2438 | return ret; |
| 2439 | wl_rfc_s1 &= ~XTAL_SI_RF10S_EN; |
| 2440 | ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, wl_rfc_s1, |
| 2441 | FULL_BIT_MASK); |
| 2442 | return ret; |
| 2443 | } |
| 2444 | |
| 2445 | static const struct rtw89_chip_ops rtw8852b_chip_ops = { |
| 2446 | .enable_bb_rf = rtw8852b_mac_enable_bb_rf, |
| 2447 | .disable_bb_rf = rtw8852b_mac_disable_bb_rf, |
Ping-Ke Shih | a804479 | 2022-10-09 20:53:57 +0800 | [diff] [blame] | 2448 | .bb_reset = rtw8852b_bb_reset, |
| 2449 | .bb_sethw = rtw8852b_bb_sethw, |
Ping-Ke Shih | b8fe87b | 2022-10-09 20:54:03 +0800 | [diff] [blame] | 2450 | .read_rf = rtw89_phy_read_rf_v1, |
| 2451 | .write_rf = rtw89_phy_write_rf_v1, |
Ping-Ke Shih | 6b06989 | 2022-10-05 16:32:12 +0800 | [diff] [blame] | 2452 | .set_channel = rtw8852b_set_channel, |
Ping-Ke Shih | d0a95ef | 2022-10-09 20:53:55 +0800 | [diff] [blame] | 2453 | .set_channel_help = rtw8852b_set_channel_help, |
Ping-Ke Shih | 132dc4f | 2022-09-28 16:43:34 +0800 | [diff] [blame] | 2454 | .read_efuse = rtw8852b_read_efuse, |
Ping-Ke Shih | 134cf7c | 2022-09-28 16:43:35 +0800 | [diff] [blame] | 2455 | .read_phycap = rtw8852b_read_phycap, |
Ping-Ke Shih | b8fe87b | 2022-10-09 20:54:03 +0800 | [diff] [blame] | 2456 | .fem_setup = NULL, |
Ping-Ke Shih | ef8acbc | 2022-10-14 14:02:35 +0800 | [diff] [blame] | 2457 | .rfk_init = rtw8852b_rfk_init, |
| 2458 | .rfk_channel = rtw8852b_rfk_channel, |
| 2459 | .rfk_band_changed = rtw8852b_rfk_band_changed, |
| 2460 | .rfk_scan = rtw8852b_rfk_scan, |
| 2461 | .rfk_track = rtw8852b_rfk_track, |
Ping-Ke Shih | 134cf7c | 2022-09-28 16:43:35 +0800 | [diff] [blame] | 2462 | .power_trim = rtw8852b_power_trim, |
Ping-Ke Shih | 08484e1 | 2022-09-28 16:43:33 +0800 | [diff] [blame] | 2463 | .set_txpwr = rtw8852b_set_txpwr, |
| 2464 | .set_txpwr_ctrl = rtw8852b_set_txpwr_ctrl, |
| 2465 | .init_txpwr_unit = rtw8852b_init_txpwr_unit, |
Ping-Ke Shih | 8f88474 | 2022-10-09 20:53:58 +0800 | [diff] [blame] | 2466 | .get_thermal = rtw8852b_get_thermal, |
Ping-Ke Shih | 98bf0dd | 2022-10-09 20:53:59 +0800 | [diff] [blame] | 2467 | .ctrl_btg = rtw8852b_ctrl_btg, |
Ping-Ke Shih | bf958f7 | 2022-10-09 20:54:00 +0800 | [diff] [blame] | 2468 | .query_ppdu = rtw8852b_query_ppdu, |
Ping-Ke Shih | 98bf0dd | 2022-10-09 20:53:59 +0800 | [diff] [blame] | 2469 | .bb_ctrl_btc_preagc = rtw8852b_bb_ctrl_btc_preagc, |
Ping-Ke Shih | 8915a25 | 2022-10-09 20:54:01 +0800 | [diff] [blame] | 2470 | .cfg_txrx_path = rtw8852b_bb_cfg_txrx_path, |
Ping-Ke Shih | b8fe87b | 2022-10-09 20:54:03 +0800 | [diff] [blame] | 2471 | .set_txpwr_ul_tb_offset = rtw8852b_set_txpwr_ul_tb_offset, |
Ping-Ke Shih | b23b36e | 2022-10-09 20:53:56 +0800 | [diff] [blame] | 2472 | .pwr_on_func = rtw8852b_pwr_on_func, |
| 2473 | .pwr_off_func = rtw8852b_pwr_off_func, |
Ping-Ke Shih | b8fe87b | 2022-10-09 20:54:03 +0800 | [diff] [blame] | 2474 | .fill_txdesc = rtw89_core_fill_txdesc, |
| 2475 | .fill_txdesc_fwcmd = rtw89_core_fill_txdesc, |
| 2476 | .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path, |
| 2477 | .mac_cfg_gnt = rtw89_mac_cfg_gnt, |
| 2478 | .stop_sch_tx = rtw89_mac_stop_sch_tx, |
| 2479 | .resume_sch_tx = rtw89_mac_resume_sch_tx, |
| 2480 | .h2c_dctl_sec_cam = NULL, |
Ping-Ke Shih | 98bf0dd | 2022-10-09 20:53:59 +0800 | [diff] [blame] | 2481 | |
| 2482 | .btc_set_rfe = rtw8852b_btc_set_rfe, |
| 2483 | .btc_init_cfg = rtw8852b_btc_init_cfg, |
| 2484 | .btc_set_wl_pri = rtw8852b_btc_set_wl_pri, |
| 2485 | .btc_set_wl_txpwr_ctrl = rtw8852b_btc_set_wl_txpwr_ctrl, |
| 2486 | .btc_get_bt_rssi = rtw8852b_btc_get_bt_rssi, |
| 2487 | .btc_update_bt_cnt = rtw8852b_btc_update_bt_cnt, |
| 2488 | .btc_wl_s1_standby = rtw8852b_btc_wl_s1_standby, |
| 2489 | .btc_set_wl_rx_gain = rtw8852b_btc_set_wl_rx_gain, |
Ching-Te Ku | 447a326 | 2023-01-06 20:08:43 +0800 | [diff] [blame] | 2490 | .btc_set_policy = rtw89_btc_set_policy_v1, |
Ping-Ke Shih | 14b6e9f | 2022-09-27 14:26:06 +0800 | [diff] [blame] | 2491 | }; |
Ping-Ke Shih | a1b7163 | 2022-09-27 14:26:04 +0800 | [diff] [blame] | 2492 | |
Chin-Yen Lee | 6863ad9 | 2023-04-10 13:34:37 +0800 | [diff] [blame] | 2493 | #ifdef CONFIG_PM |
| 2494 | static const struct wiphy_wowlan_support rtw_wowlan_stub_8852b = { |
| 2495 | .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, |
| 2496 | .n_patterns = RTW89_MAX_PATTERN_NUM, |
| 2497 | .pattern_max_len = RTW89_MAX_PATTERN_SIZE, |
| 2498 | .pattern_min_len = 1, |
| 2499 | }; |
| 2500 | #endif |
| 2501 | |
Ping-Ke Shih | a1b7163 | 2022-09-27 14:26:04 +0800 | [diff] [blame] | 2502 | const struct rtw89_chip_info rtw8852b_chip_info = { |
| 2503 | .chip_id = RTL8852B, |
Ping-Ke Shih | 08484e1 | 2022-09-28 16:43:33 +0800 | [diff] [blame] | 2504 | .ops = &rtw8852b_chip_ops, |
Ping-Ke Shih | ffde7f3 | 2023-03-20 21:06:06 +0800 | [diff] [blame] | 2505 | .fw_basename = RTW8852B_FW_BASENAME, |
| 2506 | .fw_format_max = RTW8852B_FW_FORMAT_MAX, |
Ping-Ke Shih | 7410bd7 | 2023-01-23 14:54:01 +0800 | [diff] [blame] | 2507 | .try_ce_fw = true, |
Ping-Ke Shih | 5f8c35b | 2022-09-27 14:26:10 +0800 | [diff] [blame] | 2508 | .fifo_size = 196608, |
| 2509 | .dle_scc_rsvd_size = 98304, |
Ping-Ke Shih | b8fe87b | 2022-10-09 20:54:03 +0800 | [diff] [blame] | 2510 | .max_amsdu_limit = 3500, |
| 2511 | .dis_2g_40m_ul_ofdma = true, |
| 2512 | .rsvd_ple_ofst = 0x2f800, |
Ping-Ke Shih | 3e870b4 | 2022-10-05 16:32:10 +0800 | [diff] [blame] | 2513 | .hfc_param_ini = rtw8852b_hfc_param_ini_pcie, |
Ping-Ke Shih | a1cb097 | 2022-09-27 14:26:11 +0800 | [diff] [blame] | 2514 | .dle_mem = rtw8852b_dle_mem_pcie, |
Zong-Zhe Yang | a3edb201 | 2023-01-13 17:06:32 +0800 | [diff] [blame] | 2515 | .wde_qempty_acq_num = 4, |
| 2516 | .wde_qempty_mgq_sel = 4, |
Ping-Ke Shih | b8fe87b | 2022-10-09 20:54:03 +0800 | [diff] [blame] | 2517 | .rf_base_addr = {0xe000, 0xf000}, |
Ping-Ke Shih | b23b36e | 2022-10-09 20:53:56 +0800 | [diff] [blame] | 2518 | .pwr_on_seq = NULL, |
| 2519 | .pwr_off_seq = NULL, |
Ping-Ke Shih | b8fe87b | 2022-10-09 20:54:03 +0800 | [diff] [blame] | 2520 | .bb_table = &rtw89_8852b_phy_bb_table, |
| 2521 | .bb_gain_table = &rtw89_8852b_phy_bb_gain_table, |
| 2522 | .rf_table = {&rtw89_8852b_phy_radioa_table, |
| 2523 | &rtw89_8852b_phy_radiob_table,}, |
| 2524 | .nctl_table = &rtw89_8852b_phy_nctl_table, |
| 2525 | .byr_table = &rtw89_8852b_byr_table, |
Zong-Zhe Yang | 5395482 | 2023-03-30 16:03:31 +0800 | [diff] [blame] | 2526 | .dflt_parms = &rtw89_8852b_dflt_parms, |
| 2527 | .rfe_parms_conf = NULL, |
Ping-Ke Shih | b8fe87b | 2022-10-09 20:54:03 +0800 | [diff] [blame] | 2528 | .txpwr_factor_rf = 2, |
| 2529 | .txpwr_factor_mac = 1, |
| 2530 | .dig_table = NULL, |
| 2531 | .dig_regs = &rtw8852b_dig_regs, |
| 2532 | .tssi_dbw_table = NULL, |
| 2533 | .support_chanctx_num = 0, |
| 2534 | .support_bands = BIT(NL80211_BAND_2GHZ) | |
| 2535 | BIT(NL80211_BAND_5GHZ), |
| 2536 | .support_bw160 = false, |
Eric Huang | 29136c9 | 2022-11-17 14:30:01 +0800 | [diff] [blame] | 2537 | .support_ul_tb_ctrl = true, |
Ping-Ke Shih | b8fe87b | 2022-10-09 20:54:03 +0800 | [diff] [blame] | 2538 | .hw_sec_hdr = false, |
| 2539 | .rf_path_num = 2, |
| 2540 | .tx_nss = 2, |
| 2541 | .rx_nss = 2, |
| 2542 | .acam_num = 128, |
| 2543 | .bcam_num = 10, |
| 2544 | .scam_num = 128, |
| 2545 | .bacam_num = 2, |
| 2546 | .bacam_dynamic_num = 4, |
| 2547 | .bacam_v1 = false, |
Ping-Ke Shih | 132dc4f | 2022-09-28 16:43:34 +0800 | [diff] [blame] | 2548 | .sec_ctrl_efuse_size = 4, |
| 2549 | .physical_efuse_size = 1216, |
| 2550 | .logical_efuse_size = 2048, |
| 2551 | .limit_efuse_size = 1280, |
| 2552 | .dav_phy_efuse_size = 96, |
| 2553 | .dav_log_efuse_size = 16, |
Ping-Ke Shih | 134cf7c | 2022-09-28 16:43:35 +0800 | [diff] [blame] | 2554 | .phycap_addr = 0x580, |
| 2555 | .phycap_size = 128, |
Ping-Ke Shih | b8fe87b | 2022-10-09 20:54:03 +0800 | [diff] [blame] | 2556 | .para_ver = 0, |
| 2557 | .wlcx_desired = 0x05050000, |
| 2558 | .btcx_desired = 0x5, |
| 2559 | .scbd = 0x1, |
| 2560 | .mailbox = 0x1, |
Ping-Ke Shih | b8fe87b | 2022-10-09 20:54:03 +0800 | [diff] [blame] | 2561 | |
Ping-Ke Shih | b8fe87b | 2022-10-09 20:54:03 +0800 | [diff] [blame] | 2562 | .afh_guard_ch = 6, |
| 2563 | .wl_rssi_thres = rtw89_btc_8852b_wl_rssi_thres, |
| 2564 | .bt_rssi_thres = rtw89_btc_8852b_bt_rssi_thres, |
| 2565 | .rssi_tol = 2, |
| 2566 | .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852b_mon_reg), |
| 2567 | .mon_reg = rtw89_btc_8852b_mon_reg, |
| 2568 | .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852b_rf_ul), |
| 2569 | .rf_para_ulink = rtw89_btc_8852b_rf_ul, |
| 2570 | .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852b_rf_dl), |
| 2571 | .rf_para_dlink = rtw89_btc_8852b_rf_dl, |
| 2572 | .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | |
| 2573 | BIT(RTW89_PS_MODE_CLK_GATED) | |
| 2574 | BIT(RTW89_PS_MODE_PWR_GATED), |
| 2575 | .low_power_hci_modes = 0, |
| 2576 | .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD, |
| 2577 | .hci_func_en_addr = R_AX_HCI_FUNC_EN, |
| 2578 | .h2c_desc_size = sizeof(struct rtw89_txwd_body), |
| 2579 | .txwd_body_size = sizeof(struct rtw89_txwd_body), |
| 2580 | .h2c_ctrl_reg = R_AX_H2CREG_CTRL, |
Ping-Ke Shih | e749ef9 | 2023-03-16 14:39:56 +0800 | [diff] [blame] | 2581 | .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, |
Ping-Ke Shih | b8fe87b | 2022-10-09 20:54:03 +0800 | [diff] [blame] | 2582 | .h2c_regs = rtw8852b_h2c_regs, |
| 2583 | .c2h_ctrl_reg = R_AX_C2HREG_CTRL, |
Ping-Ke Shih | e749ef9 | 2023-03-16 14:39:56 +0800 | [diff] [blame] | 2584 | .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, |
Ping-Ke Shih | b8fe87b | 2022-10-09 20:54:03 +0800 | [diff] [blame] | 2585 | .c2h_regs = rtw8852b_c2h_regs, |
| 2586 | .page_regs = &rtw8852b_page_regs, |
Eric Huang | 10cd409 | 2022-11-17 14:30:00 +0800 | [diff] [blame] | 2587 | .cfo_src_fd = true, |
Eric Huang | 9f9882d | 2023-03-30 21:23:52 +0800 | [diff] [blame] | 2588 | .cfo_hw_comp = true, |
Ping-Ke Shih | b8fe87b | 2022-10-09 20:54:03 +0800 | [diff] [blame] | 2589 | .dcfo_comp = &rtw8852b_dcfo_comp, |
Eric Huang | 9f9882d | 2023-03-30 21:23:52 +0800 | [diff] [blame] | 2590 | .dcfo_comp_sft = 10, |
Ping-Ke Shih | b8fe87b | 2022-10-09 20:54:03 +0800 | [diff] [blame] | 2591 | .imr_info = &rtw8852b_imr_info, |
| 2592 | .rrsr_cfgs = &rtw8852b_rrsr_cfgs, |
Eric Huang | a48f4fd | 2022-12-14 17:18:03 +0800 | [diff] [blame] | 2593 | .bss_clr_map_reg = R_BSS_CLR_MAP_V1, |
Ping-Ke Shih | a1b7163 | 2022-09-27 14:26:04 +0800 | [diff] [blame] | 2594 | .dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) | |
| 2595 | BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) | |
| 2596 | BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI), |
Chih-Kang Chang | 280c444 | 2023-03-22 14:02:38 +0800 | [diff] [blame] | 2597 | .edcca_lvl_reg = R_SEG0R_EDCCA_LVL_V1, |
Chin-Yen Lee | 6863ad9 | 2023-04-10 13:34:37 +0800 | [diff] [blame] | 2598 | #ifdef CONFIG_PM |
| 2599 | .wowlan_stub = &rtw_wowlan_stub_8852b, |
| 2600 | #endif |
Ping-Ke Shih | a1b7163 | 2022-09-27 14:26:04 +0800 | [diff] [blame] | 2601 | }; |
| 2602 | EXPORT_SYMBOL(rtw8852b_chip_info); |
| 2603 | |
Ping-Ke Shih | ffde7f3 | 2023-03-20 21:06:06 +0800 | [diff] [blame] | 2604 | MODULE_FIRMWARE(RTW8852B_MODULE_FIRMWARE); |
Ping-Ke Shih | a1b7163 | 2022-09-27 14:26:04 +0800 | [diff] [blame] | 2605 | MODULE_AUTHOR("Realtek Corporation"); |
| 2606 | MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852B driver"); |
| 2607 | MODULE_LICENSE("Dual BSD/GPL"); |