blob: 44e0a319f0770a08d0973e94935bf56e54fce27f [file] [log] [blame]
Thomas Gleixnerc942fdd2019-05-27 08:55:06 +02001/* SPDX-License-Identifier: GPL-2.0-or-later */
Xing Zhengf35f6222016-03-28 17:51:36 +08002/*
3 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
4 * Author: Xing Zheng <zhengxing@rock-chips.com>
Xing Zhengf35f6222016-03-28 17:51:36 +08005 */
6
7#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
8#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
9
10/* core clocks */
11#define PLL_APLLL 1
12#define PLL_APLLB 2
13#define PLL_DPLL 3
14#define PLL_CPLL 4
15#define PLL_GPLL 5
16#define PLL_NPLL 6
17#define PLL_VPLL 7
18#define ARMCLKL 8
19#define ARMCLKB 9
20
21/* sclk gates (special clocks) */
22#define SCLK_I2C1 65
23#define SCLK_I2C2 66
24#define SCLK_I2C3 67
25#define SCLK_I2C5 68
26#define SCLK_I2C6 69
27#define SCLK_I2C7 70
28#define SCLK_SPI0 71
29#define SCLK_SPI1 72
30#define SCLK_SPI2 73
31#define SCLK_SPI4 74
32#define SCLK_SPI5 75
33#define SCLK_SDMMC 76
34#define SCLK_SDIO 77
35#define SCLK_EMMC 78
36#define SCLK_TSADC 79
37#define SCLK_SARADC 80
38#define SCLK_UART0 81
39#define SCLK_UART1 82
40#define SCLK_UART2 83
41#define SCLK_UART3 84
42#define SCLK_SPDIF_8CH 85
43#define SCLK_I2S0_8CH 86
44#define SCLK_I2S1_8CH 87
45#define SCLK_I2S2_8CH 88
46#define SCLK_I2S_8CH_OUT 89
47#define SCLK_TIMER00 90
48#define SCLK_TIMER01 91
49#define SCLK_TIMER02 92
50#define SCLK_TIMER03 93
51#define SCLK_TIMER04 94
52#define SCLK_TIMER05 95
53#define SCLK_TIMER06 96
54#define SCLK_TIMER07 97
55#define SCLK_TIMER08 98
56#define SCLK_TIMER09 99
57#define SCLK_TIMER10 100
58#define SCLK_TIMER11 101
59#define SCLK_MACREF 102
60#define SCLK_MAC_RX 103
61#define SCLK_MAC_TX 104
62#define SCLK_MAC 105
63#define SCLK_MACREF_OUT 106
64#define SCLK_VOP0_PWM 107
65#define SCLK_VOP1_PWM 108
Xing Zheng003e6eb2016-04-20 19:06:49 +080066#define SCLK_RGA_CORE 109
Xing Zhengf35f6222016-03-28 17:51:36 +080067#define SCLK_ISP0 110
68#define SCLK_ISP1 111
69#define SCLK_HDMI_CEC 112
70#define SCLK_HDMI_SFR 113
71#define SCLK_DP_CORE 114
72#define SCLK_PVTM_CORE_L 115
73#define SCLK_PVTM_CORE_B 116
74#define SCLK_PVTM_GPU 117
75#define SCLK_PVTM_DDR 118
76#define SCLK_MIPIDPHY_REF 119
77#define SCLK_MIPIDPHY_CFG 120
78#define SCLK_HSICPHY 121
79#define SCLK_USBPHY480M 122
80#define SCLK_USB2PHY0_REF 123
81#define SCLK_USB2PHY1_REF 124
82#define SCLK_UPHY0_TCPDPHY_REF 125
83#define SCLK_UPHY0_TCPDCORE 126
84#define SCLK_UPHY1_TCPDPHY_REF 127
85#define SCLK_UPHY1_TCPDCORE 128
86#define SCLK_USB3OTG0_REF 129
87#define SCLK_USB3OTG1_REF 130
88#define SCLK_USB3OTG0_SUSPEND 131
89#define SCLK_USB3OTG1_SUSPEND 132
90#define SCLK_CRYPTO0 133
91#define SCLK_CRYPTO1 134
92#define SCLK_CCI_TRACE 135
93#define SCLK_CS 136
94#define SCLK_CIF_OUT 137
95#define SCLK_PCIEPHY_REF 138
96#define SCLK_PCIE_CORE 139
97#define SCLK_M0_PERILP 140
98#define SCLK_M0_PERILP_DEC 141
99#define SCLK_CM0S 142
100#define SCLK_DBG_NOC 143
101#define SCLK_DBG_PD_CORE_B 144
102#define SCLK_DBG_PD_CORE_L 145
103#define SCLK_DFIMON0_TIMER 146
104#define SCLK_DFIMON1_TIMER 147
105#define SCLK_INTMEM0 148
106#define SCLK_INTMEM1 149
107#define SCLK_INTMEM2 150
108#define SCLK_INTMEM3 151
109#define SCLK_INTMEM4 152
110#define SCLK_INTMEM5 153
111#define SCLK_SDMMC_DRV 154
112#define SCLK_SDMMC_SAMPLE 155
113#define SCLK_SDIO_DRV 156
114#define SCLK_SDIO_SAMPLE 157
115#define SCLK_VDU_CORE 158
116#define SCLK_VDU_CA 159
117#define SCLK_PCIE_PM 160
118#define SCLK_SPDIF_REC_DPTX 161
119#define SCLK_DPHY_PLL 162
120#define SCLK_DPHY_TX0_CFG 163
121#define SCLK_DPHY_TX1RX1_CFG 164
122#define SCLK_DPHY_RX0_CFG 165
Xing Zheng55df45842016-04-20 19:06:49 +0800123#define SCLK_RMII_SRC 166
124#define SCLK_PCIEPHY_REF100M 167
Lin Huang7fbdfcd2016-08-22 11:36:18 +0800125#define SCLK_DDRC 168
Eddie Caif22e4352017-04-25 14:41:09 +0800126#define SCLK_TESTCLKOUT1 169
127#define SCLK_TESTCLKOUT2 170
Xing Zhengf35f6222016-03-28 17:51:36 +0800128
129#define DCLK_VOP0 180
130#define DCLK_VOP1 181
131#define DCLK_VOP0_DIV 182
132#define DCLK_VOP1_DIV 183
133#define DCLK_M0_PERILP 184
Yakir Yange33075d2016-09-01 20:26:24 -0700134#define DCLK_VOP0_FRAC 185
135#define DCLK_VOP1_FRAC 186
Xing Zhengf35f6222016-03-28 17:51:36 +0800136
Heiko Stuebner61114132016-04-16 02:54:52 +0200137#define FCLK_CM0S 190
Xing Zhengf35f6222016-03-28 17:51:36 +0800138
139/* aclk gates */
140#define ACLK_PERIHP 192
141#define ACLK_PERIHP_NOC 193
142#define ACLK_PERILP0 194
143#define ACLK_PERILP0_NOC 195
144#define ACLK_PERF_PCIE 196
145#define ACLK_PCIE 197
146#define ACLK_INTMEM 198
147#define ACLK_TZMA 199
148#define ACLK_DCF 200
149#define ACLK_CCI 201
150#define ACLK_CCI_NOC0 202
151#define ACLK_CCI_NOC1 203
152#define ACLK_CCI_GRF 204
153#define ACLK_CENTER 205
154#define ACLK_CENTER_MAIN_NOC 206
155#define ACLK_CENTER_PERI_NOC 207
156#define ACLK_GPU 208
157#define ACLK_PERF_GPU 209
158#define ACLK_GPU_GRF 210
159#define ACLK_DMAC0_PERILP 211
160#define ACLK_DMAC1_PERILP 212
161#define ACLK_GMAC 213
162#define ACLK_GMAC_NOC 214
163#define ACLK_PERF_GMAC 215
164#define ACLK_VOP0_NOC 216
165#define ACLK_VOP0 217
166#define ACLK_VOP1_NOC 218
167#define ACLK_VOP1 219
168#define ACLK_RGA 220
169#define ACLK_RGA_NOC 221
170#define ACLK_HDCP 222
171#define ACLK_HDCP_NOC 223
172#define ACLK_HDCP22 224
173#define ACLK_IEP 225
174#define ACLK_IEP_NOC 226
175#define ACLK_VIO 227
176#define ACLK_VIO_NOC 228
177#define ACLK_ISP0 229
178#define ACLK_ISP1 230
179#define ACLK_ISP0_NOC 231
180#define ACLK_ISP1_NOC 232
181#define ACLK_ISP0_WRAPPER 233
182#define ACLK_ISP1_WRAPPER 234
183#define ACLK_VCODEC 235
184#define ACLK_VCODEC_NOC 236
185#define ACLK_VDU 237
186#define ACLK_VDU_NOC 238
187#define ACLK_PERI 239
188#define ACLK_EMMC 240
189#define ACLK_EMMC_CORE 241
190#define ACLK_EMMC_NOC 242
191#define ACLK_EMMC_GRF 243
192#define ACLK_USB3 244
193#define ACLK_USB3_NOC 245
194#define ACLK_USB3OTG0 246
195#define ACLK_USB3OTG1 247
196#define ACLK_USB3_RKSOC_AXI_PERF 248
197#define ACLK_USB3_GRF 249
198#define ACLK_GIC 250
199#define ACLK_GIC_NOC 251
200#define ACLK_GIC_ADB400_CORE_L_2_GIC 252
201#define ACLK_GIC_ADB400_CORE_B_2_GIC 253
202#define ACLK_GIC_ADB400_GIC_2_CORE_L 254
203#define ACLK_GIC_ADB400_GIC_2_CORE_B 255
204#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256
205#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257
206#define ACLK_ADB400M_PD_CORE_L 258
207#define ACLK_ADB400M_PD_CORE_B 259
Heiko Stuebner61114132016-04-16 02:54:52 +0200208#define ACLK_PERF_CORE_L 260
209#define ACLK_PERF_CORE_B 261
210#define ACLK_GIC_PRE 262
211#define ACLK_VOP0_PRE 263
212#define ACLK_VOP1_PRE 264
Xing Zhengf35f6222016-03-28 17:51:36 +0800213
214/* pclk gates */
215#define PCLK_PERIHP 320
216#define PCLK_PERIHP_NOC 321
217#define PCLK_PERILP0 322
218#define PCLK_PERILP1 323
219#define PCLK_PERILP1_NOC 324
220#define PCLK_PERILP_SGRF 325
221#define PCLK_PERIHP_GRF 326
222#define PCLK_PCIE 327
223#define PCLK_SGRF 328
224#define PCLK_INTR_ARB 329
225#define PCLK_CENTER_MAIN_NOC 330
226#define PCLK_CIC 331
227#define PCLK_COREDBG_B 332
228#define PCLK_COREDBG_L 333
229#define PCLK_DBG_CXCS_PD_CORE_B 334
230#define PCLK_DCF 335
231#define PCLK_GPIO2 336
232#define PCLK_GPIO3 337
233#define PCLK_GPIO4 338
234#define PCLK_GRF 339
235#define PCLK_HSICPHY 340
236#define PCLK_I2C1 341
237#define PCLK_I2C2 342
238#define PCLK_I2C3 343
239#define PCLK_I2C5 344
240#define PCLK_I2C6 345
241#define PCLK_I2C7 346
242#define PCLK_SPI0 347
243#define PCLK_SPI1 348
244#define PCLK_SPI2 349
245#define PCLK_SPI4 350
246#define PCLK_SPI5 351
247#define PCLK_UART0 352
248#define PCLK_UART1 353
249#define PCLK_UART2 354
250#define PCLK_UART3 355
251#define PCLK_TSADC 356
252#define PCLK_SARADC 357
253#define PCLK_GMAC 358
254#define PCLK_GMAC_NOC 359
255#define PCLK_TIMER0 360
256#define PCLK_TIMER1 361
257#define PCLK_EDP 362
258#define PCLK_EDP_NOC 363
259#define PCLK_EDP_CTRL 364
260#define PCLK_VIO 365
261#define PCLK_VIO_NOC 366
262#define PCLK_VIO_GRF 367
263#define PCLK_MIPI_DSI0 368
264#define PCLK_MIPI_DSI1 369
265#define PCLK_HDCP 370
266#define PCLK_HDCP_NOC 371
267#define PCLK_HDMI_CTRL 372
268#define PCLK_DP_CTRL 373
269#define PCLK_HDCP22 374
270#define PCLK_GASKET 375
271#define PCLK_DDR 376
272#define PCLK_DDR_MON 377
273#define PCLK_DDR_SGRF 378
274#define PCLK_ISP1_WRAPPER 379
275#define PCLK_WDT 380
276#define PCLK_EFUSE1024NS 381
277#define PCLK_EFUSE1024S 382
278#define PCLK_PMU_INTR_ARB 383
279#define PCLK_MAILBOX0 384
Heiko Stuebner61114132016-04-16 02:54:52 +0200280#define PCLK_USBPHY_MUX_G 385
281#define PCLK_UPHY0_TCPHY_G 386
282#define PCLK_UPHY0_TCPD_G 387
283#define PCLK_UPHY1_TCPHY_G 388
284#define PCLK_UPHY1_TCPD_G 389
285#define PCLK_ALIVE 390
Xing Zhengf35f6222016-03-28 17:51:36 +0800286
287/* hclk gates */
288#define HCLK_PERIHP 448
289#define HCLK_PERILP0 449
290#define HCLK_PERILP1 450
291#define HCLK_PERILP0_NOC 451
292#define HCLK_PERILP1_NOC 452
293#define HCLK_M0_PERILP 453
294#define HCLK_M0_PERILP_NOC 454
295#define HCLK_AHB1TOM 455
296#define HCLK_HOST0 456
297#define HCLK_HOST0_ARB 457
298#define HCLK_HOST1 458
299#define HCLK_HOST1_ARB 459
300#define HCLK_HSIC 460
301#define HCLK_SD 461
302#define HCLK_SDMMC 462
303#define HCLK_SDMMC_NOC 463
304#define HCLK_M_CRYPTO0 464
305#define HCLK_M_CRYPTO1 465
306#define HCLK_S_CRYPTO0 466
307#define HCLK_S_CRYPTO1 467
308#define HCLK_I2S0_8CH 468
309#define HCLK_I2S1_8CH 469
310#define HCLK_I2S2_8CH 470
311#define HCLK_SPDIF 471
312#define HCLK_VOP0_NOC 472
313#define HCLK_VOP0 473
314#define HCLK_VOP1_NOC 474
315#define HCLK_VOP1 475
316#define HCLK_ROM 476
317#define HCLK_IEP 477
318#define HCLK_IEP_NOC 478
319#define HCLK_ISP0 479
320#define HCLK_ISP1 480
321#define HCLK_ISP0_NOC 481
322#define HCLK_ISP1_NOC 482
323#define HCLK_ISP0_WRAPPER 483
324#define HCLK_ISP1_WRAPPER 484
325#define HCLK_RGA 485
326#define HCLK_RGA_NOC 486
327#define HCLK_HDCP 487
328#define HCLK_HDCP_NOC 488
329#define HCLK_HDCP22 489
330#define HCLK_VCODEC 490
331#define HCLK_VCODEC_NOC 491
332#define HCLK_VDU 492
333#define HCLK_VDU_NOC 493
334#define HCLK_SDIO 494
335#define HCLK_SDIO_NOC 495
336#define HCLK_SDIOAUDIO_NOC 496
337
338#define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1)
339
340/* pmu-clocks indices */
341
342#define PLL_PPLL 1
343
344#define SCLK_32K_SUSPEND_PMU 2
345#define SCLK_SPI3_PMU 3
346#define SCLK_TIMER12_PMU 4
347#define SCLK_TIMER13_PMU 5
348#define SCLK_UART4_PMU 6
349#define SCLK_PVTM_PMU 7
350#define SCLK_WIFI_PMU 8
351#define SCLK_I2C0_PMU 9
352#define SCLK_I2C4_PMU 10
353#define SCLK_I2C8_PMU 11
354
355#define PCLK_SRC_PMU 19
356#define PCLK_PMU 20
357#define PCLK_PMUGRF_PMU 21
358#define PCLK_INTMEM1_PMU 22
359#define PCLK_GPIO0_PMU 23
360#define PCLK_GPIO1_PMU 24
361#define PCLK_SGRF_PMU 25
362#define PCLK_NOC_PMU 26
363#define PCLK_I2C0_PMU 27
364#define PCLK_I2C4_PMU 28
365#define PCLK_I2C8_PMU 29
366#define PCLK_RKPWM_PMU 30
367#define PCLK_SPI3_PMU 31
368#define PCLK_TIMER_PMU 32
369#define PCLK_MAILBOX_PMU 33
370#define PCLK_UART4_PMU 34
371#define PCLK_WDT_M0_PMU 35
372
373#define FCLK_CM0S_SRC_PMU 44
374#define FCLK_CM0S_PMU 45
375#define SCLK_CM0S_PMU 46
376#define HCLK_CM0S_PMU 47
377#define DCLK_CM0S_PMU 48
378#define PCLK_INTR_ARB_PMU 49
379#define HCLK_NOC_PMU 50
380
381#define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1)
382
383/* soft-reset indices */
384
385/* cru_softrst_con0 */
386#define SRST_CORE_L0 0
387#define SRST_CORE_B0 1
388#define SRST_CORE_PO_L0 2
389#define SRST_CORE_PO_B0 3
390#define SRST_L2_L 4
391#define SRST_L2_B 5
392#define SRST_ADB_L 6
393#define SRST_ADB_B 7
394#define SRST_A_CCI 8
395#define SRST_A_CCIM0_NOC 9
396#define SRST_A_CCIM1_NOC 10
397#define SRST_DBG_NOC 11
398
399/* cru_softrst_con1 */
400#define SRST_CORE_L0_T 16
401#define SRST_CORE_L1 17
402#define SRST_CORE_L2 18
403#define SRST_CORE_L3 19
404#define SRST_CORE_PO_L0_T 20
405#define SRST_CORE_PO_L1 21
406#define SRST_CORE_PO_L2 22
407#define SRST_CORE_PO_L3 23
408#define SRST_A_ADB400_GIC2COREL 24
409#define SRST_A_ADB400_COREL2GIC 25
410#define SRST_P_DBG_L 26
411#define SRST_L2_L_T 28
412#define SRST_ADB_L_T 29
413#define SRST_A_RKPERF_L 30
414#define SRST_PVTM_CORE_L 31
415
416/* cru_softrst_con2 */
417#define SRST_CORE_B0_T 32
418#define SRST_CORE_B1 33
419#define SRST_CORE_PO_B0_T 36
420#define SRST_CORE_PO_B1 37
421#define SRST_A_ADB400_GIC2COREB 40
422#define SRST_A_ADB400_COREB2GIC 41
423#define SRST_P_DBG_B 42
424#define SRST_L2_B_T 43
425#define SRST_ADB_B_T 45
426#define SRST_A_RKPERF_B 46
427#define SRST_PVTM_CORE_B 47
428
429/* cru_softrst_con3 */
430#define SRST_A_CCI_T 50
431#define SRST_A_CCIM0_NOC_T 51
432#define SRST_A_CCIM1_NOC_T 52
433#define SRST_A_ADB400M_PD_CORE_B_T 53
434#define SRST_A_ADB400M_PD_CORE_L_T 54
435#define SRST_DBG_NOC_T 55
436#define SRST_DBG_CXCS 56
437#define SRST_CCI_TRACE 57
438#define SRST_P_CCI_GRF 58
439
440/* cru_softrst_con4 */
441#define SRST_A_CENTER_MAIN_NOC 64
442#define SRST_A_CENTER_PERI_NOC 65
443#define SRST_P_CENTER_MAIN 66
444#define SRST_P_DDRMON 67
445#define SRST_P_CIC 68
446#define SRST_P_CENTER_SGRF 69
447#define SRST_DDR0_MSCH 70
448#define SRST_DDRCFG0_MSCH 71
449#define SRST_DDR0 72
450#define SRST_DDRPHY0 73
451#define SRST_DDR1_MSCH 74
452#define SRST_DDRCFG1_MSCH 75
453#define SRST_DDR1 76
454#define SRST_DDRPHY1 77
455#define SRST_DDR_CIC 78
456#define SRST_PVTM_DDR 79
457
458/* cru_softrst_con5 */
459#define SRST_A_VCODEC_NOC 80
460#define SRST_A_VCODEC 81
461#define SRST_H_VCODEC_NOC 82
462#define SRST_H_VCODEC 83
463#define SRST_A_VDU_NOC 88
464#define SRST_A_VDU 89
465#define SRST_H_VDU_NOC 90
466#define SRST_H_VDU 91
467#define SRST_VDU_CORE 92
468#define SRST_VDU_CA 93
469
470/* cru_softrst_con6 */
471#define SRST_A_IEP_NOC 96
472#define SRST_A_VOP_IEP 97
473#define SRST_A_IEP 98
474#define SRST_H_IEP_NOC 99
475#define SRST_H_IEP 100
476#define SRST_A_RGA_NOC 102
477#define SRST_A_RGA 103
478#define SRST_H_RGA_NOC 104
479#define SRST_H_RGA 105
480#define SRST_RGA_CORE 106
481#define SRST_EMMC_NOC 108
482#define SRST_EMMC 109
483#define SRST_EMMC_GRF 110
484
485/* cru_softrst_con7 */
486#define SRST_A_PERIHP_NOC 112
487#define SRST_P_PERIHP_GRF 113
488#define SRST_H_PERIHP_NOC 114
489#define SRST_USBHOST0 115
490#define SRST_HOSTC0_AUX 116
491#define SRST_HOST0_ARB 117
492#define SRST_USBHOST1 118
493#define SRST_HOSTC1_AUX 119
494#define SRST_HOST1_ARB 120
495#define SRST_SDIO0 121
496#define SRST_SDMMC 122
497#define SRST_HSIC 123
498#define SRST_HSIC_AUX 124
499#define SRST_AHB1TOM 125
500#define SRST_P_PERIHP_NOC 126
501#define SRST_HSICPHY 127
502
503/* cru_softrst_con8 */
504#define SRST_A_PCIE 128
505#define SRST_P_PCIE 129
506#define SRST_PCIE_CORE 130
507#define SRST_PCIE_MGMT 131
508#define SRST_PCIE_MGMT_STICKY 132
509#define SRST_PCIE_PIPE 133
510#define SRST_PCIE_PM 134
511#define SRST_PCIEPHY 135
512#define SRST_A_GMAC_NOC 136
513#define SRST_A_GMAC 137
514#define SRST_P_GMAC_NOC 138
515#define SRST_P_GMAC_GRF 140
516#define SRST_HSICPHY_POR 142
517#define SRST_HSICPHY_UTMI 143
518
519/* cru_softrst_con9 */
520#define SRST_USB2PHY0_POR 144
521#define SRST_USB2PHY0_UTMI_PORT0 145
522#define SRST_USB2PHY0_UTMI_PORT1 146
523#define SRST_USB2PHY0_EHCIPHY 147
524#define SRST_UPHY0_PIPE_L00 148
525#define SRST_UPHY0 149
526#define SRST_UPHY0_TCPDPWRUP 150
527#define SRST_USB2PHY1_POR 152
528#define SRST_USB2PHY1_UTMI_PORT0 153
529#define SRST_USB2PHY1_UTMI_PORT1 154
530#define SRST_USB2PHY1_EHCIPHY 155
531#define SRST_UPHY1_PIPE_L00 156
532#define SRST_UPHY1 157
533#define SRST_UPHY1_TCPDPWRUP 158
534
535/* cru_softrst_con10 */
536#define SRST_A_PERILP0_NOC 160
537#define SRST_A_DCF 161
538#define SRST_GIC500 162
539#define SRST_DMAC0_PERILP0 163
540#define SRST_DMAC1_PERILP0 164
541#define SRST_TZMA 165
542#define SRST_INTMEM 166
543#define SRST_ADB400_MST0 167
544#define SRST_ADB400_MST1 168
545#define SRST_ADB400_SLV0 169
546#define SRST_ADB400_SLV1 170
547#define SRST_H_PERILP0 171
548#define SRST_H_PERILP0_NOC 172
549#define SRST_ROM 173
550#define SRST_CRYPTO_S 174
551#define SRST_CRYPTO_M 175
552
553/* cru_softrst_con11 */
554#define SRST_P_DCF 176
555#define SRST_CM0S_NOC 177
556#define SRST_CM0S 178
557#define SRST_CM0S_DBG 179
558#define SRST_CM0S_PO 180
559#define SRST_CRYPTO 181
560#define SRST_P_PERILP1_SGRF 182
561#define SRST_P_PERILP1_GRF 183
562#define SRST_CRYPTO1_S 184
563#define SRST_CRYPTO1_M 185
564#define SRST_CRYPTO1 186
565#define SRST_GIC_NOC 188
566#define SRST_SD_NOC 189
567#define SRST_SDIOAUDIO_BRG 190
568
569/* cru_softrst_con12 */
570#define SRST_H_PERILP1 192
571#define SRST_H_PERILP1_NOC 193
572#define SRST_H_I2S0_8CH 194
573#define SRST_H_I2S1_8CH 195
574#define SRST_H_I2S2_8CH 196
575#define SRST_H_SPDIF_8CH 197
576#define SRST_P_PERILP1_NOC 198
577#define SRST_P_EFUSE_1024 199
578#define SRST_P_EFUSE_1024S 200
579#define SRST_P_I2C0 201
580#define SRST_P_I2C1 202
581#define SRST_P_I2C2 203
582#define SRST_P_I2C3 204
583#define SRST_P_I2C4 205
584#define SRST_P_I2C5 206
585#define SRST_P_MAILBOX0 207
586
587/* cru_softrst_con13 */
588#define SRST_P_UART0 208
589#define SRST_P_UART1 209
590#define SRST_P_UART2 210
591#define SRST_P_UART3 211
592#define SRST_P_SARADC 212
593#define SRST_P_TSADC 213
594#define SRST_P_SPI0 214
595#define SRST_P_SPI1 215
596#define SRST_P_SPI2 216
597#define SRST_P_SPI3 217
598#define SRST_P_SPI4 218
599#define SRST_SPI0 219
600#define SRST_SPI1 220
601#define SRST_SPI2 221
602#define SRST_SPI3 222
603#define SRST_SPI4 223
604
605/* cru_softrst_con14 */
606#define SRST_I2S0_8CH 224
607#define SRST_I2S1_8CH 225
608#define SRST_I2S2_8CH 226
609#define SRST_SPDIF_8CH 227
610#define SRST_UART0 228
611#define SRST_UART1 229
612#define SRST_UART2 230
613#define SRST_UART3 231
614#define SRST_TSADC 232
615#define SRST_I2C0 233
616#define SRST_I2C1 234
617#define SRST_I2C2 235
618#define SRST_I2C3 236
619#define SRST_I2C4 237
620#define SRST_I2C5 238
621#define SRST_SDIOAUDIO_NOC 239
622
623/* cru_softrst_con15 */
624#define SRST_A_VIO_NOC 240
625#define SRST_A_HDCP_NOC 241
626#define SRST_A_HDCP 242
627#define SRST_H_HDCP_NOC 243
628#define SRST_H_HDCP 244
629#define SRST_P_HDCP_NOC 245
630#define SRST_P_HDCP 246
631#define SRST_P_HDMI_CTRL 247
632#define SRST_P_DP_CTRL 248
633#define SRST_S_DP_CTRL 249
634#define SRST_C_DP_CTRL 250
635#define SRST_P_MIPI_DSI0 251
636#define SRST_P_MIPI_DSI1 252
637#define SRST_DP_CORE 253
638#define SRST_DP_I2S 254
639
640/* cru_softrst_con16 */
641#define SRST_GASKET 256
642#define SRST_VIO_GRF 258
643#define SRST_DPTX_SPDIF_REC 259
644#define SRST_HDMI_CTRL 260
645#define SRST_HDCP_CTRL 261
646#define SRST_A_ISP0_NOC 262
647#define SRST_A_ISP1_NOC 263
648#define SRST_H_ISP0_NOC 266
649#define SRST_H_ISP1_NOC 267
650#define SRST_H_ISP0 268
651#define SRST_H_ISP1 269
652#define SRST_ISP0 270
653#define SRST_ISP1 271
654
655/* cru_softrst_con17 */
656#define SRST_A_VOP0_NOC 272
657#define SRST_A_VOP1_NOC 273
658#define SRST_A_VOP0 274
659#define SRST_A_VOP1 275
660#define SRST_H_VOP0_NOC 276
661#define SRST_H_VOP1_NOC 277
662#define SRST_H_VOP0 278
663#define SRST_H_VOP1 279
664#define SRST_D_VOP0 280
665#define SRST_D_VOP1 281
666#define SRST_VOP0_PWM 282
667#define SRST_VOP1_PWM 283
668#define SRST_P_EDP_NOC 284
669#define SRST_P_EDP_CTRL 285
670
671/* cru_softrst_con18 */
Xing Zhengf73b5042016-04-20 19:06:49 +0800672#define SRST_A_GPU 288
Xing Zhengf35f6222016-03-28 17:51:36 +0800673#define SRST_A_GPU_NOC 289
674#define SRST_A_GPU_GRF 290
675#define SRST_PVTM_GPU 291
676#define SRST_A_USB3_NOC 292
677#define SRST_A_USB3_OTG0 293
678#define SRST_A_USB3_OTG1 294
679#define SRST_A_USB3_GRF 295
680#define SRST_PMU 296
681
682/* cru_softrst_con19 */
683#define SRST_P_TIMER0_5 304
684#define SRST_TIMER0 305
685#define SRST_TIMER1 306
686#define SRST_TIMER2 307
687#define SRST_TIMER3 308
688#define SRST_TIMER4 309
689#define SRST_TIMER5 310
690#define SRST_P_TIMER6_11 311
691#define SRST_TIMER6 312
692#define SRST_TIMER7 313
693#define SRST_TIMER8 314
694#define SRST_TIMER9 315
695#define SRST_TIMER10 316
696#define SRST_TIMER11 317
697#define SRST_P_INTR_ARB_PMU 318
698#define SRST_P_ALIVE_SGRF 319
699
700/* cru_softrst_con20 */
701#define SRST_P_GPIO2 320
702#define SRST_P_GPIO3 321
703#define SRST_P_GPIO4 322
704#define SRST_P_GRF 323
705#define SRST_P_ALIVE_NOC 324
706#define SRST_P_WDT0 325
707#define SRST_P_WDT1 326
708#define SRST_P_INTR_ARB 327
709#define SRST_P_UPHY0_DPTX 328
710#define SRST_P_UPHY0_APB 330
711#define SRST_P_UPHY0_TCPHY 332
712#define SRST_P_UPHY1_TCPHY 333
713#define SRST_P_UPHY0_TCPDCTRL 334
714#define SRST_P_UPHY1_TCPDCTRL 335
715
716/* pmu soft-reset indices */
717
718/* pmu_cru_softrst_con0 */
719#define SRST_P_NOC 0
720#define SRST_P_INTMEM 1
721#define SRST_H_CM0S 2
722#define SRST_H_CM0S_NOC 3
723#define SRST_DBG_CM0S 4
724#define SRST_PO_CM0S 5
725#define SRST_P_SPI6 6
726#define SRST_SPI6 7
727#define SRST_P_TIMER_0_1 8
728#define SRST_P_TIMER_0 9
729#define SRST_P_TIMER_1 10
730#define SRST_P_UART4 11
731#define SRST_UART4 12
732#define SRST_P_WDT 13
733
734/* pmu_cru_softrst_con1 */
735#define SRST_P_I2C6 16
736#define SRST_P_I2C7 17
737#define SRST_P_I2C8 18
738#define SRST_P_MAILBOX 19
739#define SRST_P_RKPWM 20
740#define SRST_P_PMUGRF 21
741#define SRST_P_SGRF 22
742#define SRST_P_GPIO0 23
743#define SRST_P_GPIO1 24
744#define SRST_P_CRU 25
745#define SRST_P_INTR 26
746#define SRST_PVTM 27
747#define SRST_I2C6 28
748#define SRST_I2C7 29
749#define SRST_I2C8 30
750
751#endif