Thomas Gleixner | d2912cb | 2019-06-04 10:11:33 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Eric Anholt | c8b75bc | 2015-03-02 13:01:12 -0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015 Broadcom |
Eric Anholt | c8b75bc | 2015-03-02 13:01:12 -0800 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | /** |
| 7 | * DOC: VC4 KMS |
| 8 | * |
| 9 | * This is the general code for implementing KMS mode setting that |
| 10 | * doesn't clearly associate with any of the other objects (plane, |
| 11 | * crtc, HDMI encoder). |
| 12 | */ |
| 13 | |
Maxime Ripard | d7d96c0 | 2020-09-03 10:00:35 +0200 | [diff] [blame] | 14 | #include <linux/clk.h> |
| 15 | |
Masahiro Yamada | b7e8e25 | 2017-05-18 13:29:38 +0900 | [diff] [blame] | 16 | #include <drm/drm_atomic.h> |
| 17 | #include <drm/drm_atomic_helper.h> |
Sam Ravnborg | fd6d6d8 | 2019-07-16 08:42:07 +0200 | [diff] [blame] | 18 | #include <drm/drm_crtc.h> |
Noralf Trønnes | 9762477 | 2017-08-13 15:32:03 +0200 | [diff] [blame] | 19 | #include <drm/drm_gem_framebuffer_helper.h> |
Daniel Vetter | fcd70cd | 2019-01-17 22:03:34 +0100 | [diff] [blame] | 20 | #include <drm/drm_plane_helper.h> |
| 21 | #include <drm/drm_probe_helper.h> |
Sam Ravnborg | fd6d6d8 | 2019-07-16 08:42:07 +0200 | [diff] [blame] | 22 | #include <drm/drm_vblank.h> |
| 23 | |
Eric Anholt | c8b75bc | 2015-03-02 13:01:12 -0800 | [diff] [blame] | 24 | #include "vc4_drv.h" |
Stefan Schake | 766cc6b | 2018-04-20 05:25:44 -0700 | [diff] [blame] | 25 | #include "vc4_regs.h" |
| 26 | |
Maxime Ripard | a9661f2 | 2020-11-05 14:56:52 +0100 | [diff] [blame] | 27 | #define HVS_NUM_CHANNELS 3 |
| 28 | |
Stefan Schake | 766cc6b | 2018-04-20 05:25:44 -0700 | [diff] [blame] | 29 | struct vc4_ctm_state { |
| 30 | struct drm_private_state base; |
| 31 | struct drm_color_ctm *ctm; |
| 32 | int fifo; |
| 33 | }; |
| 34 | |
| 35 | static struct vc4_ctm_state *to_vc4_ctm_state(struct drm_private_state *priv) |
| 36 | { |
| 37 | return container_of(priv, struct vc4_ctm_state, base); |
| 38 | } |
| 39 | |
Maxime Ripard | f2df84e | 2020-11-20 15:42:44 +0100 | [diff] [blame] | 40 | struct vc4_hvs_state { |
| 41 | struct drm_private_state base; |
Maxime Ripard | 9ec03d7 | 2020-12-04 16:11:35 +0100 | [diff] [blame] | 42 | |
| 43 | struct { |
| 44 | unsigned in_use: 1; |
| 45 | struct drm_crtc_commit *pending_commit; |
| 46 | } fifo_state[HVS_NUM_CHANNELS]; |
Maxime Ripard | f2df84e | 2020-11-20 15:42:44 +0100 | [diff] [blame] | 47 | }; |
| 48 | |
| 49 | static struct vc4_hvs_state * |
| 50 | to_vc4_hvs_state(struct drm_private_state *priv) |
| 51 | { |
| 52 | return container_of(priv, struct vc4_hvs_state, base); |
| 53 | } |
| 54 | |
Boris Brezillon | 4686da8 | 2019-02-20 16:51:23 +0100 | [diff] [blame] | 55 | struct vc4_load_tracker_state { |
| 56 | struct drm_private_state base; |
| 57 | u64 hvs_load; |
| 58 | u64 membus_load; |
| 59 | }; |
| 60 | |
| 61 | static struct vc4_load_tracker_state * |
| 62 | to_vc4_load_tracker_state(struct drm_private_state *priv) |
| 63 | { |
| 64 | return container_of(priv, struct vc4_load_tracker_state, base); |
| 65 | } |
| 66 | |
Stefan Schake | 766cc6b | 2018-04-20 05:25:44 -0700 | [diff] [blame] | 67 | static struct vc4_ctm_state *vc4_get_ctm_state(struct drm_atomic_state *state, |
| 68 | struct drm_private_obj *manager) |
| 69 | { |
| 70 | struct drm_device *dev = state->dev; |
Maxime Ripard | 88e0858 | 2020-10-29 20:01:02 +0100 | [diff] [blame] | 71 | struct vc4_dev *vc4 = to_vc4_dev(dev); |
Stefan Schake | 766cc6b | 2018-04-20 05:25:44 -0700 | [diff] [blame] | 72 | struct drm_private_state *priv_state; |
| 73 | int ret; |
| 74 | |
| 75 | ret = drm_modeset_lock(&vc4->ctm_state_lock, state->acquire_ctx); |
| 76 | if (ret) |
| 77 | return ERR_PTR(ret); |
| 78 | |
| 79 | priv_state = drm_atomic_get_private_obj_state(state, manager); |
| 80 | if (IS_ERR(priv_state)) |
| 81 | return ERR_CAST(priv_state); |
| 82 | |
| 83 | return to_vc4_ctm_state(priv_state); |
| 84 | } |
| 85 | |
| 86 | static struct drm_private_state * |
| 87 | vc4_ctm_duplicate_state(struct drm_private_obj *obj) |
| 88 | { |
| 89 | struct vc4_ctm_state *state; |
| 90 | |
| 91 | state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); |
| 92 | if (!state) |
| 93 | return NULL; |
| 94 | |
| 95 | __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); |
| 96 | |
| 97 | return &state->base; |
| 98 | } |
| 99 | |
| 100 | static void vc4_ctm_destroy_state(struct drm_private_obj *obj, |
| 101 | struct drm_private_state *state) |
| 102 | { |
| 103 | struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(state); |
| 104 | |
| 105 | kfree(ctm_state); |
| 106 | } |
| 107 | |
| 108 | static const struct drm_private_state_funcs vc4_ctm_state_funcs = { |
| 109 | .atomic_duplicate_state = vc4_ctm_duplicate_state, |
| 110 | .atomic_destroy_state = vc4_ctm_destroy_state, |
| 111 | }; |
| 112 | |
Maxime Ripard | dcda7c2 | 2020-10-29 20:01:04 +0100 | [diff] [blame] | 113 | static void vc4_ctm_obj_fini(struct drm_device *dev, void *unused) |
| 114 | { |
| 115 | struct vc4_dev *vc4 = to_vc4_dev(dev); |
| 116 | |
| 117 | drm_atomic_private_obj_fini(&vc4->ctm_manager); |
| 118 | } |
| 119 | |
| 120 | static int vc4_ctm_obj_init(struct vc4_dev *vc4) |
| 121 | { |
| 122 | struct vc4_ctm_state *ctm_state; |
| 123 | |
| 124 | drm_modeset_lock_init(&vc4->ctm_state_lock); |
| 125 | |
| 126 | ctm_state = kzalloc(sizeof(*ctm_state), GFP_KERNEL); |
| 127 | if (!ctm_state) |
| 128 | return -ENOMEM; |
| 129 | |
| 130 | drm_atomic_private_obj_init(&vc4->base, &vc4->ctm_manager, &ctm_state->base, |
| 131 | &vc4_ctm_state_funcs); |
| 132 | |
Maxime Ripard | 3c354ed | 2020-11-05 14:56:50 +0100 | [diff] [blame] | 133 | return drmm_add_action_or_reset(&vc4->base, vc4_ctm_obj_fini, NULL); |
Maxime Ripard | dcda7c2 | 2020-10-29 20:01:04 +0100 | [diff] [blame] | 134 | } |
| 135 | |
Stefan Schake | 766cc6b | 2018-04-20 05:25:44 -0700 | [diff] [blame] | 136 | /* Converts a DRM S31.32 value to the HW S0.9 format. */ |
| 137 | static u16 vc4_ctm_s31_32_to_s0_9(u64 in) |
| 138 | { |
| 139 | u16 r; |
| 140 | |
| 141 | /* Sign bit. */ |
| 142 | r = in & BIT_ULL(63) ? BIT(9) : 0; |
| 143 | |
| 144 | if ((in & GENMASK_ULL(62, 32)) > 0) { |
| 145 | /* We have zero integer bits so we can only saturate here. */ |
| 146 | r |= GENMASK(8, 0); |
| 147 | } else { |
| 148 | /* Otherwise take the 9 most important fractional bits. */ |
| 149 | r |= (in >> 23) & GENMASK(8, 0); |
| 150 | } |
| 151 | |
| 152 | return r; |
| 153 | } |
| 154 | |
| 155 | static void |
| 156 | vc4_ctm_commit(struct vc4_dev *vc4, struct drm_atomic_state *state) |
| 157 | { |
| 158 | struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(vc4->ctm_manager.state); |
| 159 | struct drm_color_ctm *ctm = ctm_state->ctm; |
| 160 | |
| 161 | if (ctm_state->fifo) { |
| 162 | HVS_WRITE(SCALER_OLEDCOEF2, |
| 163 | VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]), |
| 164 | SCALER_OLEDCOEF2_R_TO_R) | |
| 165 | VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]), |
| 166 | SCALER_OLEDCOEF2_R_TO_G) | |
| 167 | VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]), |
| 168 | SCALER_OLEDCOEF2_R_TO_B)); |
| 169 | HVS_WRITE(SCALER_OLEDCOEF1, |
| 170 | VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]), |
| 171 | SCALER_OLEDCOEF1_G_TO_R) | |
| 172 | VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]), |
| 173 | SCALER_OLEDCOEF1_G_TO_G) | |
| 174 | VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]), |
| 175 | SCALER_OLEDCOEF1_G_TO_B)); |
| 176 | HVS_WRITE(SCALER_OLEDCOEF0, |
| 177 | VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]), |
| 178 | SCALER_OLEDCOEF0_B_TO_R) | |
| 179 | VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]), |
| 180 | SCALER_OLEDCOEF0_B_TO_G) | |
| 181 | VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]), |
| 182 | SCALER_OLEDCOEF0_B_TO_B)); |
| 183 | } |
| 184 | |
| 185 | HVS_WRITE(SCALER_OLEDOFFS, |
| 186 | VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO)); |
| 187 | } |
Eric Anholt | c8b75bc | 2015-03-02 13:01:12 -0800 | [diff] [blame] | 188 | |
Maxime Ripard | f2df84e | 2020-11-20 15:42:44 +0100 | [diff] [blame] | 189 | static struct vc4_hvs_state * |
Maxime Ripard | 9ec03d7 | 2020-12-04 16:11:35 +0100 | [diff] [blame] | 190 | vc4_hvs_get_new_global_state(struct drm_atomic_state *state) |
| 191 | { |
| 192 | struct vc4_dev *vc4 = to_vc4_dev(state->dev); |
| 193 | struct drm_private_state *priv_state; |
| 194 | |
| 195 | priv_state = drm_atomic_get_new_private_obj_state(state, &vc4->hvs_channels); |
| 196 | if (IS_ERR(priv_state)) |
| 197 | return ERR_CAST(priv_state); |
| 198 | |
| 199 | return to_vc4_hvs_state(priv_state); |
| 200 | } |
| 201 | |
| 202 | static struct vc4_hvs_state * |
| 203 | vc4_hvs_get_old_global_state(struct drm_atomic_state *state) |
| 204 | { |
| 205 | struct vc4_dev *vc4 = to_vc4_dev(state->dev); |
| 206 | struct drm_private_state *priv_state; |
| 207 | |
| 208 | priv_state = drm_atomic_get_old_private_obj_state(state, &vc4->hvs_channels); |
| 209 | if (IS_ERR(priv_state)) |
| 210 | return ERR_CAST(priv_state); |
| 211 | |
| 212 | return to_vc4_hvs_state(priv_state); |
| 213 | } |
| 214 | |
| 215 | static struct vc4_hvs_state * |
Maxime Ripard | f2df84e | 2020-11-20 15:42:44 +0100 | [diff] [blame] | 216 | vc4_hvs_get_global_state(struct drm_atomic_state *state) |
| 217 | { |
| 218 | struct vc4_dev *vc4 = to_vc4_dev(state->dev); |
| 219 | struct drm_private_state *priv_state; |
| 220 | |
| 221 | priv_state = drm_atomic_get_private_obj_state(state, &vc4->hvs_channels); |
| 222 | if (IS_ERR(priv_state)) |
| 223 | return ERR_CAST(priv_state); |
| 224 | |
| 225 | return to_vc4_hvs_state(priv_state); |
| 226 | } |
| 227 | |
Maxime Ripard | 87ebcd4 | 2020-09-03 10:00:46 +0200 | [diff] [blame] | 228 | static void vc4_hvs_pv_muxing_commit(struct vc4_dev *vc4, |
| 229 | struct drm_atomic_state *state) |
| 230 | { |
| 231 | struct drm_crtc_state *crtc_state; |
| 232 | struct drm_crtc *crtc; |
| 233 | unsigned int i; |
| 234 | |
| 235 | for_each_new_crtc_in_state(state, crtc, crtc_state, i) { |
| 236 | struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state); |
| 237 | u32 dispctrl; |
| 238 | u32 dsp3_mux; |
| 239 | |
| 240 | if (!crtc_state->active) |
| 241 | continue; |
| 242 | |
| 243 | if (vc4_state->assigned_channel != 2) |
| 244 | continue; |
| 245 | |
| 246 | /* |
| 247 | * SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to |
| 248 | * FIFO X'. |
| 249 | * SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'. |
| 250 | * |
| 251 | * DSP3 is connected to FIFO2 unless the transposer is |
| 252 | * enabled. In this case, FIFO 2 is directly accessed by the |
| 253 | * TXP IP, and we need to disable the FIFO2 -> pixelvalve1 |
| 254 | * route. |
| 255 | */ |
| 256 | if (vc4_state->feed_txp) |
| 257 | dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX); |
| 258 | else |
| 259 | dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX); |
| 260 | |
| 261 | dispctrl = HVS_READ(SCALER_DISPCTRL) & |
| 262 | ~SCALER_DISPCTRL_DSP3_MUX_MASK; |
| 263 | HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux); |
| 264 | } |
| 265 | } |
| 266 | |
| 267 | static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4, |
| 268 | struct drm_atomic_state *state) |
| 269 | { |
| 270 | struct drm_crtc_state *crtc_state; |
| 271 | struct drm_crtc *crtc; |
Maxime Ripard | 2820526 | 2020-11-20 15:42:45 +0100 | [diff] [blame] | 272 | unsigned char mux; |
Maxime Ripard | 87ebcd4 | 2020-09-03 10:00:46 +0200 | [diff] [blame] | 273 | unsigned int i; |
| 274 | u32 reg; |
| 275 | |
| 276 | for_each_new_crtc_in_state(state, crtc, crtc_state, i) { |
| 277 | struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state); |
| 278 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); |
| 279 | |
Maxime Ripard | 2820526 | 2020-11-20 15:42:45 +0100 | [diff] [blame] | 280 | if (!vc4_state->update_muxing) |
Maxime Ripard | 87ebcd4 | 2020-09-03 10:00:46 +0200 | [diff] [blame] | 281 | continue; |
| 282 | |
| 283 | switch (vc4_crtc->data->hvs_output) { |
| 284 | case 2: |
Maxime Ripard | 2820526 | 2020-11-20 15:42:45 +0100 | [diff] [blame] | 285 | mux = (vc4_state->assigned_channel == 2) ? 0 : 1; |
| 286 | reg = HVS_READ(SCALER_DISPECTRL); |
| 287 | HVS_WRITE(SCALER_DISPECTRL, |
| 288 | (reg & ~SCALER_DISPECTRL_DSP2_MUX_MASK) | |
| 289 | VC4_SET_FIELD(mux, SCALER_DISPECTRL_DSP2_MUX)); |
Maxime Ripard | 87ebcd4 | 2020-09-03 10:00:46 +0200 | [diff] [blame] | 290 | break; |
| 291 | |
| 292 | case 3: |
Maxime Ripard | 2820526 | 2020-11-20 15:42:45 +0100 | [diff] [blame] | 293 | if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED) |
| 294 | mux = 3; |
| 295 | else |
| 296 | mux = vc4_state->assigned_channel; |
| 297 | |
| 298 | reg = HVS_READ(SCALER_DISPCTRL); |
| 299 | HVS_WRITE(SCALER_DISPCTRL, |
| 300 | (reg & ~SCALER_DISPCTRL_DSP3_MUX_MASK) | |
| 301 | VC4_SET_FIELD(mux, SCALER_DISPCTRL_DSP3_MUX)); |
Maxime Ripard | 87ebcd4 | 2020-09-03 10:00:46 +0200 | [diff] [blame] | 302 | break; |
| 303 | |
| 304 | case 4: |
Maxime Ripard | 2820526 | 2020-11-20 15:42:45 +0100 | [diff] [blame] | 305 | if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED) |
| 306 | mux = 3; |
| 307 | else |
| 308 | mux = vc4_state->assigned_channel; |
| 309 | |
| 310 | reg = HVS_READ(SCALER_DISPEOLN); |
| 311 | HVS_WRITE(SCALER_DISPEOLN, |
| 312 | (reg & ~SCALER_DISPEOLN_DSP4_MUX_MASK) | |
| 313 | VC4_SET_FIELD(mux, SCALER_DISPEOLN_DSP4_MUX)); |
| 314 | |
Maxime Ripard | 87ebcd4 | 2020-09-03 10:00:46 +0200 | [diff] [blame] | 315 | break; |
| 316 | |
| 317 | case 5: |
Maxime Ripard | 2820526 | 2020-11-20 15:42:45 +0100 | [diff] [blame] | 318 | if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED) |
| 319 | mux = 3; |
| 320 | else |
| 321 | mux = vc4_state->assigned_channel; |
| 322 | |
| 323 | reg = HVS_READ(SCALER_DISPDITHER); |
| 324 | HVS_WRITE(SCALER_DISPDITHER, |
| 325 | (reg & ~SCALER_DISPDITHER_DSP5_MUX_MASK) | |
| 326 | VC4_SET_FIELD(mux, SCALER_DISPDITHER_DSP5_MUX)); |
Maxime Ripard | 87ebcd4 | 2020-09-03 10:00:46 +0200 | [diff] [blame] | 327 | break; |
| 328 | |
| 329 | default: |
| 330 | break; |
| 331 | } |
| 332 | } |
Maxime Ripard | 87ebcd4 | 2020-09-03 10:00:46 +0200 | [diff] [blame] | 333 | } |
| 334 | |
Maxime Ripard | f3c420f | 2020-12-04 16:11:38 +0100 | [diff] [blame] | 335 | static void vc4_atomic_commit_tail(struct drm_atomic_state *state) |
Eric Anholt | b501bac | 2015-11-30 12:34:01 -0800 | [diff] [blame] | 336 | { |
Eric Anholt | b501bac | 2015-11-30 12:34:01 -0800 | [diff] [blame] | 337 | struct drm_device *dev = state->dev; |
| 338 | struct vc4_dev *vc4 = to_vc4_dev(dev); |
Maxime Ripard | d7d96c0 | 2020-09-03 10:00:35 +0200 | [diff] [blame] | 339 | struct vc4_hvs *hvs = vc4->hvs; |
Maxime Ripard | 59635667 | 2020-09-03 10:00:45 +0200 | [diff] [blame] | 340 | struct drm_crtc_state *new_crtc_state; |
| 341 | struct drm_crtc *crtc; |
Maxime Ripard | 9ec03d7 | 2020-12-04 16:11:35 +0100 | [diff] [blame] | 342 | struct vc4_hvs_state *old_hvs_state; |
Maxime Ripard | 6052a31 | 2021-11-17 10:45:27 +0100 | [diff] [blame] | 343 | unsigned int channel; |
Boris Brezillon | 531a1b6 | 2019-02-20 16:51:22 +0100 | [diff] [blame] | 344 | int i; |
| 345 | |
Maxime Ripard | 59635667 | 2020-09-03 10:00:45 +0200 | [diff] [blame] | 346 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
Maxime Ripard | 87ebcd4 | 2020-09-03 10:00:46 +0200 | [diff] [blame] | 347 | struct vc4_crtc_state *vc4_crtc_state; |
Maxime Ripard | 59635667 | 2020-09-03 10:00:45 +0200 | [diff] [blame] | 348 | |
| 349 | if (!new_crtc_state->commit) |
Boris Brezillon | 531a1b6 | 2019-02-20 16:51:22 +0100 | [diff] [blame] | 350 | continue; |
| 351 | |
Maxime Ripard | 87ebcd4 | 2020-09-03 10:00:46 +0200 | [diff] [blame] | 352 | vc4_crtc_state = to_vc4_crtc_state(new_crtc_state); |
| 353 | vc4_hvs_mask_underrun(dev, vc4_crtc_state->assigned_channel); |
Boris Brezillon | 531a1b6 | 2019-02-20 16:51:22 +0100 | [diff] [blame] | 354 | } |
Eric Anholt | b501bac | 2015-11-30 12:34:01 -0800 | [diff] [blame] | 355 | |
Maxime Ripard | 9ec03d7 | 2020-12-04 16:11:35 +0100 | [diff] [blame] | 356 | old_hvs_state = vc4_hvs_get_old_global_state(state); |
Maxime Ripard | f927767 | 2021-11-17 10:45:23 +0100 | [diff] [blame] | 357 | if (IS_ERR(old_hvs_state)) |
Maxime Ripard | 9ec03d7 | 2020-12-04 16:11:35 +0100 | [diff] [blame] | 358 | return; |
| 359 | |
Maxime Ripard | 6052a31 | 2021-11-17 10:45:27 +0100 | [diff] [blame] | 360 | for (channel = 0; channel < HVS_NUM_CHANNELS; channel++) { |
Maxime Ripard | 049cfff | 2021-11-17 10:45:24 +0100 | [diff] [blame] | 361 | struct drm_crtc_commit *commit; |
Maxime Ripard | b99c2c9 | 2021-01-11 09:44:01 +0100 | [diff] [blame] | 362 | int ret; |
Maxime Ripard | 9ec03d7 | 2020-12-04 16:11:35 +0100 | [diff] [blame] | 363 | |
Maxime Ripard | 9ec03d7 | 2020-12-04 16:11:35 +0100 | [diff] [blame] | 364 | if (!old_hvs_state->fifo_state[channel].in_use) |
| 365 | continue; |
| 366 | |
Maxime Ripard | 049cfff | 2021-11-17 10:45:24 +0100 | [diff] [blame] | 367 | commit = old_hvs_state->fifo_state[channel].pending_commit; |
| 368 | if (!commit) |
| 369 | continue; |
| 370 | |
| 371 | ret = drm_crtc_commit_wait(commit); |
Maxime Ripard | b99c2c9 | 2021-01-11 09:44:01 +0100 | [diff] [blame] | 372 | if (ret) |
| 373 | drm_err(dev, "Timed out waiting for commit\n"); |
Maxime Ripard | 049cfff | 2021-11-17 10:45:24 +0100 | [diff] [blame] | 374 | |
| 375 | drm_crtc_commit_put(commit); |
Maxime Ripard | d134c5f | 2021-11-17 10:45:25 +0100 | [diff] [blame] | 376 | old_hvs_state->fifo_state[channel].pending_commit = NULL; |
Maxime Ripard | 9ec03d7 | 2020-12-04 16:11:35 +0100 | [diff] [blame] | 377 | } |
| 378 | |
Maxime Ripard | 0c980a0 | 2021-11-17 10:45:22 +0100 | [diff] [blame] | 379 | if (vc4->hvs->hvs5) |
| 380 | clk_set_min_rate(hvs->core_clk, 500000000); |
| 381 | |
Eric Anholt | b501bac | 2015-11-30 12:34:01 -0800 | [diff] [blame] | 382 | drm_atomic_helper_commit_modeset_disables(dev, state); |
| 383 | |
Stefan Schake | 766cc6b | 2018-04-20 05:25:44 -0700 | [diff] [blame] | 384 | vc4_ctm_commit(vc4, state); |
| 385 | |
Maxime Ripard | 87ebcd4 | 2020-09-03 10:00:46 +0200 | [diff] [blame] | 386 | if (vc4->hvs->hvs5) |
| 387 | vc5_hvs_pv_muxing_commit(vc4, state); |
| 388 | else |
| 389 | vc4_hvs_pv_muxing_commit(vc4, state); |
| 390 | |
Liu Ying | 2b58e98 | 2016-08-29 17:12:03 +0800 | [diff] [blame] | 391 | drm_atomic_helper_commit_planes(dev, state, 0); |
Eric Anholt | b501bac | 2015-11-30 12:34:01 -0800 | [diff] [blame] | 392 | |
| 393 | drm_atomic_helper_commit_modeset_enables(dev, state); |
| 394 | |
Boris Brezillon | 1ebe99a | 2018-07-03 09:50:21 +0200 | [diff] [blame] | 395 | drm_atomic_helper_fake_vblank(state); |
| 396 | |
Boris Brezillon | 34c8ea4 | 2017-06-02 10:32:08 +0200 | [diff] [blame] | 397 | drm_atomic_helper_commit_hw_done(state); |
| 398 | |
Boris Brezillon | 184d3cf | 2018-07-03 09:50:18 +0200 | [diff] [blame] | 399 | drm_atomic_helper_wait_for_flip_done(dev, state); |
Eric Anholt | b501bac | 2015-11-30 12:34:01 -0800 | [diff] [blame] | 400 | |
| 401 | drm_atomic_helper_cleanup_planes(dev, state); |
| 402 | |
Maxime Ripard | d7d96c0 | 2020-09-03 10:00:35 +0200 | [diff] [blame] | 403 | if (vc4->hvs->hvs5) |
| 404 | clk_set_min_rate(hvs->core_clk, 0); |
Eric Anholt | b501bac | 2015-11-30 12:34:01 -0800 | [diff] [blame] | 405 | } |
| 406 | |
Maxime Ripard | 9ec03d7 | 2020-12-04 16:11:35 +0100 | [diff] [blame] | 407 | static int vc4_atomic_commit_setup(struct drm_atomic_state *state) |
| 408 | { |
| 409 | struct drm_crtc_state *crtc_state; |
| 410 | struct vc4_hvs_state *hvs_state; |
| 411 | struct drm_crtc *crtc; |
| 412 | unsigned int i; |
| 413 | |
| 414 | hvs_state = vc4_hvs_get_new_global_state(state); |
Maxime Ripard | f927767 | 2021-11-17 10:45:23 +0100 | [diff] [blame] | 415 | if (WARN_ON(IS_ERR(hvs_state))) |
| 416 | return PTR_ERR(hvs_state); |
Maxime Ripard | 9ec03d7 | 2020-12-04 16:11:35 +0100 | [diff] [blame] | 417 | |
| 418 | for_each_new_crtc_in_state(state, crtc, crtc_state, i) { |
| 419 | struct vc4_crtc_state *vc4_crtc_state = |
| 420 | to_vc4_crtc_state(crtc_state); |
| 421 | unsigned int channel = |
| 422 | vc4_crtc_state->assigned_channel; |
| 423 | |
| 424 | if (channel == VC4_HVS_CHANNEL_DISABLED) |
| 425 | continue; |
| 426 | |
| 427 | if (!hvs_state->fifo_state[channel].in_use) |
| 428 | continue; |
| 429 | |
| 430 | hvs_state->fifo_state[channel].pending_commit = |
| 431 | drm_crtc_commit_get(crtc_state->commit); |
| 432 | } |
| 433 | |
| 434 | return 0; |
| 435 | } |
| 436 | |
Eric Anholt | 8375311 | 2017-06-07 17:13:36 -0700 | [diff] [blame] | 437 | static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev, |
| 438 | struct drm_file *file_priv, |
| 439 | const struct drm_mode_fb_cmd2 *mode_cmd) |
| 440 | { |
| 441 | struct drm_mode_fb_cmd2 mode_cmd_local; |
| 442 | |
| 443 | /* If the user didn't specify a modifier, use the |
| 444 | * vc4_set_tiling_ioctl() state for the BO. |
| 445 | */ |
| 446 | if (!(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) { |
| 447 | struct drm_gem_object *gem_obj; |
| 448 | struct vc4_bo *bo; |
| 449 | |
| 450 | gem_obj = drm_gem_object_lookup(file_priv, |
| 451 | mode_cmd->handles[0]); |
| 452 | if (!gem_obj) { |
Eric Anholt | fb95992 | 2017-07-25 09:27:32 -0700 | [diff] [blame] | 453 | DRM_DEBUG("Failed to look up GEM BO %d\n", |
Eric Anholt | 8375311 | 2017-06-07 17:13:36 -0700 | [diff] [blame] | 454 | mode_cmd->handles[0]); |
| 455 | return ERR_PTR(-ENOENT); |
| 456 | } |
| 457 | bo = to_vc4_bo(gem_obj); |
| 458 | |
| 459 | mode_cmd_local = *mode_cmd; |
| 460 | |
| 461 | if (bo->t_format) { |
| 462 | mode_cmd_local.modifier[0] = |
| 463 | DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED; |
| 464 | } else { |
| 465 | mode_cmd_local.modifier[0] = DRM_FORMAT_MOD_NONE; |
| 466 | } |
| 467 | |
Emil Velikov | f7a8cd3 | 2020-05-15 10:51:13 +0100 | [diff] [blame] | 468 | drm_gem_object_put(gem_obj); |
Eric Anholt | 8375311 | 2017-06-07 17:13:36 -0700 | [diff] [blame] | 469 | |
| 470 | mode_cmd = &mode_cmd_local; |
| 471 | } |
| 472 | |
Noralf Trønnes | 9762477 | 2017-08-13 15:32:03 +0200 | [diff] [blame] | 473 | return drm_gem_fb_create(dev, file_priv, mode_cmd); |
Eric Anholt | 8375311 | 2017-06-07 17:13:36 -0700 | [diff] [blame] | 474 | } |
| 475 | |
Stefan Schake | 766cc6b | 2018-04-20 05:25:44 -0700 | [diff] [blame] | 476 | /* Our CTM has some peculiar limitations: we can only enable it for one CRTC |
| 477 | * at a time and the HW only supports S0.9 scalars. To account for the latter, |
| 478 | * we don't allow userland to set a CTM that we have no hope of approximating. |
| 479 | */ |
| 480 | static int |
| 481 | vc4_ctm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) |
| 482 | { |
| 483 | struct vc4_dev *vc4 = to_vc4_dev(dev); |
| 484 | struct vc4_ctm_state *ctm_state = NULL; |
| 485 | struct drm_crtc *crtc; |
| 486 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
| 487 | struct drm_color_ctm *ctm; |
| 488 | int i; |
| 489 | |
| 490 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
| 491 | /* CTM is being disabled. */ |
| 492 | if (!new_crtc_state->ctm && old_crtc_state->ctm) { |
| 493 | ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager); |
| 494 | if (IS_ERR(ctm_state)) |
| 495 | return PTR_ERR(ctm_state); |
| 496 | ctm_state->fifo = 0; |
| 497 | } |
| 498 | } |
| 499 | |
| 500 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
| 501 | if (new_crtc_state->ctm == old_crtc_state->ctm) |
| 502 | continue; |
| 503 | |
| 504 | if (!ctm_state) { |
| 505 | ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager); |
| 506 | if (IS_ERR(ctm_state)) |
| 507 | return PTR_ERR(ctm_state); |
| 508 | } |
| 509 | |
| 510 | /* CTM is being enabled or the matrix changed. */ |
| 511 | if (new_crtc_state->ctm) { |
Maxime Ripard | 87ebcd4 | 2020-09-03 10:00:46 +0200 | [diff] [blame] | 512 | struct vc4_crtc_state *vc4_crtc_state = |
| 513 | to_vc4_crtc_state(new_crtc_state); |
| 514 | |
Stefan Schake | 766cc6b | 2018-04-20 05:25:44 -0700 | [diff] [blame] | 515 | /* fifo is 1-based since 0 disables CTM. */ |
Maxime Ripard | 87ebcd4 | 2020-09-03 10:00:46 +0200 | [diff] [blame] | 516 | int fifo = vc4_crtc_state->assigned_channel + 1; |
Stefan Schake | 766cc6b | 2018-04-20 05:25:44 -0700 | [diff] [blame] | 517 | |
| 518 | /* Check userland isn't trying to turn on CTM for more |
| 519 | * than one CRTC at a time. |
| 520 | */ |
| 521 | if (ctm_state->fifo && ctm_state->fifo != fifo) { |
| 522 | DRM_DEBUG_DRIVER("Too many CTM configured\n"); |
| 523 | return -EINVAL; |
| 524 | } |
| 525 | |
| 526 | /* Check we can approximate the specified CTM. |
| 527 | * We disallow scalars |c| > 1.0 since the HW has |
| 528 | * no integer bits. |
| 529 | */ |
| 530 | ctm = new_crtc_state->ctm->data; |
| 531 | for (i = 0; i < ARRAY_SIZE(ctm->matrix); i++) { |
| 532 | u64 val = ctm->matrix[i]; |
| 533 | |
| 534 | val &= ~BIT_ULL(63); |
| 535 | if (val > BIT_ULL(32)) |
| 536 | return -EINVAL; |
| 537 | } |
| 538 | |
| 539 | ctm_state->fifo = fifo; |
| 540 | ctm_state->ctm = ctm; |
| 541 | } |
| 542 | } |
| 543 | |
| 544 | return 0; |
| 545 | } |
| 546 | |
Boris Brezillon | 4686da8 | 2019-02-20 16:51:23 +0100 | [diff] [blame] | 547 | static int vc4_load_tracker_atomic_check(struct drm_atomic_state *state) |
| 548 | { |
| 549 | struct drm_plane_state *old_plane_state, *new_plane_state; |
| 550 | struct vc4_dev *vc4 = to_vc4_dev(state->dev); |
| 551 | struct vc4_load_tracker_state *load_state; |
| 552 | struct drm_private_state *priv_state; |
| 553 | struct drm_plane *plane; |
| 554 | int i; |
| 555 | |
Maxime Ripard | f437bc1 | 2020-09-03 10:01:51 +0200 | [diff] [blame] | 556 | if (!vc4->load_tracker_available) |
| 557 | return 0; |
| 558 | |
Boris Brezillon | 4686da8 | 2019-02-20 16:51:23 +0100 | [diff] [blame] | 559 | priv_state = drm_atomic_get_private_obj_state(state, |
| 560 | &vc4->load_tracker); |
| 561 | if (IS_ERR(priv_state)) |
| 562 | return PTR_ERR(priv_state); |
| 563 | |
| 564 | load_state = to_vc4_load_tracker_state(priv_state); |
| 565 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, |
| 566 | new_plane_state, i) { |
| 567 | struct vc4_plane_state *vc4_plane_state; |
| 568 | |
| 569 | if (old_plane_state->fb && old_plane_state->crtc) { |
| 570 | vc4_plane_state = to_vc4_plane_state(old_plane_state); |
| 571 | load_state->membus_load -= vc4_plane_state->membus_load; |
| 572 | load_state->hvs_load -= vc4_plane_state->hvs_load; |
| 573 | } |
| 574 | |
| 575 | if (new_plane_state->fb && new_plane_state->crtc) { |
| 576 | vc4_plane_state = to_vc4_plane_state(new_plane_state); |
| 577 | load_state->membus_load += vc4_plane_state->membus_load; |
| 578 | load_state->hvs_load += vc4_plane_state->hvs_load; |
| 579 | } |
| 580 | } |
| 581 | |
Paul Kocialkowski | 6b5c029 | 2019-02-20 16:51:24 +0100 | [diff] [blame] | 582 | /* Don't check the load when the tracker is disabled. */ |
| 583 | if (!vc4->load_tracker_enabled) |
| 584 | return 0; |
| 585 | |
Boris Brezillon | 4686da8 | 2019-02-20 16:51:23 +0100 | [diff] [blame] | 586 | /* The absolute limit is 2Gbyte/sec, but let's take a margin to let |
| 587 | * the system work when other blocks are accessing the memory. |
| 588 | */ |
| 589 | if (load_state->membus_load > SZ_1G + SZ_512M) |
| 590 | return -ENOSPC; |
| 591 | |
| 592 | /* HVS clock is supposed to run @ 250Mhz, let's take a margin and |
| 593 | * consider the maximum number of cycles is 240M. |
| 594 | */ |
| 595 | if (load_state->hvs_load > 240000000ULL) |
| 596 | return -ENOSPC; |
| 597 | |
| 598 | return 0; |
| 599 | } |
| 600 | |
| 601 | static struct drm_private_state * |
| 602 | vc4_load_tracker_duplicate_state(struct drm_private_obj *obj) |
| 603 | { |
| 604 | struct vc4_load_tracker_state *state; |
| 605 | |
| 606 | state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); |
| 607 | if (!state) |
| 608 | return NULL; |
| 609 | |
| 610 | __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); |
| 611 | |
| 612 | return &state->base; |
| 613 | } |
| 614 | |
| 615 | static void vc4_load_tracker_destroy_state(struct drm_private_obj *obj, |
| 616 | struct drm_private_state *state) |
| 617 | { |
| 618 | struct vc4_load_tracker_state *load_state; |
| 619 | |
| 620 | load_state = to_vc4_load_tracker_state(state); |
| 621 | kfree(load_state); |
| 622 | } |
| 623 | |
| 624 | static const struct drm_private_state_funcs vc4_load_tracker_state_funcs = { |
| 625 | .atomic_duplicate_state = vc4_load_tracker_duplicate_state, |
| 626 | .atomic_destroy_state = vc4_load_tracker_destroy_state, |
| 627 | }; |
| 628 | |
Maxime Ripard | dcda7c2 | 2020-10-29 20:01:04 +0100 | [diff] [blame] | 629 | static void vc4_load_tracker_obj_fini(struct drm_device *dev, void *unused) |
| 630 | { |
| 631 | struct vc4_dev *vc4 = to_vc4_dev(dev); |
| 632 | |
| 633 | if (!vc4->load_tracker_available) |
| 634 | return; |
| 635 | |
| 636 | drm_atomic_private_obj_fini(&vc4->load_tracker); |
| 637 | } |
| 638 | |
| 639 | static int vc4_load_tracker_obj_init(struct vc4_dev *vc4) |
| 640 | { |
| 641 | struct vc4_load_tracker_state *load_state; |
| 642 | |
| 643 | if (!vc4->load_tracker_available) |
| 644 | return 0; |
| 645 | |
| 646 | load_state = kzalloc(sizeof(*load_state), GFP_KERNEL); |
| 647 | if (!load_state) |
| 648 | return -ENOMEM; |
| 649 | |
| 650 | drm_atomic_private_obj_init(&vc4->base, &vc4->load_tracker, |
| 651 | &load_state->base, |
| 652 | &vc4_load_tracker_state_funcs); |
| 653 | |
Maxime Ripard | 3c354ed | 2020-11-05 14:56:50 +0100 | [diff] [blame] | 654 | return drmm_add_action_or_reset(&vc4->base, vc4_load_tracker_obj_fini, NULL); |
Maxime Ripard | dcda7c2 | 2020-10-29 20:01:04 +0100 | [diff] [blame] | 655 | } |
| 656 | |
Maxime Ripard | f2df84e | 2020-11-20 15:42:44 +0100 | [diff] [blame] | 657 | static struct drm_private_state * |
| 658 | vc4_hvs_channels_duplicate_state(struct drm_private_obj *obj) |
| 659 | { |
| 660 | struct vc4_hvs_state *old_state = to_vc4_hvs_state(obj->state); |
| 661 | struct vc4_hvs_state *state; |
Maxime Ripard | 9ec03d7 | 2020-12-04 16:11:35 +0100 | [diff] [blame] | 662 | unsigned int i; |
Maxime Ripard | f2df84e | 2020-11-20 15:42:44 +0100 | [diff] [blame] | 663 | |
| 664 | state = kzalloc(sizeof(*state), GFP_KERNEL); |
| 665 | if (!state) |
| 666 | return NULL; |
| 667 | |
| 668 | __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); |
| 669 | |
Maxime Ripard | f2df84e | 2020-11-20 15:42:44 +0100 | [diff] [blame] | 670 | |
Maxime Ripard | 9ec03d7 | 2020-12-04 16:11:35 +0100 | [diff] [blame] | 671 | for (i = 0; i < HVS_NUM_CHANNELS; i++) { |
| 672 | state->fifo_state[i].in_use = old_state->fifo_state[i].in_use; |
Maxime Ripard | 9ec03d7 | 2020-12-04 16:11:35 +0100 | [diff] [blame] | 673 | } |
| 674 | |
Maxime Ripard | f2df84e | 2020-11-20 15:42:44 +0100 | [diff] [blame] | 675 | return &state->base; |
| 676 | } |
| 677 | |
| 678 | static void vc4_hvs_channels_destroy_state(struct drm_private_obj *obj, |
| 679 | struct drm_private_state *state) |
| 680 | { |
| 681 | struct vc4_hvs_state *hvs_state = to_vc4_hvs_state(state); |
Maxime Ripard | 9ec03d7 | 2020-12-04 16:11:35 +0100 | [diff] [blame] | 682 | unsigned int i; |
| 683 | |
| 684 | for (i = 0; i < HVS_NUM_CHANNELS; i++) { |
| 685 | if (!hvs_state->fifo_state[i].pending_commit) |
| 686 | continue; |
| 687 | |
| 688 | drm_crtc_commit_put(hvs_state->fifo_state[i].pending_commit); |
| 689 | } |
Maxime Ripard | f2df84e | 2020-11-20 15:42:44 +0100 | [diff] [blame] | 690 | |
| 691 | kfree(hvs_state); |
| 692 | } |
| 693 | |
| 694 | static const struct drm_private_state_funcs vc4_hvs_state_funcs = { |
| 695 | .atomic_duplicate_state = vc4_hvs_channels_duplicate_state, |
| 696 | .atomic_destroy_state = vc4_hvs_channels_destroy_state, |
| 697 | }; |
| 698 | |
| 699 | static void vc4_hvs_channels_obj_fini(struct drm_device *dev, void *unused) |
| 700 | { |
| 701 | struct vc4_dev *vc4 = to_vc4_dev(dev); |
| 702 | |
| 703 | drm_atomic_private_obj_fini(&vc4->hvs_channels); |
| 704 | } |
| 705 | |
| 706 | static int vc4_hvs_channels_obj_init(struct vc4_dev *vc4) |
| 707 | { |
| 708 | struct vc4_hvs_state *state; |
| 709 | |
| 710 | state = kzalloc(sizeof(*state), GFP_KERNEL); |
| 711 | if (!state) |
| 712 | return -ENOMEM; |
| 713 | |
Maxime Ripard | f2df84e | 2020-11-20 15:42:44 +0100 | [diff] [blame] | 714 | drm_atomic_private_obj_init(&vc4->base, &vc4->hvs_channels, |
| 715 | &state->base, |
| 716 | &vc4_hvs_state_funcs); |
| 717 | |
| 718 | return drmm_add_action_or_reset(&vc4->base, vc4_hvs_channels_obj_fini, NULL); |
| 719 | } |
| 720 | |
Maxime Ripard | b5dbc4d | 2020-11-05 14:56:54 +0100 | [diff] [blame] | 721 | /* |
| 722 | * The BCM2711 HVS has up to 7 outputs connected to the pixelvalves and |
| 723 | * the TXP (and therefore all the CRTCs found on that platform). |
| 724 | * |
| 725 | * The naive (and our initial) implementation would just iterate over |
| 726 | * all the active CRTCs, try to find a suitable FIFO, and then remove it |
| 727 | * from the pool of available FIFOs. However, there are a few corner |
| 728 | * cases that need to be considered: |
| 729 | * |
| 730 | * - When running in a dual-display setup (so with two CRTCs involved), |
| 731 | * we can update the state of a single CRTC (for example by changing |
| 732 | * its mode using xrandr under X11) without affecting the other. In |
| 733 | * this case, the other CRTC wouldn't be in the state at all, so we |
| 734 | * need to consider all the running CRTCs in the DRM device to assign |
| 735 | * a FIFO, not just the one in the state. |
| 736 | * |
Maxime Ripard | f2df84e | 2020-11-20 15:42:44 +0100 | [diff] [blame] | 737 | * - To fix the above, we can't use drm_atomic_get_crtc_state on all |
| 738 | * enabled CRTCs to pull their CRTC state into the global state, since |
| 739 | * a page flip would start considering their vblank to complete. Since |
| 740 | * we don't have a guarantee that they are actually active, that |
| 741 | * vblank might never happen, and shouldn't even be considered if we |
| 742 | * want to do a page flip on a single CRTC. That can be tested by |
| 743 | * doing a modetest -v first on HDMI1 and then on HDMI0. |
| 744 | * |
Maxime Ripard | b5dbc4d | 2020-11-05 14:56:54 +0100 | [diff] [blame] | 745 | * - Since we need the pixelvalve to be disabled and enabled back when |
| 746 | * the FIFO is changed, we should keep the FIFO assigned for as long |
| 747 | * as the CRTC is enabled, only considering it free again once that |
| 748 | * CRTC has been disabled. This can be tested by booting X11 on a |
| 749 | * single display, and changing the resolution down and then back up. |
| 750 | */ |
Maxime Ripard | a72b045 | 2020-11-05 14:56:53 +0100 | [diff] [blame] | 751 | static int vc4_pv_muxing_atomic_check(struct drm_device *dev, |
| 752 | struct drm_atomic_state *state) |
Stefan Schake | 766cc6b | 2018-04-20 05:25:44 -0700 | [diff] [blame] | 753 | { |
Maxime Ripard | f2df84e | 2020-11-20 15:42:44 +0100 | [diff] [blame] | 754 | struct vc4_hvs_state *hvs_new_state; |
Maxime Ripard | 8ba0b6d1 | 2020-09-23 10:40:32 +0200 | [diff] [blame] | 755 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
Maxime Ripard | 87ebcd4 | 2020-09-03 10:00:46 +0200 | [diff] [blame] | 756 | struct drm_crtc *crtc; |
Maxime Ripard | 03b03ef | 2020-12-04 16:11:36 +0100 | [diff] [blame] | 757 | unsigned int unassigned_channels = 0; |
Maxime Ripard | a72b045 | 2020-11-05 14:56:53 +0100 | [diff] [blame] | 758 | unsigned int i; |
Maxime Ripard | 87ebcd4 | 2020-09-03 10:00:46 +0200 | [diff] [blame] | 759 | |
Maxime Ripard | f2df84e | 2020-11-20 15:42:44 +0100 | [diff] [blame] | 760 | hvs_new_state = vc4_hvs_get_global_state(state); |
Maxime Ripard | f927767 | 2021-11-17 10:45:23 +0100 | [diff] [blame] | 761 | if (IS_ERR(hvs_new_state)) |
| 762 | return PTR_ERR(hvs_new_state); |
Maxime Ripard | 089d834 | 2020-09-17 14:16:23 +0200 | [diff] [blame] | 763 | |
Maxime Ripard | 03b03ef | 2020-12-04 16:11:36 +0100 | [diff] [blame] | 764 | for (i = 0; i < ARRAY_SIZE(hvs_new_state->fifo_state); i++) |
| 765 | if (!hvs_new_state->fifo_state[i].in_use) |
| 766 | unassigned_channels |= BIT(i); |
| 767 | |
Maxime Ripard | 8ba0b6d1 | 2020-09-23 10:40:32 +0200 | [diff] [blame] | 768 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
Maxime Ripard | f2df84e | 2020-11-20 15:42:44 +0100 | [diff] [blame] | 769 | struct vc4_crtc_state *old_vc4_crtc_state = |
| 770 | to_vc4_crtc_state(old_crtc_state); |
Maxime Ripard | 8ba0b6d1 | 2020-09-23 10:40:32 +0200 | [diff] [blame] | 771 | struct vc4_crtc_state *new_vc4_crtc_state = |
| 772 | to_vc4_crtc_state(new_crtc_state); |
Maxime Ripard | 87ebcd4 | 2020-09-03 10:00:46 +0200 | [diff] [blame] | 773 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); |
| 774 | unsigned int matching_channels; |
Maxime Ripard | d62a8ed | 2020-12-04 16:11:34 +0100 | [diff] [blame] | 775 | unsigned int channel; |
Maxime Ripard | 87ebcd4 | 2020-09-03 10:00:46 +0200 | [diff] [blame] | 776 | |
Maxime Ripard | 2820526 | 2020-11-20 15:42:45 +0100 | [diff] [blame] | 777 | /* Nothing to do here, let's skip it */ |
| 778 | if (old_crtc_state->enable == new_crtc_state->enable) |
| 779 | continue; |
| 780 | |
| 781 | /* Muxing will need to be modified, mark it as such */ |
| 782 | new_vc4_crtc_state->update_muxing = true; |
| 783 | |
| 784 | /* If we're disabling our CRTC, we put back our channel */ |
| 785 | if (!new_crtc_state->enable) { |
Maxime Ripard | 9ec03d7 | 2020-12-04 16:11:35 +0100 | [diff] [blame] | 786 | channel = old_vc4_crtc_state->assigned_channel; |
Maxime Ripard | 9ec03d7 | 2020-12-04 16:11:35 +0100 | [diff] [blame] | 787 | hvs_new_state->fifo_state[channel].in_use = false; |
Maxime Ripard | 8ba0b6d1 | 2020-09-23 10:40:32 +0200 | [diff] [blame] | 788 | new_vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED; |
Maxime Ripard | 2820526 | 2020-11-20 15:42:45 +0100 | [diff] [blame] | 789 | continue; |
Maxime Ripard | f2df84e | 2020-11-20 15:42:44 +0100 | [diff] [blame] | 790 | } |
Maxime Ripard | 8ba0b6d1 | 2020-09-23 10:40:32 +0200 | [diff] [blame] | 791 | |
Maxime Ripard | 87ebcd4 | 2020-09-03 10:00:46 +0200 | [diff] [blame] | 792 | /* |
| 793 | * The problem we have to solve here is that we have |
| 794 | * up to 7 encoders, connected to up to 6 CRTCs. |
| 795 | * |
| 796 | * Those CRTCs, depending on the instance, can be |
| 797 | * routed to 1, 2 or 3 HVS FIFOs, and we need to set |
| 798 | * the change the muxing between FIFOs and outputs in |
| 799 | * the HVS accordingly. |
| 800 | * |
| 801 | * It would be pretty hard to come up with an |
| 802 | * algorithm that would generically solve |
| 803 | * this. However, the current routing trees we support |
| 804 | * allow us to simplify a bit the problem. |
| 805 | * |
| 806 | * Indeed, with the current supported layouts, if we |
| 807 | * try to assign in the ascending crtc index order the |
| 808 | * FIFOs, we can't fall into the situation where an |
| 809 | * earlier CRTC that had multiple routes is assigned |
| 810 | * one that was the only option for a later CRTC. |
| 811 | * |
| 812 | * If the layout changes and doesn't give us that in |
| 813 | * the future, we will need to have something smarter, |
| 814 | * but it works so far. |
| 815 | */ |
Maxime Ripard | 03b03ef | 2020-12-04 16:11:36 +0100 | [diff] [blame] | 816 | matching_channels = unassigned_channels & vc4_crtc->data->hvs_available_channels; |
Maxime Ripard | d62a8ed | 2020-12-04 16:11:34 +0100 | [diff] [blame] | 817 | if (!matching_channels) |
Maxime Ripard | 87ebcd4 | 2020-09-03 10:00:46 +0200 | [diff] [blame] | 818 | return -EINVAL; |
Maxime Ripard | d62a8ed | 2020-12-04 16:11:34 +0100 | [diff] [blame] | 819 | |
| 820 | channel = ffs(matching_channels) - 1; |
| 821 | new_vc4_crtc_state->assigned_channel = channel; |
Maxime Ripard | 03b03ef | 2020-12-04 16:11:36 +0100 | [diff] [blame] | 822 | unassigned_channels &= ~BIT(channel); |
Maxime Ripard | 9ec03d7 | 2020-12-04 16:11:35 +0100 | [diff] [blame] | 823 | hvs_new_state->fifo_state[channel].in_use = true; |
Maxime Ripard | 87ebcd4 | 2020-09-03 10:00:46 +0200 | [diff] [blame] | 824 | } |
Stefan Schake | 766cc6b | 2018-04-20 05:25:44 -0700 | [diff] [blame] | 825 | |
Maxime Ripard | a72b045 | 2020-11-05 14:56:53 +0100 | [diff] [blame] | 826 | return 0; |
| 827 | } |
| 828 | |
| 829 | static int |
| 830 | vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) |
| 831 | { |
| 832 | int ret; |
| 833 | |
| 834 | ret = vc4_pv_muxing_atomic_check(dev, state); |
| 835 | if (ret) |
| 836 | return ret; |
| 837 | |
Stefan Schake | 766cc6b | 2018-04-20 05:25:44 -0700 | [diff] [blame] | 838 | ret = vc4_ctm_atomic_check(dev, state); |
| 839 | if (ret < 0) |
| 840 | return ret; |
| 841 | |
Boris Brezillon | 4686da8 | 2019-02-20 16:51:23 +0100 | [diff] [blame] | 842 | ret = drm_atomic_helper_check(dev, state); |
| 843 | if (ret) |
| 844 | return ret; |
| 845 | |
| 846 | return vc4_load_tracker_atomic_check(state); |
Stefan Schake | 766cc6b | 2018-04-20 05:25:44 -0700 | [diff] [blame] | 847 | } |
| 848 | |
Maxime Ripard | 9ec03d7 | 2020-12-04 16:11:35 +0100 | [diff] [blame] | 849 | static struct drm_mode_config_helper_funcs vc4_mode_config_helpers = { |
| 850 | .atomic_commit_setup = vc4_atomic_commit_setup, |
Maxime Ripard | f3c420f | 2020-12-04 16:11:38 +0100 | [diff] [blame] | 851 | .atomic_commit_tail = vc4_atomic_commit_tail, |
Maxime Ripard | 9ec03d7 | 2020-12-04 16:11:35 +0100 | [diff] [blame] | 852 | }; |
| 853 | |
Eric Anholt | c8b75bc | 2015-03-02 13:01:12 -0800 | [diff] [blame] | 854 | static const struct drm_mode_config_funcs vc4_mode_funcs = { |
Stefan Schake | 766cc6b | 2018-04-20 05:25:44 -0700 | [diff] [blame] | 855 | .atomic_check = vc4_atomic_check, |
Maxime Ripard | f3c420f | 2020-12-04 16:11:38 +0100 | [diff] [blame] | 856 | .atomic_commit = drm_atomic_helper_commit, |
Eric Anholt | 8375311 | 2017-06-07 17:13:36 -0700 | [diff] [blame] | 857 | .fb_create = vc4_fb_create, |
Eric Anholt | c8b75bc | 2015-03-02 13:01:12 -0800 | [diff] [blame] | 858 | }; |
| 859 | |
| 860 | int vc4_kms_load(struct drm_device *dev) |
| 861 | { |
Derek Foreman | 48666d5 | 2015-07-02 11:19:54 -0500 | [diff] [blame] | 862 | struct vc4_dev *vc4 = to_vc4_dev(dev); |
Maxime Ripard | f437bc1 | 2020-09-03 10:01:51 +0200 | [diff] [blame] | 863 | bool is_vc5 = of_device_is_compatible(dev->dev->of_node, |
| 864 | "brcm,bcm2711-vc5"); |
Eric Anholt | c8b75bc | 2015-03-02 13:01:12 -0800 | [diff] [blame] | 865 | int ret; |
| 866 | |
Maxime Ripard | f437bc1 | 2020-09-03 10:01:51 +0200 | [diff] [blame] | 867 | if (!is_vc5) { |
| 868 | vc4->load_tracker_available = true; |
| 869 | |
| 870 | /* Start with the load tracker enabled. Can be |
| 871 | * disabled through the debugfs load_tracker file. |
| 872 | */ |
| 873 | vc4->load_tracker_enabled = true; |
| 874 | } |
Paul Kocialkowski | 6b5c029 | 2019-02-20 16:51:24 +0100 | [diff] [blame] | 875 | |
Mario Kleiner | 7d2818f | 2017-06-22 03:28:11 +0200 | [diff] [blame] | 876 | /* Set support for vblank irq fast disable, before drm_vblank_init() */ |
| 877 | dev->vblank_disable_immediate = true; |
| 878 | |
Eric Anholt | c8b75bc | 2015-03-02 13:01:12 -0800 | [diff] [blame] | 879 | ret = drm_vblank_init(dev, dev->mode_config.num_crtc); |
| 880 | if (ret < 0) { |
| 881 | dev_err(dev->dev, "failed to initialize vblank\n"); |
| 882 | return ret; |
| 883 | } |
| 884 | |
Maxime Ripard | f437bc1 | 2020-09-03 10:01:51 +0200 | [diff] [blame] | 885 | if (is_vc5) { |
| 886 | dev->mode_config.max_width = 7680; |
| 887 | dev->mode_config.max_height = 7680; |
| 888 | } else { |
| 889 | dev->mode_config.max_width = 2048; |
| 890 | dev->mode_config.max_height = 2048; |
| 891 | } |
| 892 | |
Eric Anholt | c8b75bc | 2015-03-02 13:01:12 -0800 | [diff] [blame] | 893 | dev->mode_config.funcs = &vc4_mode_funcs; |
Maxime Ripard | 9ec03d7 | 2020-12-04 16:11:35 +0100 | [diff] [blame] | 894 | dev->mode_config.helper_private = &vc4_mode_config_helpers; |
Eric Anholt | c8b75bc | 2015-03-02 13:01:12 -0800 | [diff] [blame] | 895 | dev->mode_config.preferred_depth = 24; |
Eric Anholt | b501bac | 2015-11-30 12:34:01 -0800 | [diff] [blame] | 896 | dev->mode_config.async_page_flip = true; |
| 897 | |
Maxime Ripard | dcda7c2 | 2020-10-29 20:01:04 +0100 | [diff] [blame] | 898 | ret = vc4_ctm_obj_init(vc4); |
| 899 | if (ret) |
| 900 | return ret; |
Stefan Schake | 766cc6b | 2018-04-20 05:25:44 -0700 | [diff] [blame] | 901 | |
Maxime Ripard | dcda7c2 | 2020-10-29 20:01:04 +0100 | [diff] [blame] | 902 | ret = vc4_load_tracker_obj_init(vc4); |
| 903 | if (ret) |
| 904 | return ret; |
Boris Brezillon | 4686da8 | 2019-02-20 16:51:23 +0100 | [diff] [blame] | 905 | |
Maxime Ripard | f2df84e | 2020-11-20 15:42:44 +0100 | [diff] [blame] | 906 | ret = vc4_hvs_channels_obj_init(vc4); |
| 907 | if (ret) |
| 908 | return ret; |
| 909 | |
Eric Anholt | c8b75bc | 2015-03-02 13:01:12 -0800 | [diff] [blame] | 910 | drm_mode_config_reset(dev); |
| 911 | |
Eric Anholt | c8b75bc | 2015-03-02 13:01:12 -0800 | [diff] [blame] | 912 | drm_kms_helper_poll_init(dev); |
| 913 | |
| 914 | return 0; |
| 915 | } |