Mathieu Poirier | ad0dfdf | 2018-05-09 12:06:04 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
Mathieu Poirier | 0bcbf2e | 2016-02-17 17:52:01 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright(C) 2015 Linaro Limited. All rights reserved. |
| 4 | * Author: Mathieu Poirier <mathieu.poirier@linaro.org> |
Mathieu Poirier | 0bcbf2e | 2016-02-17 17:52:01 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _CORESIGHT_ETM_PERF_H |
| 8 | #define _CORESIGHT_ETM_PERF_H |
| 9 | |
Suzuki K Poulose | d25054e | 2018-09-20 13:17:55 -0600 | [diff] [blame] | 10 | #include <linux/percpu-defs.h> |
Mathieu Poirier | ca878b1 | 2016-08-25 15:19:12 -0600 | [diff] [blame] | 11 | #include "coresight-priv.h" |
| 12 | |
Mathieu Poirier | 0bcbf2e | 2016-02-17 17:52:01 -0700 | [diff] [blame] | 13 | struct coresight_device; |
Mike Leach | 94d2bac | 2021-08-18 13:40:15 -0600 | [diff] [blame] | 14 | struct cscfg_config_desc; |
Mathieu Poirier | 0bcbf2e | 2016-02-17 17:52:01 -0700 | [diff] [blame] | 15 | |
Mathieu Poirier | ca878b1 | 2016-08-25 15:19:12 -0600 | [diff] [blame] | 16 | /* |
| 17 | * In both ETMv3 and v4 the maximum number of address comparator implentable |
| 18 | * is 8. The actual number is implementation specific and will be checked |
| 19 | * when filters are applied. |
| 20 | */ |
| 21 | #define ETM_ADDR_CMP_MAX 8 |
| 22 | |
| 23 | /** |
| 24 | * struct etm_filter - single instruction range or start/stop configuration. |
| 25 | * @start_addr: The address to start tracing on. |
| 26 | * @stop_addr: The address to stop tracing on. |
| 27 | * @type: Is this a range or start/stop filter. |
| 28 | */ |
| 29 | struct etm_filter { |
| 30 | unsigned long start_addr; |
| 31 | unsigned long stop_addr; |
| 32 | enum etm_addr_type type; |
| 33 | }; |
| 34 | |
| 35 | /** |
| 36 | * struct etm_filters - set of filters for a session |
| 37 | * @etm_filter: All the filters for this session. |
| 38 | * @nr_filters: Number of filters |
| 39 | * @ssstatus: Status of the start/stop logic. |
| 40 | */ |
| 41 | struct etm_filters { |
| 42 | struct etm_filter etm_filter[ETM_ADDR_CMP_MAX]; |
| 43 | unsigned int nr_filters; |
| 44 | bool ssstatus; |
| 45 | }; |
| 46 | |
Suzuki K Poulose | d25054e | 2018-09-20 13:17:55 -0600 | [diff] [blame] | 47 | /** |
| 48 | * struct etm_event_data - Coresight specifics associated to an event |
| 49 | * @work: Handle to free allocated memory outside IRQ context. |
| 50 | * @mask: Hold the CPU(s) this event was set for. |
| 51 | * @snk_config: The sink configuration. |
Mike Leach | a0114b4 | 2021-08-18 13:40:17 -0600 | [diff] [blame] | 52 | * @cfg_hash: The hash id of any coresight config selected. |
Suzuki K Poulose | d25054e | 2018-09-20 13:17:55 -0600 | [diff] [blame] | 53 | * @path: An array of path, each slot for one CPU. |
| 54 | */ |
| 55 | struct etm_event_data { |
| 56 | struct work_struct work; |
| 57 | cpumask_t mask; |
| 58 | void *snk_config; |
Mike Leach | a0114b4 | 2021-08-18 13:40:17 -0600 | [diff] [blame] | 59 | u32 cfg_hash; |
Suzuki K Poulose | d25054e | 2018-09-20 13:17:55 -0600 | [diff] [blame] | 60 | struct list_head * __percpu *path; |
| 61 | }; |
Mathieu Poirier | ca878b1 | 2016-08-25 15:19:12 -0600 | [diff] [blame] | 62 | |
Kim Phillips | b812711 | 2020-09-28 10:34:51 -0600 | [diff] [blame] | 63 | #if IS_ENABLED(CONFIG_CORESIGHT) |
Mathieu Poirier | 0bcbf2e | 2016-02-17 17:52:01 -0700 | [diff] [blame] | 64 | int etm_perf_symlink(struct coresight_device *csdev, bool link); |
Mathieu Poirier | bb8e370 | 2019-01-31 11:47:09 -0700 | [diff] [blame] | 65 | int etm_perf_add_symlink_sink(struct coresight_device *csdev); |
| 66 | void etm_perf_del_symlink_sink(struct coresight_device *csdev); |
Suzuki K Poulose | d25054e | 2018-09-20 13:17:55 -0600 | [diff] [blame] | 67 | static inline void *etm_perf_sink_config(struct perf_output_handle *handle) |
| 68 | { |
| 69 | struct etm_event_data *data = perf_get_aux(handle); |
Mathieu Poirier | 0bcbf2e | 2016-02-17 17:52:01 -0700 | [diff] [blame] | 70 | |
Suzuki K Poulose | d25054e | 2018-09-20 13:17:55 -0600 | [diff] [blame] | 71 | if (data) |
| 72 | return data->snk_config; |
| 73 | return NULL; |
| 74 | } |
Mike Leach | 94d2bac | 2021-08-18 13:40:15 -0600 | [diff] [blame] | 75 | int etm_perf_add_symlink_cscfg(struct device *dev, |
| 76 | struct cscfg_config_desc *config_desc); |
| 77 | void etm_perf_del_symlink_cscfg(struct cscfg_config_desc *config_desc); |
Mathieu Poirier | 0bcbf2e | 2016-02-17 17:52:01 -0700 | [diff] [blame] | 78 | #else |
| 79 | static inline int etm_perf_symlink(struct coresight_device *csdev, bool link) |
| 80 | { return -EINVAL; } |
Mathieu Poirier | bb8e370 | 2019-01-31 11:47:09 -0700 | [diff] [blame] | 81 | int etm_perf_add_symlink_sink(struct coresight_device *csdev) |
| 82 | { return -EINVAL; } |
| 83 | void etm_perf_del_symlink_sink(struct coresight_device *csdev) {} |
Suzuki K Poulose | d25054e | 2018-09-20 13:17:55 -0600 | [diff] [blame] | 84 | static inline void *etm_perf_sink_config(struct perf_output_handle *handle) |
| 85 | { |
| 86 | return NULL; |
| 87 | } |
Mike Leach | 94d2bac | 2021-08-18 13:40:15 -0600 | [diff] [blame] | 88 | int etm_perf_add_symlink_cscfg(struct device *dev, |
| 89 | struct cscfg_config_desc *config_desc) |
| 90 | { return -EINVAL; } |
| 91 | void etm_perf_del_symlink_cscfg(struct cscfg_config_desc *config_desc) {} |
Suzuki K Poulose | d25054e | 2018-09-20 13:17:55 -0600 | [diff] [blame] | 92 | |
Mathieu Poirier | 0bcbf2e | 2016-02-17 17:52:01 -0700 | [diff] [blame] | 93 | #endif /* CONFIG_CORESIGHT */ |
| 94 | |
Tingwei Zhang | 8e264c5 | 2020-09-28 10:35:12 -0600 | [diff] [blame] | 95 | int __init etm_perf_init(void); |
Mike Leach | 85e2414c | 2021-08-18 13:40:12 -0600 | [diff] [blame] | 96 | void etm_perf_exit(void); |
Tingwei Zhang | 8e264c5 | 2020-09-28 10:35:12 -0600 | [diff] [blame] | 97 | |
Mathieu Poirier | 0bcbf2e | 2016-02-17 17:52:01 -0700 | [diff] [blame] | 98 | #endif |