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Michal Simekeedbdab2009-03-27 14:25:49 +01001/*
Michal Simek968674b2013-08-27 10:48:29 +02002 * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2012-2013 Xilinx, Inc.
Michal Simekeedbdab2009-03-27 14:25:49 +01004 * Copyright (C) 2007-2009 PetaLogix
5 * Copyright (C) 2006 Atmark Techno, Inc.
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11
Grant Likely2462bac2012-01-26 14:10:13 -070012#include <linux/irqdomain.h>
Michal Simekeedbdab2009-03-27 14:25:49 +010013#include <linux/irq.h>
Joel Porquetfd4b2672015-07-07 17:13:15 -040014#include <linux/irqchip.h>
Zubair Lutfullah Kakakhel9689c992016-11-14 12:13:49 +000015#include <linux/irqchip/chained_irq.h>
Michal Simekbcff6612013-08-27 10:49:00 +020016#include <linux/of_address.h>
Michal Simekeedbdab2009-03-27 14:25:49 +010017#include <linux/io.h>
Zubair Lutfullah Kakakhel591db742016-11-14 12:13:47 +000018#include <linux/jump_label.h>
John Williams892ee922009-07-29 22:08:40 +100019#include <linux/bug.h>
Zubair Lutfullah Kakakhel9689c992016-11-14 12:13:49 +000020#include <linux/of_irq.h>
Michal Simekeedbdab2009-03-27 14:25:49 +010021
Michal Simekeedbdab2009-03-27 14:25:49 +010022/* No one else should require these constants, so define them locally here. */
23#define ISR 0x00 /* Interrupt Status Register */
24#define IPR 0x04 /* Interrupt Pending Register */
25#define IER 0x08 /* Interrupt Enable Register */
26#define IAR 0x0c /* Interrupt Acknowledge Register */
27#define SIE 0x10 /* Set Interrupt Enable bits */
28#define CIE 0x14 /* Clear Interrupt Enable bits */
29#define IVR 0x18 /* Interrupt Vector Register */
30#define MER 0x1c /* Master Enable Register */
31
32#define MER_ME (1<<0)
33#define MER_HIE (1<<1)
34
Michal Simek1e364922022-03-04 08:51:29 +010035#define SPURIOUS_IRQ (-1U)
36
Zubair Lutfullah Kakakhel591db742016-11-14 12:13:47 +000037static DEFINE_STATIC_KEY_FALSE(xintc_is_be);
Michal Simek1aa12432014-02-24 14:56:32 +010038
Zubair Lutfullah Kakakhel591db742016-11-14 12:13:47 +000039struct xintc_irq_chip {
40 void __iomem *base;
41 struct irq_domain *root_domain;
42 u32 intr_mask;
Mubin Sayyed67862a32020-03-17 18:25:57 +053043 u32 nr_irq;
Zubair Lutfullah Kakakhel591db742016-11-14 12:13:47 +000044};
45
Mubin Sayyed67862a32020-03-17 18:25:57 +053046static struct xintc_irq_chip *primary_intc;
Zubair Lutfullah Kakakhel591db742016-11-14 12:13:47 +000047
Mubin Sayyed67862a32020-03-17 18:25:57 +053048static void xintc_write(struct xintc_irq_chip *irqc, int reg, u32 data)
Michal Simek1aa12432014-02-24 14:56:32 +010049{
Zubair Lutfullah Kakakhel591db742016-11-14 12:13:47 +000050 if (static_branch_unlikely(&xintc_is_be))
Mubin Sayyed67862a32020-03-17 18:25:57 +053051 iowrite32be(data, irqc->base + reg);
Zubair Lutfullah Kakakhel591db742016-11-14 12:13:47 +000052 else
Mubin Sayyed67862a32020-03-17 18:25:57 +053053 iowrite32(data, irqc->base + reg);
Michal Simek1aa12432014-02-24 14:56:32 +010054}
55
Mubin Sayyed67862a32020-03-17 18:25:57 +053056static u32 xintc_read(struct xintc_irq_chip *irqc, int reg)
Michal Simek1aa12432014-02-24 14:56:32 +010057{
Zubair Lutfullah Kakakhel591db742016-11-14 12:13:47 +000058 if (static_branch_unlikely(&xintc_is_be))
Mubin Sayyed67862a32020-03-17 18:25:57 +053059 return ioread32be(irqc->base + reg);
Zubair Lutfullah Kakakhel591db742016-11-14 12:13:47 +000060 else
Mubin Sayyed67862a32020-03-17 18:25:57 +053061 return ioread32(irqc->base + reg);
Michal Simek1aa12432014-02-24 14:56:32 +010062}
63
Thomas Gleixner6f205a42011-02-06 19:36:30 +000064static void intc_enable_or_unmask(struct irq_data *d)
Michal Simekeedbdab2009-03-27 14:25:49 +010065{
Mubin Sayyed67862a32020-03-17 18:25:57 +053066 struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
67 unsigned long mask = BIT(d->hwirq);
Michal Simek6c7a2672011-12-09 10:45:20 +010068
Zubair Lutfullah Kakakhela5734de2016-11-14 12:13:46 +000069 pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq);
steve@digidescorp.com33d9ff52009-11-17 08:43:39 -060070
71 /* ack level irqs because they can't be acked during
72 * ack function since the handle_level_irq function
73 * acks the irq before calling the interrupt handler
74 */
Thomas Gleixner4adc1922011-03-24 14:52:04 +010075 if (irqd_is_level_type(d))
Mubin Sayyed67862a32020-03-17 18:25:57 +053076 xintc_write(irqc, IAR, mask);
Michal Simek7958a682012-11-05 11:51:13 +010077
Mubin Sayyed67862a32020-03-17 18:25:57 +053078 xintc_write(irqc, SIE, mask);
Michal Simekeedbdab2009-03-27 14:25:49 +010079}
80
Thomas Gleixner6f205a42011-02-06 19:36:30 +000081static void intc_disable_or_mask(struct irq_data *d)
Michal Simekeedbdab2009-03-27 14:25:49 +010082{
Mubin Sayyed67862a32020-03-17 18:25:57 +053083 struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
84
Zubair Lutfullah Kakakhela5734de2016-11-14 12:13:46 +000085 pr_debug("irq-xilinx: disable: %ld\n", d->hwirq);
Mubin Sayyed67862a32020-03-17 18:25:57 +053086 xintc_write(irqc, CIE, BIT(d->hwirq));
Michal Simekeedbdab2009-03-27 14:25:49 +010087}
88
Thomas Gleixner6f205a42011-02-06 19:36:30 +000089static void intc_ack(struct irq_data *d)
Michal Simekeedbdab2009-03-27 14:25:49 +010090{
Mubin Sayyed67862a32020-03-17 18:25:57 +053091 struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
92
Zubair Lutfullah Kakakhela5734de2016-11-14 12:13:46 +000093 pr_debug("irq-xilinx: ack: %ld\n", d->hwirq);
Mubin Sayyed67862a32020-03-17 18:25:57 +053094 xintc_write(irqc, IAR, BIT(d->hwirq));
Michal Simekeedbdab2009-03-27 14:25:49 +010095}
96
Thomas Gleixner6f205a42011-02-06 19:36:30 +000097static void intc_mask_ack(struct irq_data *d)
Michal Simekeedbdab2009-03-27 14:25:49 +010098{
Mubin Sayyed67862a32020-03-17 18:25:57 +053099 struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
100 unsigned long mask = BIT(d->hwirq);
Michal Simek6c7a2672011-12-09 10:45:20 +0100101
Zubair Lutfullah Kakakhela5734de2016-11-14 12:13:46 +0000102 pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq);
Mubin Sayyed67862a32020-03-17 18:25:57 +0530103 xintc_write(irqc, CIE, mask);
104 xintc_write(irqc, IAR, mask);
Michal Simekeedbdab2009-03-27 14:25:49 +0100105}
106
Michal Simekeedbdab2009-03-27 14:25:49 +0100107static struct irq_chip intc_dev = {
108 .name = "Xilinx INTC",
Thomas Gleixner6f205a42011-02-06 19:36:30 +0000109 .irq_unmask = intc_enable_or_unmask,
110 .irq_mask = intc_disable_or_mask,
111 .irq_ack = intc_ack,
112 .irq_mask_ack = intc_mask_ack,
Michal Simekeedbdab2009-03-27 14:25:49 +0100113};
114
Michal Simekc0d997f2012-12-13 17:30:05 +0100115static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
Grant Likely2462bac2012-01-26 14:10:13 -0700116{
Mubin Sayyed67862a32020-03-17 18:25:57 +0530117 struct xintc_irq_chip *irqc = d->host_data;
118
119 if (irqc->intr_mask & BIT(hw)) {
Grant Likely2462bac2012-01-26 14:10:13 -0700120 irq_set_chip_and_handler_name(irq, &intc_dev,
Mubin Sayyed67862a32020-03-17 18:25:57 +0530121 handle_edge_irq, "edge");
Grant Likely2462bac2012-01-26 14:10:13 -0700122 irq_clear_status_flags(irq, IRQ_LEVEL);
123 } else {
124 irq_set_chip_and_handler_name(irq, &intc_dev,
Mubin Sayyed67862a32020-03-17 18:25:57 +0530125 handle_level_irq, "level");
Grant Likely2462bac2012-01-26 14:10:13 -0700126 irq_set_status_flags(irq, IRQ_LEVEL);
127 }
Mubin Sayyed67862a32020-03-17 18:25:57 +0530128 irq_set_chip_data(irq, irqc);
Grant Likely2462bac2012-01-26 14:10:13 -0700129 return 0;
130}
131
132static const struct irq_domain_ops xintc_irq_domain_ops = {
133 .xlate = irq_domain_xlate_onetwocell,
134 .map = xintc_map,
135};
136
Zubair Lutfullah Kakakhel9689c992016-11-14 12:13:49 +0000137static void xil_intc_irq_handler(struct irq_desc *desc)
138{
139 struct irq_chip *chip = irq_desc_get_chip(desc);
Mubin Sayyed67862a32020-03-17 18:25:57 +0530140 struct xintc_irq_chip *irqc;
Zubair Lutfullah Kakakhel9689c992016-11-14 12:13:49 +0000141
Mubin Sayyed67862a32020-03-17 18:25:57 +0530142 irqc = irq_data_get_irq_handler_data(&desc->irq_data);
Zubair Lutfullah Kakakhel9689c992016-11-14 12:13:49 +0000143 chained_irq_enter(chip, desc);
144 do {
Marc Zyngier046a6ee2021-05-04 17:42:18 +0100145 u32 hwirq = xintc_read(irqc, IVR);
146
147 if (hwirq == -1U)
Zubair Lutfullah Kakakhel9689c992016-11-14 12:13:49 +0000148 break;
Marc Zyngier046a6ee2021-05-04 17:42:18 +0100149
150 generic_handle_domain_irq(irqc->root_domain, hwirq);
Zubair Lutfullah Kakakhel9689c992016-11-14 12:13:49 +0000151 } while (true);
152 chained_irq_exit(chip, desc);
153}
154
Michal Simek1e364922022-03-04 08:51:29 +0100155static void xil_intc_handle_irq(struct pt_regs *regs)
156{
157 u32 hwirq;
158
159 do {
160 hwirq = xintc_read(primary_intc, IVR);
161 if (unlikely(hwirq == SPURIOUS_IRQ))
162 break;
163
164 generic_handle_domain_irq(primary_intc->root_domain, hwirq);
165 } while (true);
166}
167
Michal Simek8a9e90a2013-08-27 10:49:00 +0200168static int __init xilinx_intc_of_init(struct device_node *intc,
169 struct device_node *parent)
Michal Simekeedbdab2009-03-27 14:25:49 +0100170{
Zubair Lutfullah Kakakhel591db742016-11-14 12:13:47 +0000171 struct xintc_irq_chip *irqc;
Mubin Sayyed67862a32020-03-17 18:25:57 +0530172 int ret, irq;
Zubair Lutfullah Kakakhel591db742016-11-14 12:13:47 +0000173
174 irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
175 if (!irqc)
176 return -ENOMEM;
Zubair Lutfullah Kakakhel591db742016-11-14 12:13:47 +0000177 irqc->base = of_iomap(intc, 0);
178 BUG_ON(!irqc->base);
Michal Simekeedbdab2009-03-27 14:25:49 +0100179
Mubin Sayyed67862a32020-03-17 18:25:57 +0530180 ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &irqc->nr_irq);
Michal Simekbcff6612013-08-27 10:49:00 +0200181 if (ret < 0) {
Zubair Lutfullah Kakakhela5734de2016-11-14 12:13:46 +0000182 pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n");
Mubin Sayyed67862a32020-03-17 18:25:57 +0530183 goto error;
Michal Simekbcff6612013-08-27 10:49:00 +0200184 }
185
Zubair Lutfullah Kakakhel591db742016-11-14 12:13:47 +0000186 ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &irqc->intr_mask);
Michal Simekbcff6612013-08-27 10:49:00 +0200187 if (ret < 0) {
Zubair Lutfullah Kakakhel8a11da52016-11-14 12:13:50 +0000188 pr_warn("irq-xilinx: unable to read xlnx,kind-of-intr\n");
189 irqc->intr_mask = 0;
Michal Simekbcff6612013-08-27 10:49:00 +0200190 }
191
Mubin Sayyed67862a32020-03-17 18:25:57 +0530192 if (irqc->intr_mask >> irqc->nr_irq)
Zubair Lutfullah Kakakhela5734de2016-11-14 12:13:46 +0000193 pr_warn("irq-xilinx: mismatch in kind-of-intr param\n");
Michal Simekeedbdab2009-03-27 14:25:49 +0100194
Rob Herringe81f54c2017-07-18 16:43:10 -0500195 pr_info("irq-xilinx: %pOF: num_irq=%d, edge=0x%x\n",
Mubin Sayyed67862a32020-03-17 18:25:57 +0530196 intc, irqc->nr_irq, irqc->intr_mask);
Michal Simekeedbdab2009-03-27 14:25:49 +0100197
Michal Simek1aa12432014-02-24 14:56:32 +0100198
Michal Simekeedbdab2009-03-27 14:25:49 +0100199 /*
200 * Disable all external interrupts until they are
Ingo Molnara359f752021-03-22 04:21:30 +0100201 * explicitly requested.
Michal Simekeedbdab2009-03-27 14:25:49 +0100202 */
Mubin Sayyed67862a32020-03-17 18:25:57 +0530203 xintc_write(irqc, IER, 0);
Michal Simekeedbdab2009-03-27 14:25:49 +0100204
205 /* Acknowledge any pending interrupts just in case. */
Mubin Sayyed67862a32020-03-17 18:25:57 +0530206 xintc_write(irqc, IAR, 0xffffffff);
Michal Simekeedbdab2009-03-27 14:25:49 +0100207
208 /* Turn on the Master Enable. */
Mubin Sayyed67862a32020-03-17 18:25:57 +0530209 xintc_write(irqc, MER, MER_HIE | MER_ME);
210 if (xintc_read(irqc, MER) != (MER_HIE | MER_ME)) {
Zubair Lutfullah Kakakhel591db742016-11-14 12:13:47 +0000211 static_branch_enable(&xintc_is_be);
Mubin Sayyed67862a32020-03-17 18:25:57 +0530212 xintc_write(irqc, MER, MER_HIE | MER_ME);
Michal Simek1aa12432014-02-24 14:56:32 +0100213 }
Michal Simekeedbdab2009-03-27 14:25:49 +0100214
Mubin Sayyed67862a32020-03-17 18:25:57 +0530215 irqc->root_domain = irq_domain_add_linear(intc, irqc->nr_irq,
Zubair Lutfullah Kakakhel591db742016-11-14 12:13:47 +0000216 &xintc_irq_domain_ops, irqc);
217 if (!irqc->root_domain) {
218 pr_err("irq-xilinx: Unable to create IRQ domain\n");
Michal Simekc74038b2020-03-17 18:25:58 +0530219 ret = -EINVAL;
Mubin Sayyed67862a32020-03-17 18:25:57 +0530220 goto error;
Zubair Lutfullah Kakakhel591db742016-11-14 12:13:47 +0000221 }
Dan Christensen7c2c8512013-03-17 04:48:56 -0500222
Zubair Lutfullah Kakakhel9689c992016-11-14 12:13:49 +0000223 if (parent) {
224 irq = irq_of_parse_and_map(intc, 0);
225 if (irq) {
226 irq_set_chained_handler_and_data(irq,
227 xil_intc_irq_handler,
228 irqc);
229 } else {
230 pr_err("irq-xilinx: interrupts property not in DT\n");
231 ret = -EINVAL;
Mubin Sayyed67862a32020-03-17 18:25:57 +0530232 goto error;
Zubair Lutfullah Kakakhel9689c992016-11-14 12:13:49 +0000233 }
234 } else {
Mubin Sayyed67862a32020-03-17 18:25:57 +0530235 primary_intc = irqc;
Marc Zyngiere02f6c02020-03-30 10:41:58 +0100236 irq_set_default_host(primary_intc->root_domain);
Michal Simek1e364922022-03-04 08:51:29 +0100237 set_handle_irq(xil_intc_handle_irq);
Zubair Lutfullah Kakakhel9689c992016-11-14 12:13:49 +0000238 }
Michal Simek8a9e90a2013-08-27 10:49:00 +0200239
240 return 0;
Zubair Lutfullah Kakakhel591db742016-11-14 12:13:47 +0000241
Mubin Sayyed67862a32020-03-17 18:25:57 +0530242error:
243 iounmap(irqc->base);
Zubair Lutfullah Kakakhel591db742016-11-14 12:13:47 +0000244 kfree(irqc);
245 return ret;
246
Michal Simekeedbdab2009-03-27 14:25:49 +0100247}
Michal Simek8a9e90a2013-08-27 10:49:00 +0200248
Zubair Lutfullah Kakakhel83282552016-11-14 12:13:51 +0000249IRQCHIP_DECLARE(xilinx_intc_xps, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init);
250IRQCHIP_DECLARE(xilinx_intc_opb, "xlnx,opb-intc-1.00.c", xilinx_intc_of_init);