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Thomas Gleixneraf873fc2019-05-28 09:57:21 -07001// SPDX-License-Identifier: GPL-2.0-only
Maxime Coqueline37e4592015-05-22 23:03:33 +02002/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Maxime Coqueline37e4592015-05-22 23:03:33 +02005 *
6 * Inspired by time-efm32.c from Uwe Kleine-Koenig
7 */
8
9#include <linux/kernel.h>
10#include <linux/clocksource.h>
11#include <linux/clockchips.h>
Daniel Lezcano81abdbb2018-01-08 14:28:58 +010012#include <linux/delay.h>
Maxime Coqueline37e4592015-05-22 23:03:33 +020013#include <linux/irq.h>
14#include <linux/interrupt.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17#include <linux/of_irq.h>
18#include <linux/clk.h>
19#include <linux/reset.h>
Benjamin Gaignardf5ef02b2018-01-08 14:28:57 +010020#include <linux/sched_clock.h>
Benjamin Gaignardd04af492018-01-08 14:28:51 +010021#include <linux/slab.h>
22
23#include "timer-of.h"
Maxime Coqueline37e4592015-05-22 23:03:33 +020024
25#define TIM_CR1 0x00
26#define TIM_DIER 0x0c
27#define TIM_SR 0x10
28#define TIM_EGR 0x14
Benjamin Gaignard8e82df32018-01-08 14:28:55 +010029#define TIM_CNT 0x24
Maxime Coqueline37e4592015-05-22 23:03:33 +020030#define TIM_PSC 0x28
31#define TIM_ARR 0x2c
Benjamin Gaignard8e82df32018-01-08 14:28:55 +010032#define TIM_CCR1 0x34
Maxime Coqueline37e4592015-05-22 23:03:33 +020033
34#define TIM_CR1_CEN BIT(0)
Benjamin Gaignard8e82df32018-01-08 14:28:55 +010035#define TIM_CR1_UDIS BIT(1)
Maxime Coqueline37e4592015-05-22 23:03:33 +020036#define TIM_CR1_OPM BIT(3)
37#define TIM_CR1_ARPE BIT(7)
38
39#define TIM_DIER_UIE BIT(0)
Benjamin Gaignard8e82df32018-01-08 14:28:55 +010040#define TIM_DIER_CC1IE BIT(1)
Maxime Coqueline37e4592015-05-22 23:03:33 +020041
42#define TIM_SR_UIF BIT(0)
43
44#define TIM_EGR_UG BIT(0)
45
Benjamin Gaignard4744daa2018-01-08 14:28:54 +010046#define TIM_PSC_MAX USHRT_MAX
47#define TIM_PSC_CLKRATE 10000
48
Daniel Lezcano3c84e752018-01-08 14:28:56 +010049struct stm32_timer_private {
50 int bits;
51};
52
53/**
54 * stm32_timer_of_bits_set - set accessor helper
55 * @to: a timer_of structure pointer
56 * @bits: the number of bits (16 or 32)
57 *
58 * Accessor helper to set the number of bits in the timer-of private
59 * structure.
60 *
61 */
62static void stm32_timer_of_bits_set(struct timer_of *to, int bits)
63{
64 struct stm32_timer_private *pd = to->private_data;
65
66 pd->bits = bits;
67}
68
69/**
70 * stm32_timer_of_bits_get - get accessor helper
71 * @to: a timer_of structure pointer
72 *
73 * Accessor helper to get the number of bits in the timer-of private
74 * structure.
75 *
76 * Returns an integer corresponding to the number of bits.
77 */
78static int stm32_timer_of_bits_get(struct timer_of *to)
79{
80 struct stm32_timer_private *pd = to->private_data;
81
82 return pd->bits;
83}
84
Benjamin Gaignardf5ef02b2018-01-08 14:28:57 +010085static void __iomem *stm32_timer_cnt __read_mostly;
86
87static u64 notrace stm32_read_sched_clock(void)
88{
89 return readl_relaxed(stm32_timer_cnt);
90}
91
Daniel Lezcano81abdbb2018-01-08 14:28:58 +010092static struct delay_timer stm32_timer_delay;
93
94static unsigned long stm32_read_delay(void)
95{
96 return readl_relaxed(stm32_timer_cnt);
97}
98
Benjamin Gaignard8e82df32018-01-08 14:28:55 +010099static void stm32_clock_event_disable(struct timer_of *to)
100{
101 writel_relaxed(0, timer_of_base(to) + TIM_DIER);
102}
103
Daniel Lezcano103bb562018-01-08 14:28:59 +0100104/**
105 * stm32_timer_start - Start the counter without event
106 * @to: a timer_of structure pointer
107 *
108 * Start the timer in order to have the counter reset and start
109 * incrementing but disable interrupt event when there is a counter
110 * overflow. By default, the counter direction is used as upcounter.
111 */
112static void stm32_timer_start(struct timer_of *to)
Benjamin Gaignard8e82df32018-01-08 14:28:55 +0100113{
114 writel_relaxed(TIM_CR1_UDIS | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1);
115}
116
Benjamin Gaignardd04af492018-01-08 14:28:51 +0100117static int stm32_clock_event_shutdown(struct clock_event_device *clkevt)
Maxime Coqueline37e4592015-05-22 23:03:33 +0200118{
Benjamin Gaignardd04af492018-01-08 14:28:51 +0100119 struct timer_of *to = to_timer_of(clkevt);
Maxime Coqueline37e4592015-05-22 23:03:33 +0200120
Benjamin Gaignard8e82df32018-01-08 14:28:55 +0100121 stm32_clock_event_disable(to);
Benjamin Gaignardd04af492018-01-08 14:28:51 +0100122
Viresh Kumar8e8af4c2015-06-18 16:24:50 +0530123 return 0;
Maxime Coqueline37e4592015-05-22 23:03:33 +0200124}
125
126static int stm32_clock_event_set_next_event(unsigned long evt,
Benjamin Gaignardd04af492018-01-08 14:28:51 +0100127 struct clock_event_device *clkevt)
Maxime Coqueline37e4592015-05-22 23:03:33 +0200128{
Benjamin Gaignardd04af492018-01-08 14:28:51 +0100129 struct timer_of *to = to_timer_of(clkevt);
Benjamin Gaignard8e82df32018-01-08 14:28:55 +0100130 unsigned long now, next;
Maxime Coqueline37e4592015-05-22 23:03:33 +0200131
Benjamin Gaignard8e82df32018-01-08 14:28:55 +0100132 next = readl_relaxed(timer_of_base(to) + TIM_CNT) + evt;
133 writel_relaxed(next, timer_of_base(to) + TIM_CCR1);
134 now = readl_relaxed(timer_of_base(to) + TIM_CNT);
135
136 if ((next - now) > evt)
137 return -ETIME;
138
139 writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER);
140
141 return 0;
142}
143
144static int stm32_clock_event_set_periodic(struct clock_event_device *clkevt)
145{
146 struct timer_of *to = to_timer_of(clkevt);
147
Daniel Lezcano103bb562018-01-08 14:28:59 +0100148 stm32_timer_start(to);
Benjamin Gaignard8e82df32018-01-08 14:28:55 +0100149
150 return stm32_clock_event_set_next_event(timer_of_period(to), clkevt);
151}
152
153static int stm32_clock_event_set_oneshot(struct clock_event_device *clkevt)
154{
155 struct timer_of *to = to_timer_of(clkevt);
156
Daniel Lezcano103bb562018-01-08 14:28:59 +0100157 stm32_timer_start(to);
Maxime Coqueline37e4592015-05-22 23:03:33 +0200158
159 return 0;
160}
161
162static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id)
163{
Benjamin Gaignardd04af492018-01-08 14:28:51 +0100164 struct clock_event_device *clkevt = (struct clock_event_device *)dev_id;
165 struct timer_of *to = to_timer_of(clkevt);
Maxime Coqueline37e4592015-05-22 23:03:33 +0200166
Benjamin Gaignardd04af492018-01-08 14:28:51 +0100167 writel_relaxed(0, timer_of_base(to) + TIM_SR);
Maxime Coqueline37e4592015-05-22 23:03:33 +0200168
Benjamin Gaignard8e82df32018-01-08 14:28:55 +0100169 if (clockevent_state_periodic(clkevt))
170 stm32_clock_event_set_periodic(clkevt);
171 else
172 stm32_clock_event_shutdown(clkevt);
173
Benjamin Gaignardd04af492018-01-08 14:28:51 +0100174 clkevt->event_handler(clkevt);
Maxime Coqueline37e4592015-05-22 23:03:33 +0200175
176 return IRQ_HANDLED;
177}
178
Daniel Lezcano70c62cf2018-01-08 14:28:53 +0100179/**
180 * stm32_timer_width - Sort out the timer width (32/16)
181 * @to: a pointer to a timer-of structure
182 *
183 * Write the 32-bit max value and read/return the result. If the timer
184 * is 32 bits wide, the result will be UINT_MAX, otherwise it will
185 * be truncated by the 16-bit register to USHRT_MAX.
186 *
Daniel Lezcano70c62cf2018-01-08 14:28:53 +0100187 */
Daniel Lezcano3c84e752018-01-08 14:28:56 +0100188static void __init stm32_timer_set_width(struct timer_of *to)
Daniel Lezcano70c62cf2018-01-08 14:28:53 +0100189{
Daniel Lezcano3c84e752018-01-08 14:28:56 +0100190 u32 width;
191
Daniel Lezcano70c62cf2018-01-08 14:28:53 +0100192 writel_relaxed(UINT_MAX, timer_of_base(to) + TIM_ARR);
193
Daniel Lezcano3c84e752018-01-08 14:28:56 +0100194 width = readl_relaxed(timer_of_base(to) + TIM_ARR);
195
196 stm32_timer_of_bits_set(to, width == UINT_MAX ? 32 : 16);
Daniel Lezcano70c62cf2018-01-08 14:28:53 +0100197}
198
Daniel Lezcano3c84e752018-01-08 14:28:56 +0100199/**
200 * stm32_timer_set_prescaler - Compute and set the prescaler register
201 * @to: a pointer to a timer-of structure
202 *
203 * Depending on the timer width, compute the prescaler to always
204 * target a 10MHz timer rate for 16 bits. 32-bit timers are
205 * considered precise and long enough to not use the prescaler.
206 */
207static void __init stm32_timer_set_prescaler(struct timer_of *to)
Maxime Coqueline37e4592015-05-22 23:03:33 +0200208{
Daniel Lezcano3c84e752018-01-08 14:28:56 +0100209 int prescaler = 1;
Maxime Coqueline37e4592015-05-22 23:03:33 +0200210
Daniel Lezcano3c84e752018-01-08 14:28:56 +0100211 if (stm32_timer_of_bits_get(to) != 32) {
Benjamin Gaignard4744daa2018-01-08 14:28:54 +0100212 prescaler = DIV_ROUND_CLOSEST(timer_of_rate(to),
213 TIM_PSC_CLKRATE);
214 /*
215 * The prescaler register is an u16, the variable
216 * can't be greater than TIM_PSC_MAX, let's cap it in
217 * this case.
218 */
219 prescaler = prescaler < TIM_PSC_MAX ? prescaler : TIM_PSC_MAX;
Benjamin Gaignardd04af492018-01-08 14:28:51 +0100220 }
Benjamin Gaignardd04af492018-01-08 14:28:51 +0100221
222 writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC);
223 writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR);
224 writel_relaxed(0, timer_of_base(to) + TIM_SR);
Benjamin Gaignardd04af492018-01-08 14:28:51 +0100225
226 /* Adjust rate and period given the prescaler value */
227 to->of_clk.rate = DIV_ROUND_CLOSEST(to->of_clk.rate, prescaler);
228 to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ);
Daniel Lezcano3c84e752018-01-08 14:28:56 +0100229}
Benjamin Gaignardd04af492018-01-08 14:28:51 +0100230
Benjamin Gaignardf5ef02b2018-01-08 14:28:57 +0100231static int __init stm32_clocksource_init(struct timer_of *to)
232{
233 u32 bits = stm32_timer_of_bits_get(to);
234 const char *name = to->np->full_name;
235
236 /*
237 * This driver allows to register several timers and relies on
238 * the generic time framework to select the right one.
239 * However, nothing allows to do the same for the
240 * sched_clock. We are not interested in a sched_clock for the
241 * 16-bit timers but only for the 32-bit one, so if no 32-bit
242 * timer is registered yet, we select this 32-bit timer as a
243 * sched_clock.
244 */
245 if (bits == 32 && !stm32_timer_cnt) {
Daniel Lezcano103bb562018-01-08 14:28:59 +0100246
247 /*
248 * Start immediately the counter as we will be using
249 * it right after.
250 */
251 stm32_timer_start(to);
252
Benjamin Gaignardf5ef02b2018-01-08 14:28:57 +0100253 stm32_timer_cnt = timer_of_base(to) + TIM_CNT;
254 sched_clock_register(stm32_read_sched_clock, bits, timer_of_rate(to));
255 pr_info("%s: STM32 sched_clock registered\n", name);
Daniel Lezcano81abdbb2018-01-08 14:28:58 +0100256
257 stm32_timer_delay.read_current_timer = stm32_read_delay;
258 stm32_timer_delay.freq = timer_of_rate(to);
259 register_current_timer_delay(&stm32_timer_delay);
260 pr_info("%s: STM32 delay timer registered\n", name);
Benjamin Gaignardf5ef02b2018-01-08 14:28:57 +0100261 }
262
263 return clocksource_mmio_init(timer_of_base(to) + TIM_CNT, name,
264 timer_of_rate(to), bits == 32 ? 250 : 100,
265 bits, clocksource_mmio_readl_up);
266}
267
Daniel Lezcano3c84e752018-01-08 14:28:56 +0100268static void __init stm32_clockevent_init(struct timer_of *to)
269{
270 u32 bits = stm32_timer_of_bits_get(to);
271
272 to->clkevt.name = to->np->full_name;
273 to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
274 to->clkevt.set_state_shutdown = stm32_clock_event_shutdown;
275 to->clkevt.set_state_periodic = stm32_clock_event_set_periodic;
276 to->clkevt.set_state_oneshot = stm32_clock_event_set_oneshot;
277 to->clkevt.tick_resume = stm32_clock_event_shutdown;
278 to->clkevt.set_next_event = stm32_clock_event_set_next_event;
279 to->clkevt.rating = bits == 32 ? 250 : 100;
280
281 clockevents_config_and_register(&to->clkevt, timer_of_rate(to), 0x1,
282 (1 << bits) - 1);
Benjamin Gaignardd04af492018-01-08 14:28:51 +0100283
284 pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n",
Daniel Lezcano3c84e752018-01-08 14:28:56 +0100285 to->np, bits);
Benjamin Gaignardd04af492018-01-08 14:28:51 +0100286}
287
288static int __init stm32_timer_init(struct device_node *node)
289{
290 struct reset_control *rstc;
291 struct timer_of *to;
292 int ret;
293
294 to = kzalloc(sizeof(*to), GFP_KERNEL);
295 if (!to)
Daniel Lezcanoe0aeca3d2018-01-08 14:28:50 +0100296 return -ENOMEM;
297
Benjamin Gaignardd04af492018-01-08 14:28:51 +0100298 to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE;
299 to->of_irq.handler = stm32_clock_event_handler;
Maxime Coqueline37e4592015-05-22 23:03:33 +0200300
Benjamin Gaignardd04af492018-01-08 14:28:51 +0100301 ret = timer_of_init(node, to);
302 if (ret)
303 goto err;
Maxime Coqueline37e4592015-05-22 23:03:33 +0200304
Daniel Lezcano3c84e752018-01-08 14:28:56 +0100305 to->private_data = kzalloc(sizeof(struct stm32_timer_private),
306 GFP_KERNEL);
Julia Lawalla26ed662018-06-10 16:24:15 +0200307 if (!to->private_data) {
308 ret = -ENOMEM;
Daniel Lezcano3c84e752018-01-08 14:28:56 +0100309 goto deinit;
Julia Lawalla26ed662018-06-10 16:24:15 +0200310 }
Daniel Lezcano3c84e752018-01-08 14:28:56 +0100311
Benjamin Gaignardd04af492018-01-08 14:28:51 +0100312 rstc = of_reset_control_get(node, NULL);
Maxime Coqueline37e4592015-05-22 23:03:33 +0200313 if (!IS_ERR(rstc)) {
314 reset_control_assert(rstc);
315 reset_control_deassert(rstc);
316 }
317
Daniel Lezcano3c84e752018-01-08 14:28:56 +0100318 stm32_timer_set_width(to);
319
320 stm32_timer_set_prescaler(to);
321
Benjamin Gaignardf5ef02b2018-01-08 14:28:57 +0100322 ret = stm32_clocksource_init(to);
323 if (ret)
324 goto deinit;
325
Benjamin Gaignardd04af492018-01-08 14:28:51 +0100326 stm32_clockevent_init(to);
327 return 0;
Daniel Lezcano3c84e752018-01-08 14:28:56 +0100328
329deinit:
330 timer_of_cleanup(to);
Benjamin Gaignardd04af492018-01-08 14:28:51 +0100331err:
332 kfree(to);
Daniel Lezcano38d94c52016-06-06 23:28:17 +0200333 return ret;
Maxime Coqueline37e4592015-05-22 23:03:33 +0200334}
335
Benjamin Gaignardd04af492018-01-08 14:28:51 +0100336TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_timer_init);