blob: f454ddd9bbaa6268b21f465ff607d4546e60bf01 [file] [log] [blame]
Roger Quadros68989fe2020-09-15 14:45:41 +03001# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/usb/cdns,usb3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
Krzysztof Kozlowski84e85352022-12-16 17:38:12 +01007title: Cadence USBSS-DRD controller
Roger Quadros68989fe2020-09-15 14:45:41 +03008
9maintainers:
10 - Pawel Laszczak <pawell@cadence.com>
11
12properties:
13 compatible:
14 const: cdns,usb3
15
16 reg:
17 items:
18 - description: OTG controller registers
19 - description: XHCI Host controller registers
20 - description: DEVICE controller registers
21
22 reg-names:
23 items:
24 - const: otg
25 - const: xhci
26 - const: dev
27
28 interrupts:
Peter Chen1bc514d2020-10-20 10:44:06 +080029 minItems: 3
Roger Quadros68989fe2020-09-15 14:45:41 +030030 items:
Roger Quadros68989fe2020-09-15 14:45:41 +030031 - description: XHCI host controller interrupt
32 - description: Device controller interrupt
Geert Uytterhoeven309f5d72021-05-27 21:39:52 +020033 - description: OTG/DRD controller interrupt
Peter Chen1bc514d2020-10-20 10:44:06 +080034 - description: interrupt used to wake up core, e.g when usbcmd.rs is
35 cleared by xhci core, this interrupt is optional
Roger Quadros68989fe2020-09-15 14:45:41 +030036
37 interrupt-names:
Peter Chen1bc514d2020-10-20 10:44:06 +080038 minItems: 3
Roger Quadros68989fe2020-09-15 14:45:41 +030039 items:
40 - const: host
41 - const: peripheral
42 - const: otg
Peter Chen1bc514d2020-10-20 10:44:06 +080043 - const: wakeup
Roger Quadros68989fe2020-09-15 14:45:41 +030044
Frank Li1899e792024-06-07 11:41:19 -040045 port:
46 $ref: /schemas/graph.yaml#/properties/port
47 description:
48 This port is used with the 'usb-role-switch' property to connect the
49 cdns3 to type C connector.
Roger Quadros68989fe2020-09-15 14:45:41 +030050
51 maximum-speed:
52 enum: [super-speed, high-speed, full-speed]
53
54 phys:
Rob Herring6ad88382020-04-20 21:24:47 -050055 minItems: 1
56 maxItems: 2
Roger Quadros68989fe2020-09-15 14:45:41 +030057
58 phy-names:
59 minItems: 1
60 maxItems: 2
61 items:
62 anyOf:
63 - const: cdns3,usb2-phy
64 - const: cdns3,usb3-phy
65
66 cdns,on-chip-buff-size:
67 description:
68 size of memory intended as internal memory for endpoints
69 buffers expressed in KB
Frank Li50a17262023-05-15 12:20:52 -040070 $ref: /schemas/types.yaml#/definitions/uint16
Roger Quadros68989fe2020-09-15 14:45:41 +030071
Roger Quadros5261e48f2020-09-15 14:45:42 +030072 cdns,phyrst-a-enable:
73 description: Enable resetting of PHY if Rx fail is detected
74 type: boolean
75
Frank Li1899e792024-06-07 11:41:19 -040076dependencies:
77 port: [ usb-role-switch ]
78
Roger Quadros68989fe2020-09-15 14:45:41 +030079required:
80 - compatible
81 - reg
82 - reg-names
83 - interrupts
Aswath Govindrajuab1150e2021-05-28 11:36:57 +053084 - interrupt-names
Roger Quadros68989fe2020-09-15 14:45:41 +030085
Frank Li1899e792024-06-07 11:41:19 -040086allOf:
87 - $ref: usb-drd.yaml#
88
89unevaluatedProperties: false
Roger Quadros68989fe2020-09-15 14:45:41 +030090
91examples:
92 - |
93 #include <dt-bindings/interrupt-controller/arm-gic.h>
94 bus {
95 #address-cells = <2>;
96 #size-cells = <2>;
97
98 usb@6000000 {
99 compatible = "cdns,usb3";
100 reg = <0x00 0x6000000 0x00 0x10000>,
101 <0x00 0x6010000 0x00 0x10000>,
102 <0x00 0x6020000 0x00 0x10000>;
103 reg-names = "otg", "xhci", "dev";
104 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
107 interrupt-names = "host", "peripheral", "otg";
108 maximum-speed = "super-speed";
109 dr_mode = "otg";
110 };
111 };