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Thomas Gleixnera636cd62019-05-19 15:51:34 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +02002/*
3 * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board
4 *
5 * Copyright (C) 2011 Atmel,
6 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +02007 */
8/dts-v1/;
Jean-Christophe PLAGNIOL-VILLARD6db64d22013-05-15 01:21:50 +08009#include "at91sam9g45.dtsi"
Alexandre Belloni66844c72014-03-19 00:15:41 +010010#include <dt-bindings/pwm/pwm.h>
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020011
12/ {
13 model = "Atmel AT91SAM9M10G45-EK";
14 compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9";
15
16 chosen {
Alexandre Belloniaa070462015-06-03 14:24:10 +020017 bootargs = "mem=64M root=/dev/mtdblock1 rw rootfstype=jffs2";
18 stdout-path = "serial0:115200n8";
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020019 };
20
Ludovic Desrochesdcce6ce2012-04-02 20:44:20 +020021 memory {
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020022 reg = <0x70000000 0x4000000>;
23 };
24
Jean-Christophe PLAGNIOL-VILLARDeb5e76f2012-03-02 20:44:23 +080025 clocks {
Alexandre Belloni4c67a132014-06-13 20:01:51 +020026 slow_xtal {
27 clock-frequency = <32768>;
28 };
29
30 main_xtal {
31 clock-frequency = <12000000>;
32 };
Jean-Christophe PLAGNIOL-VILLARDeb5e76f2012-03-02 20:44:23 +080033 };
34
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020035 ahb {
36 apb {
37 dbgu: serial@ffffee00 {
38 status = "okay";
39 };
40
Alexandre Bellonifb0f84f2016-06-08 18:12:31 +020041 tcb0: timer@fff7c000 {
42 timer@0 {
43 compatible = "atmel,tcb-timer";
44 reg = <0>, <1>;
45 };
46
47 timer@2 {
48 compatible = "atmel,tcb-timer";
49 reg = <2>;
50 };
51 };
52
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020053 usart1: serial@fff90000 {
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +080054 pinctrl-0 =
55 <&pinctrl_usart1
56 &pinctrl_usart1_rts
57 &pinctrl_usart1_cts>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020058 status = "okay";
59 };
Nicolas Ferre0d4f99d2011-12-05 18:03:05 +010060
61 macb0: ethernet@fffbc000 {
62 phy-mode = "rmii";
63 status = "okay";
64 };
Ludovic Desrochesfbc18712012-09-12 08:42:17 +020065
66 i2c0: i2c@fff84000 {
67 status = "okay";
Josh Wu917cdc52015-06-16 18:08:34 +080068 ov2640: camera@30 {
69 compatible = "ovti,ov2640";
70 reg = <0x30>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
73 resetb-gpios = <&pioD 12 GPIO_ACTIVE_LOW>;
74 pwdn-gpios = <&pioD 13 GPIO_ACTIVE_HIGH>;
75 clocks = <&pck1>;
76 clock-names = "xvclk";
77 assigned-clocks = <&pck1>;
78 assigned-clock-rates = <25000000>;
79
80 port {
81 ov2640_0: endpoint {
82 remote-endpoint = <&isi_0>;
83 bus-width = <8>;
84 };
85 };
86 };
Ludovic Desrochesfbc18712012-09-12 08:42:17 +020087 };
88
89 i2c1: i2c@fff88000 {
90 status = "okay";
91 };
Ludovic Desroches4134a452012-11-19 12:24:02 +010092
Wenyou Yangc77bcef2013-05-31 11:11:33 +080093 watchdog@fffffd40 {
94 status = "okay";
95 };
96
Ludovic Desroches4134a452012-11-19 12:24:02 +010097 mmc0: mmc@fff80000 {
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +080098 pinctrl-0 = <
99 &pinctrl_board_mmc0
100 &pinctrl_mmc0_slot0_clk_cmd_dat0
101 &pinctrl_mmc0_slot0_dat1_3>;
Ludovic Desroches4134a452012-11-19 12:24:02 +0100102 status = "okay";
103 slot@0 {
104 reg = <0>;
105 bus-width = <4>;
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800106 cd-gpios = <&pioD 10 GPIO_ACTIVE_HIGH>;
Ludovic Desroches4134a452012-11-19 12:24:02 +0100107 };
108 };
109
110 mmc1: mmc@fffd0000 {
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +0800111 pinctrl-0 = <
112 &pinctrl_board_mmc1
113 &pinctrl_mmc1_slot0_clk_cmd_dat0
114 &pinctrl_mmc1_slot0_dat1_3>;
Ludovic Desroches4134a452012-11-19 12:24:02 +0100115 status = "okay";
116 slot@0 {
117 reg = <0>;
118 bus-width = <4>;
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800119 cd-gpios = <&pioD 11 GPIO_ACTIVE_HIGH>;
120 wp-gpios = <&pioD 29 GPIO_ACTIVE_HIGH>;
Ludovic Desroches4134a452012-11-19 12:24:02 +0100121 };
122 };
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +0800123
124 pinctrl@fffff200 {
Josh Wu917cdc52015-06-16 18:08:34 +0800125 camera_sensor {
126 pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 {
127 atmel,pins =
128 <AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE>;
129 };
130
131 pinctrl_sensor_reset: sensor_reset-0 {
132 atmel,pins =
133 <AT91_PIOD 12 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
134 };
135
136 pinctrl_sensor_power: sensor_power-0 {
137 atmel,pins =
138 <AT91_PIOD 13 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
139 };
140 };
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +0800141 mmc0 {
142 pinctrl_board_mmc0: mmc0-board {
143 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800144 <AT91_PIOD 10 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD10 gpio CD pin pull up and deglitch */
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +0800145 };
146 };
147
148 mmc1 {
149 pinctrl_board_mmc1: mmc1-board {
150 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800151 <AT91_PIOD 11 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH /* PD11 gpio CD pin pull up and deglitch */
152 AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD29 gpio WP pin pull up */
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +0800153 };
154 };
Bo Sheneed97292013-12-19 11:59:18 +0800155
156 pwm0 {
157 pinctrl_pwm_leds: pwm-led {
158 atmel,pins =
159 <AT91_PIOD 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PD0 periph B */
160 AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PD31 periph B */
161 };
162 };
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +0800163 };
Richard Genoudb6811e92013-04-03 14:03:05 +0800164
165 spi0: spi@fffa4000{
166 status = "okay";
167 cs-gpios = <&pioB 3 0>, <0>, <0>, <0>;
168 mtd_dataflash@0 {
169 compatible = "atmel,at45", "atmel,dataflash";
170 spi-max-frequency = <13000000>;
171 reg = <0>;
172 };
173 };
Jean-Christophe PLAGNIOL-VILLARD24ce10e2013-05-03 20:56:01 +0800174
175 usb2: gadget@fff78000 {
176 atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>;
177 status = "okay";
178 };
Bo Sheneed97292013-12-19 11:59:18 +0800179
Dmitry Rezvanov2b179392017-06-18 21:40:49 +0900180 ac97: sound@fffac000 {
181 status = "okay";
182 };
183
Alexandre Bellonie10a57e2014-03-19 00:15:40 +0100184 adc0: adc@fffb0000 {
185 pinctrl-names = "default";
186 pinctrl-0 = <
187 &pinctrl_adc0_ad0
188 &pinctrl_adc0_ad1
189 &pinctrl_adc0_ad2
190 &pinctrl_adc0_ad3
191 &pinctrl_adc0_ad4
192 &pinctrl_adc0_ad5
193 &pinctrl_adc0_ad6
194 &pinctrl_adc0_ad7>;
195 atmel,adc-ts-wires = <4>;
196 status = "okay";
197 };
198
Josh Wu917cdc52015-06-16 18:08:34 +0800199 isi@fffb4000 {
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_isi_data_0_7>;
202 status = "okay";
203 port {
204 isi_0: endpoint {
205 remote-endpoint = <&ov2640_0>;
206 bus-width = <8>;
Josh Wubc81beb2015-09-18 19:28:22 +0800207 vsync-active = <1>;
208 hsync-active = <1>;
Josh Wu917cdc52015-06-16 18:08:34 +0800209 };
210 };
211 };
212
Bo Sheneed97292013-12-19 11:59:18 +0800213 pwm0: pwm@fffb8000 {
214 status = "okay";
215
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_pwm_leds>;
218 };
Erik van Luijk4dd79332014-09-02 12:52:12 +0200219
Boris Brezillon199ec7a2014-11-14 11:08:52 +0100220 rtc@fffffd20 {
221 atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
222 status = "okay";
223 };
224
225 gpbr: syscon@fffffd60 {
226 status = "okay";
227 };
228
Erik van Luijk4dd79332014-09-02 12:52:12 +0200229 rtc@fffffdb0 {
230 status = "okay";
231 };
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200232 };
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800233
Mathieu Malaterreed4ced02017-12-15 13:46:26 +0100234 fb0: fb@500000 {
Jean-Christophe PLAGNIOL-VILLARDf4390a72013-03-29 02:11:22 +0800235 display = <&display0>;
236 status = "okay";
237
Rob Herring8a6836e2019-05-16 17:56:14 -0500238 display0: panel {
Jean-Christophe PLAGNIOL-VILLARDf4390a72013-03-29 02:11:22 +0800239 bits-per-pixel = <32>;
240 atmel,lcdcon-backlight;
241 atmel,dmacon = <0x1>;
242 atmel,lcdcon2 = <0x80008002>;
243 atmel,guard-time = <9>;
244 atmel,lcd-wiring-mode = "RGB";
245
246 display-timings {
247 native-mode = <&timing0>;
248 timing0: timing0 {
249 clock-frequency = <9000000>;
250 hactive = <480>;
251 vactive = <272>;
252 hback-porch = <1>;
253 hfront-porch = <1>;
254 vback-porch = <40>;
255 vfront-porch = <1>;
256 hsync-len = <45>;
257 vsync-len = <1>;
258 };
259 };
260 };
261 };
262
Boris Brezillon1004a292017-05-30 11:20:53 +0200263 ebi: ebi@10000000 {
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800264 status = "okay";
265
Boris Brezillon1004a292017-05-30 11:20:53 +0200266 nand_controller: nand-controller {
267 status = "okay";
268 pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
269 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800270
Boris Brezillon1004a292017-05-30 11:20:53 +0200271 nand@3 {
272 reg = <0x3 0x0 0x800000>;
273 rb-gpios = <&pioC 8 GPIO_ACTIVE_HIGH>;
274 cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
275 nand-bus-width = <8>;
276 nand-ecc-mode = "soft";
277 nand-on-flash-bbt;
278 label = "atmel_nand";
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800279
Boris Brezillon1004a292017-05-30 11:20:53 +0200280 partitions {
281 compatible = "fixed-partitions";
282 #address-cells = <1>;
283 #size-cells = <1>;
284
285 boot@0 {
286 label = "bootstrap/uboot/kernel";
287 reg = <0x0 0x400000>;
288 };
289
290 rootfs@400000 {
291 label = "rootfs";
292 reg = <0x400000 0x3C00000>;
293 };
294
295 data@4000000 {
296 label = "data";
297 reg = <0x4000000 0xC000000>;
298 };
299 };
300 };
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800301 };
Jean-Christophe PLAGNIOL-VILLARD6a062452011-11-21 06:55:18 +0800302 };
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800303
Rob Herring8dccafa2017-10-13 12:54:51 -0500304 usb0: ohci@700000 {
Jean-Christophe PLAGNIOL-VILLARD6a062452011-11-21 06:55:18 +0800305 status = "okay";
306 num-ports = <2>;
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800307 atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW
308 &pioD 3 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800309 };
Jean-Christophe PLAGNIOL-VILLARD62c55532011-11-22 12:11:13 +0800310
Rob Herring8dccafa2017-10-13 12:54:51 -0500311 usb1: ehci@800000 {
Jean-Christophe PLAGNIOL-VILLARD62c55532011-11-22 12:11:13 +0800312 status = "okay";
313 };
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200314 };
Jean-Christophe PLAGNIOL-VILLARDf2ee7ac2012-02-04 12:26:01 +0800315
316 leds {
317 compatible = "gpio-leds";
318
319 d8 {
320 label = "d8";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800321 gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
Jean-Christophe PLAGNIOL-VILLARDf2ee7ac2012-02-04 12:26:01 +0800322 linux,default-trigger = "heartbeat";
323 };
Bo Sheneed97292013-12-19 11:59:18 +0800324 };
325
326 pwmleds {
327 compatible = "pwm-leds";
Jean-Christophe PLAGNIOL-VILLARDf2ee7ac2012-02-04 12:26:01 +0800328
329 d6 {
330 label = "d6";
Alexandre Belloni66844c72014-03-19 00:15:41 +0100331 pwms = <&pwm0 3 5000 PWM_POLARITY_INVERTED>;
Bo Sheneed97292013-12-19 11:59:18 +0800332 max-brightness = <255>;
Jean-Christophe PLAGNIOL-VILLARDf2ee7ac2012-02-04 12:26:01 +0800333 linux,default-trigger = "nand-disk";
334 };
335
336 d7 {
337 label = "d7";
Alexandre Belloni66844c72014-03-19 00:15:41 +0100338 pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>;
Bo Sheneed97292013-12-19 11:59:18 +0800339 max-brightness = <255>;
Jean-Christophe PLAGNIOL-VILLARDf2ee7ac2012-02-04 12:26:01 +0800340 linux,default-trigger = "mmc0";
341 };
342 };
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800343
344 gpio_keys {
345 compatible = "gpio-keys";
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800346
347 left_click {
348 label = "left_click";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800349 gpios = <&pioB 6 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800350 linux,code = <272>;
Sudeep Holla67ae8b92015-10-21 11:10:07 +0100351 wakeup-source;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800352 };
353
354 right_click {
355 label = "right_click";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800356 gpios = <&pioB 7 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800357 linux,code = <273>;
Sudeep Holla67ae8b92015-10-21 11:10:07 +0100358 wakeup-source;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800359 };
360
361 left {
362 label = "Joystick Left";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800363 gpios = <&pioB 14 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800364 linux,code = <105>;
365 };
366
367 right {
368 label = "Joystick Right";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800369 gpios = <&pioB 15 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800370 linux,code = <106>;
371 };
372
373 up {
374 label = "Joystick Up";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800375 gpios = <&pioB 16 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800376 linux,code = <103>;
377 };
378
379 down {
380 label = "Joystick Down";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800381 gpios = <&pioB 17 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800382 linux,code = <108>;
383 };
384
385 enter {
386 label = "Joystick Press";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800387 gpios = <&pioB 18 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800388 linux,code = <28>;
389 };
390 };
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200391};