blob: 1fea68e551f135bd41ba079e1087471f1d8cfc80 [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +02002/*
Thierry Reding89184652014-04-16 09:24:44 +02003 * Copyright (C) 2011-2014 NVIDIA CORPORATION. All rights reserved.
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +02004 */
5
Thierry Reding804cb542015-03-27 11:07:27 +01006#include <linux/bitops.h>
Thierry Redingd1313e72015-01-23 09:49:25 +01007#include <linux/debugfs.h>
Thierry Redingbc5e6de2013-01-21 11:09:06 +01008#include <linux/err.h>
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +02009#include <linux/iommu.h>
Thierry Reding89184652014-04-16 09:24:44 +020010#include <linux/kernel.h>
Hiroshi Doyu0760e8f2012-06-25 14:23:55 +030011#include <linux/of.h>
Thierry Reding89184652014-04-16 09:24:44 +020012#include <linux/of_device.h>
Nicolin Chen541f29b2020-11-25 02:10:13 -080013#include <linux/pci.h>
Thierry Reding89184652014-04-16 09:24:44 +020014#include <linux/platform_device.h>
15#include <linux/slab.h>
Dmitry Osipenko404d0b32020-09-01 23:37:30 +030016#include <linux/spinlock.h>
Joerg Roedel461a6942017-04-26 15:46:20 +020017#include <linux/dma-mapping.h>
Thierry Reding306a7f92014-07-17 13:17:24 +020018
19#include <soc/tegra/ahb.h>
Thierry Reding89184652014-04-16 09:24:44 +020020#include <soc/tegra/mc.h>
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +020021
Thierry Reding7f4c9172017-10-12 16:19:16 +020022struct tegra_smmu_group {
23 struct list_head list;
Thierry Reding1ea54402020-08-06 17:54:04 +020024 struct tegra_smmu *smmu;
Thierry Reding7f4c9172017-10-12 16:19:16 +020025 const struct tegra_smmu_group_soc *soc;
26 struct iommu_group *group;
Nicolin Chen21d3c042020-09-11 00:16:43 -070027 unsigned int swgroup;
Thierry Reding7f4c9172017-10-12 16:19:16 +020028};
29
Thierry Reding89184652014-04-16 09:24:44 +020030struct tegra_smmu {
31 void __iomem *regs;
32 struct device *dev;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +020033
Thierry Reding89184652014-04-16 09:24:44 +020034 struct tegra_mc *mc;
35 const struct tegra_smmu_soc *soc;
Stephen Warrene6bc5932012-09-04 16:36:15 -060036
Thierry Reding7f4c9172017-10-12 16:19:16 +020037 struct list_head groups;
38
Thierry Reding804cb542015-03-27 11:07:27 +010039 unsigned long pfn_mask;
Thierry Reding11cec152015-08-06 14:20:31 +020040 unsigned long tlb_mask;
Thierry Reding804cb542015-03-27 11:07:27 +010041
Thierry Reding89184652014-04-16 09:24:44 +020042 unsigned long *asids;
43 struct mutex lock;
Stephen Warrene6bc5932012-09-04 16:36:15 -060044
Thierry Reding89184652014-04-16 09:24:44 +020045 struct list_head list;
Thierry Redingd1313e72015-01-23 09:49:25 +010046
47 struct dentry *debugfs;
Joerg Roedel0b480e42017-08-09 17:41:52 +020048
49 struct iommu_device iommu; /* IOMMU Core code handle */
Stephen Warrene6bc5932012-09-04 16:36:15 -060050};
51
Thierry Reding89184652014-04-16 09:24:44 +020052struct tegra_smmu_as {
Joerg Roedeld5f1a812015-03-26 13:43:12 +010053 struct iommu_domain domain;
Thierry Reding89184652014-04-16 09:24:44 +020054 struct tegra_smmu *smmu;
55 unsigned int use_count;
Dmitry Osipenko404d0b32020-09-01 23:37:30 +030056 spinlock_t lock;
Russell King32924c72015-07-27 13:29:31 +010057 u32 *count;
Russell King853520f2015-07-27 13:29:26 +010058 struct page **pts;
Thierry Reding89184652014-04-16 09:24:44 +020059 struct page *pd;
Russell Kinge3c97192015-07-27 13:29:52 +010060 dma_addr_t pd_dma;
Thierry Reding89184652014-04-16 09:24:44 +020061 unsigned id;
62 u32 attr;
Hiroshi Doyu39abf8a2012-08-02 11:46:40 +030063};
64
Joerg Roedeld5f1a812015-03-26 13:43:12 +010065static struct tegra_smmu_as *to_smmu_as(struct iommu_domain *dom)
66{
67 return container_of(dom, struct tegra_smmu_as, domain);
68}
69
Thierry Reding89184652014-04-16 09:24:44 +020070static inline void smmu_writel(struct tegra_smmu *smmu, u32 value,
71 unsigned long offset)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +020072{
Thierry Reding89184652014-04-16 09:24:44 +020073 writel(value, smmu->regs + offset);
Joerg Roedelfe1229b2013-02-04 20:40:58 +010074}
75
Thierry Reding89184652014-04-16 09:24:44 +020076static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +020077{
Thierry Reding89184652014-04-16 09:24:44 +020078 return readl(smmu->regs + offset);
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +020079}
80
Thierry Reding89184652014-04-16 09:24:44 +020081#define SMMU_CONFIG 0x010
82#define SMMU_CONFIG_ENABLE (1 << 0)
83
84#define SMMU_TLB_CONFIG 0x14
85#define SMMU_TLB_CONFIG_HIT_UNDER_MISS (1 << 29)
86#define SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION (1 << 28)
Thierry Reding11cec152015-08-06 14:20:31 +020087#define SMMU_TLB_CONFIG_ACTIVE_LINES(smmu) \
88 ((smmu)->soc->num_tlb_lines & (smmu)->tlb_mask)
Thierry Reding89184652014-04-16 09:24:44 +020089
90#define SMMU_PTC_CONFIG 0x18
91#define SMMU_PTC_CONFIG_ENABLE (1 << 29)
92#define SMMU_PTC_CONFIG_REQ_LIMIT(x) (((x) & 0x0f) << 24)
93#define SMMU_PTC_CONFIG_INDEX_MAP(x) ((x) & 0x3f)
94
95#define SMMU_PTB_ASID 0x01c
96#define SMMU_PTB_ASID_VALUE(x) ((x) & 0x7f)
97
98#define SMMU_PTB_DATA 0x020
Russell Kinge3c97192015-07-27 13:29:52 +010099#define SMMU_PTB_DATA_VALUE(dma, attr) ((dma) >> 12 | (attr))
Thierry Reding89184652014-04-16 09:24:44 +0200100
Russell Kinge3c97192015-07-27 13:29:52 +0100101#define SMMU_MK_PDE(dma, attr) ((dma) >> SMMU_PTE_SHIFT | (attr))
Thierry Reding89184652014-04-16 09:24:44 +0200102
103#define SMMU_TLB_FLUSH 0x030
104#define SMMU_TLB_FLUSH_VA_MATCH_ALL (0 << 0)
105#define SMMU_TLB_FLUSH_VA_MATCH_SECTION (2 << 0)
106#define SMMU_TLB_FLUSH_VA_MATCH_GROUP (3 << 0)
Thierry Reding89184652014-04-16 09:24:44 +0200107#define SMMU_TLB_FLUSH_VA_SECTION(addr) ((((addr) & 0xffc00000) >> 12) | \
108 SMMU_TLB_FLUSH_VA_MATCH_SECTION)
109#define SMMU_TLB_FLUSH_VA_GROUP(addr) ((((addr) & 0xffffc000) >> 12) | \
110 SMMU_TLB_FLUSH_VA_MATCH_GROUP)
111#define SMMU_TLB_FLUSH_ASID_MATCH (1 << 31)
112
113#define SMMU_PTC_FLUSH 0x034
114#define SMMU_PTC_FLUSH_TYPE_ALL (0 << 0)
115#define SMMU_PTC_FLUSH_TYPE_ADR (1 << 0)
116
117#define SMMU_PTC_FLUSH_HI 0x9b8
118#define SMMU_PTC_FLUSH_HI_MASK 0x3
119
120/* per-SWGROUP SMMU_*_ASID register */
121#define SMMU_ASID_ENABLE (1 << 31)
122#define SMMU_ASID_MASK 0x7f
123#define SMMU_ASID_VALUE(x) ((x) & SMMU_ASID_MASK)
124
125/* page table definitions */
126#define SMMU_NUM_PDE 1024
127#define SMMU_NUM_PTE 1024
128
129#define SMMU_SIZE_PD (SMMU_NUM_PDE * 4)
130#define SMMU_SIZE_PT (SMMU_NUM_PTE * 4)
131
132#define SMMU_PDE_SHIFT 22
133#define SMMU_PTE_SHIFT 12
134
Nicolin Chen82fa58e2020-09-11 00:16:41 -0700135#define SMMU_PAGE_MASK (~(SMMU_SIZE_PT-1))
136#define SMMU_OFFSET_IN_PAGE(x) ((unsigned long)(x) & ~SMMU_PAGE_MASK)
137#define SMMU_PFN_PHYS(x) ((phys_addr_t)(x) << SMMU_PTE_SHIFT)
138#define SMMU_PHYS_PFN(x) ((unsigned long)((x) >> SMMU_PTE_SHIFT))
139
Thierry Reding89184652014-04-16 09:24:44 +0200140#define SMMU_PD_READABLE (1 << 31)
141#define SMMU_PD_WRITABLE (1 << 30)
142#define SMMU_PD_NONSECURE (1 << 29)
143
144#define SMMU_PDE_READABLE (1 << 31)
145#define SMMU_PDE_WRITABLE (1 << 30)
146#define SMMU_PDE_NONSECURE (1 << 29)
147#define SMMU_PDE_NEXT (1 << 28)
148
149#define SMMU_PTE_READABLE (1 << 31)
150#define SMMU_PTE_WRITABLE (1 << 30)
151#define SMMU_PTE_NONSECURE (1 << 29)
152
153#define SMMU_PDE_ATTR (SMMU_PDE_READABLE | SMMU_PDE_WRITABLE | \
154 SMMU_PDE_NONSECURE)
Thierry Reding89184652014-04-16 09:24:44 +0200155
Russell King34d35f82015-07-27 13:29:16 +0100156static unsigned int iova_pd_index(unsigned long iova)
157{
158 return (iova >> SMMU_PDE_SHIFT) & (SMMU_NUM_PDE - 1);
159}
160
161static unsigned int iova_pt_index(unsigned long iova)
162{
163 return (iova >> SMMU_PTE_SHIFT) & (SMMU_NUM_PTE - 1);
164}
165
Russell Kinge3c97192015-07-27 13:29:52 +0100166static bool smmu_dma_addr_valid(struct tegra_smmu *smmu, dma_addr_t addr)
Russell King4b3c7d12015-07-27 13:29:36 +0100167{
Russell Kinge3c97192015-07-27 13:29:52 +0100168 addr >>= 12;
169 return (addr & smmu->pfn_mask) == addr;
170}
Russell King4b3c7d12015-07-27 13:29:36 +0100171
Thierry Reding96d3ab82019-10-16 13:50:26 +0200172static dma_addr_t smmu_pde_to_dma(struct tegra_smmu *smmu, u32 pde)
Russell Kinge3c97192015-07-27 13:29:52 +0100173{
Thierry Reding96d3ab82019-10-16 13:50:26 +0200174 return (dma_addr_t)(pde & smmu->pfn_mask) << 12;
Russell King4b3c7d12015-07-27 13:29:36 +0100175}
176
Russell Kingb8fe0382015-07-27 13:29:41 +0100177static void smmu_flush_ptc_all(struct tegra_smmu *smmu)
178{
179 smmu_writel(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH);
180}
181
Russell Kinge3c97192015-07-27 13:29:52 +0100182static inline void smmu_flush_ptc(struct tegra_smmu *smmu, dma_addr_t dma,
Thierry Reding89184652014-04-16 09:24:44 +0200183 unsigned long offset)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200184{
Thierry Reding89184652014-04-16 09:24:44 +0200185 u32 value;
Hiroshi Doyua6870e92013-01-31 10:14:10 +0200186
Russell Kingb8fe0382015-07-27 13:29:41 +0100187 offset &= ~(smmu->mc->soc->atom_size - 1);
Hiroshi Doyua6870e92013-01-31 10:14:10 +0200188
Russell Kingb8fe0382015-07-27 13:29:41 +0100189 if (smmu->mc->soc->num_address_bits > 32) {
Russell Kinge3c97192015-07-27 13:29:52 +0100190#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
191 value = (dma >> 32) & SMMU_PTC_FLUSH_HI_MASK;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200192#else
Russell Kingb8fe0382015-07-27 13:29:41 +0100193 value = 0;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200194#endif
Russell Kingb8fe0382015-07-27 13:29:41 +0100195 smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI);
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200196 }
Hiroshi DOYU9e971a02012-07-02 14:26:38 +0300197
Russell Kinge3c97192015-07-27 13:29:52 +0100198 value = (dma + offset) | SMMU_PTC_FLUSH_TYPE_ADR;
Thierry Reding89184652014-04-16 09:24:44 +0200199 smmu_writel(smmu, value, SMMU_PTC_FLUSH);
200}
201
202static inline void smmu_flush_tlb(struct tegra_smmu *smmu)
203{
204 smmu_writel(smmu, SMMU_TLB_FLUSH_VA_MATCH_ALL, SMMU_TLB_FLUSH);
205}
206
207static inline void smmu_flush_tlb_asid(struct tegra_smmu *smmu,
208 unsigned long asid)
209{
210 u32 value;
211
Dmitry Osipenko43a05412019-03-07 01:50:07 +0300212 if (smmu->soc->num_asids == 4)
213 value = (asid & 0x3) << 29;
214 else
215 value = (asid & 0x7f) << 24;
216
217 value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_MATCH_ALL;
Thierry Reding89184652014-04-16 09:24:44 +0200218 smmu_writel(smmu, value, SMMU_TLB_FLUSH);
219}
220
221static inline void smmu_flush_tlb_section(struct tegra_smmu *smmu,
222 unsigned long asid,
223 unsigned long iova)
224{
225 u32 value;
226
Dmitry Osipenko43a05412019-03-07 01:50:07 +0300227 if (smmu->soc->num_asids == 4)
228 value = (asid & 0x3) << 29;
229 else
230 value = (asid & 0x7f) << 24;
231
232 value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_SECTION(iova);
Thierry Reding89184652014-04-16 09:24:44 +0200233 smmu_writel(smmu, value, SMMU_TLB_FLUSH);
234}
235
236static inline void smmu_flush_tlb_group(struct tegra_smmu *smmu,
237 unsigned long asid,
238 unsigned long iova)
239{
240 u32 value;
241
Dmitry Osipenko43a05412019-03-07 01:50:07 +0300242 if (smmu->soc->num_asids == 4)
243 value = (asid & 0x3) << 29;
244 else
245 value = (asid & 0x7f) << 24;
246
247 value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_GROUP(iova);
Thierry Reding89184652014-04-16 09:24:44 +0200248 smmu_writel(smmu, value, SMMU_TLB_FLUSH);
249}
250
251static inline void smmu_flush(struct tegra_smmu *smmu)
252{
Navneet Kumar446152d2019-10-16 13:50:24 +0200253 smmu_readl(smmu, SMMU_PTB_ASID);
Thierry Reding89184652014-04-16 09:24:44 +0200254}
255
256static int tegra_smmu_alloc_asid(struct tegra_smmu *smmu, unsigned int *idp)
257{
258 unsigned long id;
259
Thierry Reding89184652014-04-16 09:24:44 +0200260 id = find_first_zero_bit(smmu->asids, smmu->soc->num_asids);
Nicolin Chend5f583b2020-11-25 02:10:10 -0800261 if (id >= smmu->soc->num_asids)
Thierry Reding89184652014-04-16 09:24:44 +0200262 return -ENOSPC;
Hiroshi DOYU9e971a02012-07-02 14:26:38 +0300263
Thierry Reding89184652014-04-16 09:24:44 +0200264 set_bit(id, smmu->asids);
265 *idp = id;
Hiroshi DOYU9e971a02012-07-02 14:26:38 +0300266
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200267 return 0;
268}
269
Thierry Reding89184652014-04-16 09:24:44 +0200270static void tegra_smmu_free_asid(struct tegra_smmu *smmu, unsigned int id)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200271{
Thierry Reding89184652014-04-16 09:24:44 +0200272 clear_bit(id, smmu->asids);
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200273}
274
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100275static struct iommu_domain *tegra_smmu_domain_alloc(unsigned type)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200276{
Thierry Reding89184652014-04-16 09:24:44 +0200277 struct tegra_smmu_as *as;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200278
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100279 if (type != IOMMU_DOMAIN_UNMANAGED)
280 return NULL;
281
Thierry Reding89184652014-04-16 09:24:44 +0200282 as = kzalloc(sizeof(*as), GFP_KERNEL);
283 if (!as)
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100284 return NULL;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200285
Thierry Reding89184652014-04-16 09:24:44 +0200286 as->attr = SMMU_PD_READABLE | SMMU_PD_WRITABLE | SMMU_PD_NONSECURE;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200287
Russell King707917c2015-07-27 13:30:02 +0100288 as->pd = alloc_page(GFP_KERNEL | __GFP_DMA | __GFP_ZERO);
Thierry Reding89184652014-04-16 09:24:44 +0200289 if (!as->pd) {
290 kfree(as);
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100291 return NULL;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200292 }
293
Russell King32924c72015-07-27 13:29:31 +0100294 as->count = kcalloc(SMMU_NUM_PDE, sizeof(u32), GFP_KERNEL);
Thierry Reding89184652014-04-16 09:24:44 +0200295 if (!as->count) {
296 __free_page(as->pd);
297 kfree(as);
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100298 return NULL;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200299 }
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200300
Russell King853520f2015-07-27 13:29:26 +0100301 as->pts = kcalloc(SMMU_NUM_PDE, sizeof(*as->pts), GFP_KERNEL);
302 if (!as->pts) {
Russell King32924c72015-07-27 13:29:31 +0100303 kfree(as->count);
Russell King853520f2015-07-27 13:29:26 +0100304 __free_page(as->pd);
305 kfree(as);
306 return NULL;
307 }
308
Dmitry Osipenko404d0b32020-09-01 23:37:30 +0300309 spin_lock_init(&as->lock);
310
Thierry Reding471d9142015-03-27 11:07:25 +0100311 /* setup aperture */
Joerg Roedel7f65ef02015-04-02 13:33:19 +0200312 as->domain.geometry.aperture_start = 0;
313 as->domain.geometry.aperture_end = 0xffffffff;
314 as->domain.geometry.force_aperture = true;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200315
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100316 return &as->domain;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200317}
318
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100319static void tegra_smmu_domain_free(struct iommu_domain *domain)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200320{
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100321 struct tegra_smmu_as *as = to_smmu_as(domain);
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200322
Thierry Reding89184652014-04-16 09:24:44 +0200323 /* TODO: free page directory and page tables */
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200324
Dmitry Osipenko4f970312019-03-07 01:50:08 +0300325 WARN_ON_ONCE(as->use_count);
326 kfree(as->count);
327 kfree(as->pts);
Thierry Reding89184652014-04-16 09:24:44 +0200328 kfree(as);
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200329}
330
Thierry Reding89184652014-04-16 09:24:44 +0200331static const struct tegra_smmu_swgroup *
332tegra_smmu_find_swgroup(struct tegra_smmu *smmu, unsigned int swgroup)
Hiroshi Doyu39abf8a2012-08-02 11:46:40 +0300333{
Thierry Reding89184652014-04-16 09:24:44 +0200334 const struct tegra_smmu_swgroup *group = NULL;
335 unsigned int i;
Hiroshi Doyu39abf8a2012-08-02 11:46:40 +0300336
Thierry Reding89184652014-04-16 09:24:44 +0200337 for (i = 0; i < smmu->soc->num_swgroups; i++) {
338 if (smmu->soc->swgroups[i].swgroup == swgroup) {
339 group = &smmu->soc->swgroups[i];
Hiroshi Doyu39abf8a2012-08-02 11:46:40 +0300340 break;
Hiroshi Doyu39abf8a2012-08-02 11:46:40 +0300341 }
342 }
343
Thierry Reding89184652014-04-16 09:24:44 +0200344 return group;
Hiroshi Doyu39abf8a2012-08-02 11:46:40 +0300345}
346
Thierry Reding89184652014-04-16 09:24:44 +0200347static void tegra_smmu_enable(struct tegra_smmu *smmu, unsigned int swgroup,
348 unsigned int asid)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200349{
Thierry Reding89184652014-04-16 09:24:44 +0200350 const struct tegra_smmu_swgroup *group;
351 unsigned int i;
352 u32 value;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200353
Navneet Kumare31e5922019-10-16 13:50:25 +0200354 group = tegra_smmu_find_swgroup(smmu, swgroup);
355 if (group) {
356 value = smmu_readl(smmu, group->reg);
357 value &= ~SMMU_ASID_MASK;
358 value |= SMMU_ASID_VALUE(asid);
359 value |= SMMU_ASID_ENABLE;
360 smmu_writel(smmu, value, group->reg);
361 } else {
362 pr_warn("%s group from swgroup %u not found\n", __func__,
363 swgroup);
364 /* No point moving ahead if group was not found */
365 return;
366 }
367
Thierry Reding89184652014-04-16 09:24:44 +0200368 for (i = 0; i < smmu->soc->num_clients; i++) {
369 const struct tegra_mc_client *client = &smmu->soc->clients[i];
370
371 if (client->swgroup != swgroup)
372 continue;
373
Thierry Reding4f1ac762021-06-02 18:32:51 +0200374 value = smmu_readl(smmu, client->regs.smmu.reg);
375 value |= BIT(client->regs.smmu.bit);
376 smmu_writel(smmu, value, client->regs.smmu.reg);
Thierry Reding89184652014-04-16 09:24:44 +0200377 }
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200378}
379
Thierry Reding89184652014-04-16 09:24:44 +0200380static void tegra_smmu_disable(struct tegra_smmu *smmu, unsigned int swgroup,
381 unsigned int asid)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200382{
Thierry Reding89184652014-04-16 09:24:44 +0200383 const struct tegra_smmu_swgroup *group;
384 unsigned int i;
385 u32 value;
386
387 group = tegra_smmu_find_swgroup(smmu, swgroup);
388 if (group) {
389 value = smmu_readl(smmu, group->reg);
390 value &= ~SMMU_ASID_MASK;
391 value |= SMMU_ASID_VALUE(asid);
392 value &= ~SMMU_ASID_ENABLE;
393 smmu_writel(smmu, value, group->reg);
394 }
395
396 for (i = 0; i < smmu->soc->num_clients; i++) {
397 const struct tegra_mc_client *client = &smmu->soc->clients[i];
398
399 if (client->swgroup != swgroup)
400 continue;
401
Thierry Reding4f1ac762021-06-02 18:32:51 +0200402 value = smmu_readl(smmu, client->regs.smmu.reg);
403 value &= ~BIT(client->regs.smmu.bit);
404 smmu_writel(smmu, value, client->regs.smmu.reg);
Thierry Reding89184652014-04-16 09:24:44 +0200405 }
406}
407
408static int tegra_smmu_as_prepare(struct tegra_smmu *smmu,
409 struct tegra_smmu_as *as)
410{
411 u32 value;
Nicolin Chend5f583b2020-11-25 02:10:10 -0800412 int err = 0;
413
414 mutex_lock(&smmu->lock);
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200415
Thierry Reding89184652014-04-16 09:24:44 +0200416 if (as->use_count > 0) {
417 as->use_count++;
Nicolin Chend5f583b2020-11-25 02:10:10 -0800418 goto unlock;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200419 }
420
Russell Kinge3c97192015-07-27 13:29:52 +0100421 as->pd_dma = dma_map_page(smmu->dev, as->pd, 0, SMMU_SIZE_PD,
422 DMA_TO_DEVICE);
Nicolin Chend5f583b2020-11-25 02:10:10 -0800423 if (dma_mapping_error(smmu->dev, as->pd_dma)) {
424 err = -ENOMEM;
425 goto unlock;
426 }
Russell Kinge3c97192015-07-27 13:29:52 +0100427
428 /* We can't handle 64-bit DMA addresses */
429 if (!smmu_dma_addr_valid(smmu, as->pd_dma)) {
430 err = -ENOMEM;
431 goto err_unmap;
432 }
433
Thierry Reding89184652014-04-16 09:24:44 +0200434 err = tegra_smmu_alloc_asid(smmu, &as->id);
435 if (err < 0)
Russell Kinge3c97192015-07-27 13:29:52 +0100436 goto err_unmap;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200437
Russell Kinge3c97192015-07-27 13:29:52 +0100438 smmu_flush_ptc(smmu, as->pd_dma, 0);
Thierry Reding89184652014-04-16 09:24:44 +0200439 smmu_flush_tlb_asid(smmu, as->id);
440
441 smmu_writel(smmu, as->id & 0x7f, SMMU_PTB_ASID);
Russell Kinge3c97192015-07-27 13:29:52 +0100442 value = SMMU_PTB_DATA_VALUE(as->pd_dma, as->attr);
Thierry Reding89184652014-04-16 09:24:44 +0200443 smmu_writel(smmu, value, SMMU_PTB_DATA);
444 smmu_flush(smmu);
445
446 as->smmu = smmu;
447 as->use_count++;
448
Nicolin Chend5f583b2020-11-25 02:10:10 -0800449 mutex_unlock(&smmu->lock);
450
Thierry Reding89184652014-04-16 09:24:44 +0200451 return 0;
Russell Kinge3c97192015-07-27 13:29:52 +0100452
453err_unmap:
454 dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE);
Nicolin Chend5f583b2020-11-25 02:10:10 -0800455unlock:
456 mutex_unlock(&smmu->lock);
457
Russell Kinge3c97192015-07-27 13:29:52 +0100458 return err;
Thierry Reding89184652014-04-16 09:24:44 +0200459}
460
461static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu,
462 struct tegra_smmu_as *as)
463{
Nicolin Chend5f583b2020-11-25 02:10:10 -0800464 mutex_lock(&smmu->lock);
465
466 if (--as->use_count > 0) {
467 mutex_unlock(&smmu->lock);
Thierry Reding89184652014-04-16 09:24:44 +0200468 return;
Nicolin Chend5f583b2020-11-25 02:10:10 -0800469 }
Thierry Reding89184652014-04-16 09:24:44 +0200470
471 tegra_smmu_free_asid(smmu, as->id);
Russell Kinge3c97192015-07-27 13:29:52 +0100472
473 dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE);
474
Thierry Reding89184652014-04-16 09:24:44 +0200475 as->smmu = NULL;
Nicolin Chend5f583b2020-11-25 02:10:10 -0800476
477 mutex_unlock(&smmu->lock);
Thierry Reding89184652014-04-16 09:24:44 +0200478}
479
480static int tegra_smmu_attach_dev(struct iommu_domain *domain,
481 struct device *dev)
482{
Nicolin Chen8750d202020-11-25 02:10:11 -0800483 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
Joerg Roedela5616e22020-06-25 15:08:29 +0200484 struct tegra_smmu *smmu = dev_iommu_priv_get(dev);
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100485 struct tegra_smmu_as *as = to_smmu_as(domain);
Nicolin Chen8750d202020-11-25 02:10:11 -0800486 unsigned int index;
487 int err;
Thierry Reding89184652014-04-16 09:24:44 +0200488
Nicolin Chen8750d202020-11-25 02:10:11 -0800489 if (!fwspec)
490 return -ENOENT;
Thierry Reding89184652014-04-16 09:24:44 +0200491
Nicolin Chen8750d202020-11-25 02:10:11 -0800492 for (index = 0; index < fwspec->num_ids; index++) {
Thierry Reding89184652014-04-16 09:24:44 +0200493 err = tegra_smmu_as_prepare(smmu, as);
Nicolin Chen8750d202020-11-25 02:10:11 -0800494 if (err)
495 goto disable;
Thierry Reding89184652014-04-16 09:24:44 +0200496
Nicolin Chen8750d202020-11-25 02:10:11 -0800497 tegra_smmu_enable(smmu, fwspec->ids[index], as->id);
Thierry Reding89184652014-04-16 09:24:44 +0200498 }
499
500 if (index == 0)
501 return -ENODEV;
502
503 return 0;
Nicolin Chen8750d202020-11-25 02:10:11 -0800504
505disable:
506 while (index--) {
507 tegra_smmu_disable(smmu, fwspec->ids[index], as->id);
508 tegra_smmu_as_unprepare(smmu, as);
509 }
510
511 return err;
Thierry Reding89184652014-04-16 09:24:44 +0200512}
513
514static void tegra_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
515{
Nicolin Chen8750d202020-11-25 02:10:11 -0800516 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100517 struct tegra_smmu_as *as = to_smmu_as(domain);
Thierry Reding89184652014-04-16 09:24:44 +0200518 struct tegra_smmu *smmu = as->smmu;
Nicolin Chen8750d202020-11-25 02:10:11 -0800519 unsigned int index;
Thierry Reding89184652014-04-16 09:24:44 +0200520
Nicolin Chen8750d202020-11-25 02:10:11 -0800521 if (!fwspec)
522 return;
Thierry Reding89184652014-04-16 09:24:44 +0200523
Nicolin Chen8750d202020-11-25 02:10:11 -0800524 for (index = 0; index < fwspec->num_ids; index++) {
525 tegra_smmu_disable(smmu, fwspec->ids[index], as->id);
Thierry Reding89184652014-04-16 09:24:44 +0200526 tegra_smmu_as_unprepare(smmu, as);
Thierry Reding89184652014-04-16 09:24:44 +0200527 }
528}
529
Russell King4080e992015-07-27 13:30:12 +0100530static void tegra_smmu_set_pde(struct tegra_smmu_as *as, unsigned long iova,
531 u32 value)
532{
533 unsigned int pd_index = iova_pd_index(iova);
534 struct tegra_smmu *smmu = as->smmu;
535 u32 *pd = page_address(as->pd);
536 unsigned long offset = pd_index * sizeof(*pd);
537
538 /* Set the page directory entry first */
539 pd[pd_index] = value;
540
541 /* The flush the page directory entry from caches */
542 dma_sync_single_range_for_device(smmu->dev, as->pd_dma, offset,
543 sizeof(*pd), DMA_TO_DEVICE);
544
545 /* And flush the iommu */
546 smmu_flush_ptc(smmu, as->pd_dma, offset);
547 smmu_flush_tlb_section(smmu, as->id, iova);
548 smmu_flush(smmu);
549}
550
Russell King0b42c7c2015-07-27 13:29:21 +0100551static u32 *tegra_smmu_pte_offset(struct page *pt_page, unsigned long iova)
552{
553 u32 *pt = page_address(pt_page);
554
555 return pt + iova_pt_index(iova);
556}
557
558static u32 *tegra_smmu_pte_lookup(struct tegra_smmu_as *as, unsigned long iova,
Russell Kinge3c97192015-07-27 13:29:52 +0100559 dma_addr_t *dmap)
Russell King0b42c7c2015-07-27 13:29:21 +0100560{
561 unsigned int pd_index = iova_pd_index(iova);
Thierry Reding96d3ab82019-10-16 13:50:26 +0200562 struct tegra_smmu *smmu = as->smmu;
Russell King0b42c7c2015-07-27 13:29:21 +0100563 struct page *pt_page;
Russell Kinge3c97192015-07-27 13:29:52 +0100564 u32 *pd;
Russell King0b42c7c2015-07-27 13:29:21 +0100565
Russell King853520f2015-07-27 13:29:26 +0100566 pt_page = as->pts[pd_index];
567 if (!pt_page)
Russell King0b42c7c2015-07-27 13:29:21 +0100568 return NULL;
569
Russell Kinge3c97192015-07-27 13:29:52 +0100570 pd = page_address(as->pd);
Thierry Reding96d3ab82019-10-16 13:50:26 +0200571 *dmap = smmu_pde_to_dma(smmu, pd[pd_index]);
Russell King0b42c7c2015-07-27 13:29:21 +0100572
573 return tegra_smmu_pte_offset(pt_page, iova);
574}
575
Thierry Reding89184652014-04-16 09:24:44 +0200576static u32 *as_get_pte(struct tegra_smmu_as *as, dma_addr_t iova,
Dmitry Osipenko404d0b32020-09-01 23:37:30 +0300577 dma_addr_t *dmap, struct page *page)
Thierry Reding89184652014-04-16 09:24:44 +0200578{
Russell King34d35f82015-07-27 13:29:16 +0100579 unsigned int pde = iova_pd_index(iova);
Thierry Reding89184652014-04-16 09:24:44 +0200580 struct tegra_smmu *smmu = as->smmu;
Thierry Reding89184652014-04-16 09:24:44 +0200581
Russell King853520f2015-07-27 13:29:26 +0100582 if (!as->pts[pde]) {
Russell Kinge3c97192015-07-27 13:29:52 +0100583 dma_addr_t dma;
584
Russell Kinge3c97192015-07-27 13:29:52 +0100585 dma = dma_map_page(smmu->dev, page, 0, SMMU_SIZE_PT,
586 DMA_TO_DEVICE);
587 if (dma_mapping_error(smmu->dev, dma)) {
588 __free_page(page);
589 return NULL;
590 }
591
592 if (!smmu_dma_addr_valid(smmu, dma)) {
593 dma_unmap_page(smmu->dev, dma, SMMU_SIZE_PT,
594 DMA_TO_DEVICE);
595 __free_page(page);
596 return NULL;
597 }
598
Russell King853520f2015-07-27 13:29:26 +0100599 as->pts[pde] = page;
600
Russell King4080e992015-07-27 13:30:12 +0100601 tegra_smmu_set_pde(as, iova, SMMU_MK_PDE(dma, SMMU_PDE_ATTR |
602 SMMU_PDE_NEXT));
Russell Kinge3c97192015-07-27 13:29:52 +0100603
604 *dmap = dma;
Thierry Reding89184652014-04-16 09:24:44 +0200605 } else {
Russell King4080e992015-07-27 13:30:12 +0100606 u32 *pd = page_address(as->pd);
607
Thierry Reding96d3ab82019-10-16 13:50:26 +0200608 *dmap = smmu_pde_to_dma(smmu, pd[pde]);
Thierry Reding89184652014-04-16 09:24:44 +0200609 }
610
Russell King7ffc6f02015-08-06 14:56:39 +0200611 return tegra_smmu_pte_offset(as->pts[pde], iova);
612}
Russell King0b42c7c2015-07-27 13:29:21 +0100613
Russell King7ffc6f02015-08-06 14:56:39 +0200614static void tegra_smmu_pte_get_use(struct tegra_smmu_as *as, unsigned long iova)
615{
616 unsigned int pd_index = iova_pd_index(iova);
Thierry Reding89184652014-04-16 09:24:44 +0200617
Russell King7ffc6f02015-08-06 14:56:39 +0200618 as->count[pd_index]++;
Thierry Reding89184652014-04-16 09:24:44 +0200619}
620
Russell Kingb98e34f2015-07-27 13:29:05 +0100621static void tegra_smmu_pte_put_use(struct tegra_smmu_as *as, unsigned long iova)
Thierry Reding89184652014-04-16 09:24:44 +0200622{
Russell King34d35f82015-07-27 13:29:16 +0100623 unsigned int pde = iova_pd_index(iova);
Russell King853520f2015-07-27 13:29:26 +0100624 struct page *page = as->pts[pde];
Thierry Reding89184652014-04-16 09:24:44 +0200625
626 /*
627 * When no entries in this page table are used anymore, return the
628 * memory page to the system.
629 */
Russell King32924c72015-07-27 13:29:31 +0100630 if (--as->count[pde] == 0) {
Russell King4080e992015-07-27 13:30:12 +0100631 struct tegra_smmu *smmu = as->smmu;
632 u32 *pd = page_address(as->pd);
Thierry Reding96d3ab82019-10-16 13:50:26 +0200633 dma_addr_t pte_dma = smmu_pde_to_dma(smmu, pd[pde]);
Thierry Reding89184652014-04-16 09:24:44 +0200634
Russell King4080e992015-07-27 13:30:12 +0100635 tegra_smmu_set_pde(as, iova, 0);
Russell Kingb98e34f2015-07-27 13:29:05 +0100636
Russell Kinge3c97192015-07-27 13:29:52 +0100637 dma_unmap_page(smmu->dev, pte_dma, SMMU_SIZE_PT, DMA_TO_DEVICE);
Russell Kingb98e34f2015-07-27 13:29:05 +0100638 __free_page(page);
Russell King853520f2015-07-27 13:29:26 +0100639 as->pts[pde] = NULL;
Thierry Reding89184652014-04-16 09:24:44 +0200640 }
641}
642
Russell King8482ee52015-07-27 13:29:10 +0100643static void tegra_smmu_set_pte(struct tegra_smmu_as *as, unsigned long iova,
Russell Kinge3c97192015-07-27 13:29:52 +0100644 u32 *pte, dma_addr_t pte_dma, u32 val)
Russell King8482ee52015-07-27 13:29:10 +0100645{
646 struct tegra_smmu *smmu = as->smmu;
Nicolin Chen82fa58e2020-09-11 00:16:41 -0700647 unsigned long offset = SMMU_OFFSET_IN_PAGE(pte);
Russell King8482ee52015-07-27 13:29:10 +0100648
649 *pte = val;
650
Russell Kinge3c97192015-07-27 13:29:52 +0100651 dma_sync_single_range_for_device(smmu->dev, pte_dma, offset,
652 4, DMA_TO_DEVICE);
653 smmu_flush_ptc(smmu, pte_dma, offset);
Russell King8482ee52015-07-27 13:29:10 +0100654 smmu_flush_tlb_group(smmu, as->id, iova);
655 smmu_flush(smmu);
656}
657
Dmitry Osipenko404d0b32020-09-01 23:37:30 +0300658static struct page *as_get_pde_page(struct tegra_smmu_as *as,
659 unsigned long iova, gfp_t gfp,
660 unsigned long *flags)
661{
662 unsigned int pde = iova_pd_index(iova);
663 struct page *page = as->pts[pde];
664
665 /* at first check whether allocation needs to be done at all */
666 if (page)
667 return page;
668
669 /*
670 * In order to prevent exhaustion of the atomic memory pool, we
671 * allocate page in a sleeping context if GFP flags permit. Hence
672 * spinlock needs to be unlocked and re-locked after allocation.
673 */
674 if (!(gfp & __GFP_ATOMIC))
675 spin_unlock_irqrestore(&as->lock, *flags);
676
677 page = alloc_page(gfp | __GFP_DMA | __GFP_ZERO);
678
679 if (!(gfp & __GFP_ATOMIC))
680 spin_lock_irqsave(&as->lock, *flags);
681
682 /*
683 * In a case of blocking allocation, a concurrent mapping may win
684 * the PDE allocation. In this case the allocated page isn't needed
685 * if allocation succeeded and the allocation failure isn't fatal.
686 */
687 if (as->pts[pde]) {
688 if (page)
689 __free_page(page);
690
691 page = as->pts[pde];
692 }
693
694 return page;
695}
696
697static int
698__tegra_smmu_map(struct iommu_domain *domain, unsigned long iova,
699 phys_addr_t paddr, size_t size, int prot, gfp_t gfp,
700 unsigned long *flags)
Thierry Reding89184652014-04-16 09:24:44 +0200701{
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100702 struct tegra_smmu_as *as = to_smmu_as(domain);
Russell Kinge3c97192015-07-27 13:29:52 +0100703 dma_addr_t pte_dma;
Dmitry Osipenko404d0b32020-09-01 23:37:30 +0300704 struct page *page;
Dmitry Osipenko43d957b2019-03-07 01:50:09 +0300705 u32 pte_attrs;
Thierry Reding89184652014-04-16 09:24:44 +0200706 u32 *pte;
707
Dmitry Osipenko404d0b32020-09-01 23:37:30 +0300708 page = as_get_pde_page(as, iova, gfp, flags);
709 if (!page)
710 return -ENOMEM;
711
712 pte = as_get_pte(as, iova, &pte_dma, page);
Thierry Reding89184652014-04-16 09:24:44 +0200713 if (!pte)
Hiroshi Doyu0547c2f2012-06-25 14:23:57 +0300714 return -ENOMEM;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200715
Russell King7ffc6f02015-08-06 14:56:39 +0200716 /* If we aren't overwriting a pre-existing entry, increment use */
717 if (*pte == 0)
718 tegra_smmu_pte_get_use(as, iova);
719
Dmitry Osipenko43d957b2019-03-07 01:50:09 +0300720 pte_attrs = SMMU_PTE_NONSECURE;
721
722 if (prot & IOMMU_READ)
723 pte_attrs |= SMMU_PTE_READABLE;
724
725 if (prot & IOMMU_WRITE)
726 pte_attrs |= SMMU_PTE_WRITABLE;
727
Russell Kinge3c97192015-07-27 13:29:52 +0100728 tegra_smmu_set_pte(as, iova, pte, pte_dma,
Nicolin Chen82fa58e2020-09-11 00:16:41 -0700729 SMMU_PHYS_PFN(paddr) | pte_attrs);
Thierry Reding89184652014-04-16 09:24:44 +0200730
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200731 return 0;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200732}
733
Dmitry Osipenko404d0b32020-09-01 23:37:30 +0300734static size_t
735__tegra_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
736 size_t size, struct iommu_iotlb_gather *gather)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200737{
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100738 struct tegra_smmu_as *as = to_smmu_as(domain);
Russell Kinge3c97192015-07-27 13:29:52 +0100739 dma_addr_t pte_dma;
Thierry Reding89184652014-04-16 09:24:44 +0200740 u32 *pte;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200741
Russell Kinge3c97192015-07-27 13:29:52 +0100742 pte = tegra_smmu_pte_lookup(as, iova, &pte_dma);
Russell Kingb98e34f2015-07-27 13:29:05 +0100743 if (!pte || !*pte)
Thierry Reding89184652014-04-16 09:24:44 +0200744 return 0;
Hiroshi Doyu39abf8a2012-08-02 11:46:40 +0300745
Russell Kinge3c97192015-07-27 13:29:52 +0100746 tegra_smmu_set_pte(as, iova, pte, pte_dma, 0);
Russell Kingb98e34f2015-07-27 13:29:05 +0100747 tegra_smmu_pte_put_use(as, iova);
748
Thierry Reding89184652014-04-16 09:24:44 +0200749 return size;
750}
751
Dmitry Osipenko404d0b32020-09-01 23:37:30 +0300752static int tegra_smmu_map(struct iommu_domain *domain, unsigned long iova,
753 phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
754{
755 struct tegra_smmu_as *as = to_smmu_as(domain);
756 unsigned long flags;
757 int ret;
758
759 spin_lock_irqsave(&as->lock, flags);
760 ret = __tegra_smmu_map(domain, iova, paddr, size, prot, gfp, &flags);
761 spin_unlock_irqrestore(&as->lock, flags);
762
763 return ret;
764}
765
766static size_t tegra_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
767 size_t size, struct iommu_iotlb_gather *gather)
768{
769 struct tegra_smmu_as *as = to_smmu_as(domain);
770 unsigned long flags;
771
772 spin_lock_irqsave(&as->lock, flags);
773 size = __tegra_smmu_unmap(domain, iova, size, gather);
774 spin_unlock_irqrestore(&as->lock, flags);
775
776 return size;
777}
778
Thierry Reding89184652014-04-16 09:24:44 +0200779static phys_addr_t tegra_smmu_iova_to_phys(struct iommu_domain *domain,
780 dma_addr_t iova)
781{
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100782 struct tegra_smmu_as *as = to_smmu_as(domain);
Thierry Reding89184652014-04-16 09:24:44 +0200783 unsigned long pfn;
Russell Kinge3c97192015-07-27 13:29:52 +0100784 dma_addr_t pte_dma;
Thierry Reding89184652014-04-16 09:24:44 +0200785 u32 *pte;
786
Russell Kinge3c97192015-07-27 13:29:52 +0100787 pte = tegra_smmu_pte_lookup(as, iova, &pte_dma);
Russell King91137852015-07-27 13:29:00 +0100788 if (!pte || !*pte)
789 return 0;
790
Thierry Reding804cb542015-03-27 11:07:27 +0100791 pfn = *pte & as->smmu->pfn_mask;
Thierry Reding89184652014-04-16 09:24:44 +0200792
Nicolin Chen4fba9882020-09-11 00:16:42 -0700793 return SMMU_PFN_PHYS(pfn) + SMMU_OFFSET_IN_PAGE(iova);
Thierry Reding89184652014-04-16 09:24:44 +0200794}
795
Nicolin Chen765a9d12021-02-18 14:07:02 -0800796static struct tegra_smmu *tegra_smmu_find(struct device_node *np)
797{
798 struct platform_device *pdev;
799 struct tegra_mc *mc;
800
801 pdev = of_find_device_by_node(np);
802 if (!pdev)
803 return NULL;
804
805 mc = platform_get_drvdata(pdev);
Miaoqian Lin9826e392022-01-07 08:09:11 +0000806 if (!mc) {
807 put_device(&pdev->dev);
Nicolin Chen765a9d12021-02-18 14:07:02 -0800808 return NULL;
Miaoqian Lin9826e392022-01-07 08:09:11 +0000809 }
Nicolin Chen765a9d12021-02-18 14:07:02 -0800810
811 return mc->smmu;
812}
813
814static int tegra_smmu_configure(struct tegra_smmu *smmu, struct device *dev,
815 struct of_phandle_args *args)
816{
817 const struct iommu_ops *ops = smmu->iommu.ops;
818 int err;
819
820 err = iommu_fwspec_init(dev, &dev->of_node->fwnode, ops);
821 if (err < 0) {
822 dev_err(dev, "failed to initialize fwspec: %d\n", err);
823 return err;
824 }
825
826 err = ops->of_xlate(dev, args);
827 if (err < 0) {
828 dev_err(dev, "failed to parse SW group ID: %d\n", err);
829 iommu_fwspec_free(dev);
830 return err;
831 }
832
833 return 0;
834}
835
Joerg Roedelb287ba72020-04-29 15:37:04 +0200836static struct iommu_device *tegra_smmu_probe_device(struct device *dev)
Thierry Reding89184652014-04-16 09:24:44 +0200837{
Nicolin Chen765a9d12021-02-18 14:07:02 -0800838 struct device_node *np = dev->of_node;
839 struct tegra_smmu *smmu = NULL;
840 struct of_phandle_args args;
841 unsigned int index = 0;
842 int err;
Thierry Reding89184652014-04-16 09:24:44 +0200843
Nicolin Chen765a9d12021-02-18 14:07:02 -0800844 while (of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index,
845 &args) == 0) {
846 smmu = tegra_smmu_find(args.np);
847 if (smmu) {
848 err = tegra_smmu_configure(smmu, dev, &args);
Nicolin Chen765a9d12021-02-18 14:07:02 -0800849
Dmitry Osipenko8dfd0fa2021-03-12 18:54:39 +0300850 if (err < 0) {
851 of_node_put(args.np);
Nicolin Chen765a9d12021-02-18 14:07:02 -0800852 return ERR_PTR(err);
Dmitry Osipenko8dfd0fa2021-03-12 18:54:39 +0300853 }
Nicolin Chen765a9d12021-02-18 14:07:02 -0800854 }
855
856 of_node_put(args.np);
857 index++;
858 }
859
860 smmu = dev_iommu_priv_get(dev);
Thierry Reding7f4c9172017-10-12 16:19:16 +0200861 if (!smmu)
Joerg Roedelb287ba72020-04-29 15:37:04 +0200862 return ERR_PTR(-ENODEV);
Thierry Reding7f4c9172017-10-12 16:19:16 +0200863
Joerg Roedelb287ba72020-04-29 15:37:04 +0200864 return &smmu->iommu;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200865}
866
Nicolin Chen25938c72020-11-25 02:10:12 -0800867static void tegra_smmu_release_device(struct device *dev) {}
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200868
Thierry Reding7f4c9172017-10-12 16:19:16 +0200869static const struct tegra_smmu_group_soc *
870tegra_smmu_find_group(struct tegra_smmu *smmu, unsigned int swgroup)
871{
872 unsigned int i, j;
873
874 for (i = 0; i < smmu->soc->num_groups; i++)
875 for (j = 0; j < smmu->soc->groups[i].num_swgroups; j++)
876 if (smmu->soc->groups[i].swgroups[j] == swgroup)
877 return &smmu->soc->groups[i];
878
879 return NULL;
880}
881
Thierry Reding1ea54402020-08-06 17:54:04 +0200882static void tegra_smmu_group_release(void *iommu_data)
883{
884 struct tegra_smmu_group *group = iommu_data;
885 struct tegra_smmu *smmu = group->smmu;
886
887 mutex_lock(&smmu->lock);
888 list_del(&group->list);
889 mutex_unlock(&smmu->lock);
890}
891
Nicolin Chencf910f62020-11-25 02:10:09 -0800892static struct iommu_group *tegra_smmu_device_group(struct device *dev)
Thierry Reding7f4c9172017-10-12 16:19:16 +0200893{
Nicolin Chencf910f62020-11-25 02:10:09 -0800894 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
895 struct tegra_smmu *smmu = dev_iommu_priv_get(dev);
Thierry Reding7f4c9172017-10-12 16:19:16 +0200896 const struct tegra_smmu_group_soc *soc;
Nicolin Chencf910f62020-11-25 02:10:09 -0800897 unsigned int swgroup = fwspec->ids[0];
Thierry Reding7f4c9172017-10-12 16:19:16 +0200898 struct tegra_smmu_group *group;
Thierry Reding5b30fbf2020-08-06 17:54:03 +0200899 struct iommu_group *grp;
Thierry Reding7f4c9172017-10-12 16:19:16 +0200900
Nicolin Chen21d3c042020-09-11 00:16:43 -0700901 /* Find group_soc associating with swgroup */
Thierry Reding7f4c9172017-10-12 16:19:16 +0200902 soc = tegra_smmu_find_group(smmu, swgroup);
Thierry Reding7f4c9172017-10-12 16:19:16 +0200903
904 mutex_lock(&smmu->lock);
905
Nicolin Chen21d3c042020-09-11 00:16:43 -0700906 /* Find existing iommu_group associating with swgroup or group_soc */
Thierry Reding7f4c9172017-10-12 16:19:16 +0200907 list_for_each_entry(group, &smmu->groups, list)
Nicolin Chen21d3c042020-09-11 00:16:43 -0700908 if ((group->swgroup == swgroup) || (soc && group->soc == soc)) {
Thierry Reding5b30fbf2020-08-06 17:54:03 +0200909 grp = iommu_group_ref_get(group->group);
Thierry Reding7f4c9172017-10-12 16:19:16 +0200910 mutex_unlock(&smmu->lock);
Thierry Reding5b30fbf2020-08-06 17:54:03 +0200911 return grp;
Thierry Reding7f4c9172017-10-12 16:19:16 +0200912 }
913
914 group = devm_kzalloc(smmu->dev, sizeof(*group), GFP_KERNEL);
915 if (!group) {
916 mutex_unlock(&smmu->lock);
917 return NULL;
918 }
919
920 INIT_LIST_HEAD(&group->list);
Nicolin Chen21d3c042020-09-11 00:16:43 -0700921 group->swgroup = swgroup;
Thierry Reding1ea54402020-08-06 17:54:04 +0200922 group->smmu = smmu;
Thierry Reding7f4c9172017-10-12 16:19:16 +0200923 group->soc = soc;
924
Nicolin Chen541f29b2020-11-25 02:10:13 -0800925 if (dev_is_pci(dev))
926 group->group = pci_device_group(dev);
927 else
928 group->group = generic_device_group(dev);
929
Wei Yongjun83476bf2017-12-20 03:06:09 +0000930 if (IS_ERR(group->group)) {
Thierry Reding7f4c9172017-10-12 16:19:16 +0200931 devm_kfree(smmu->dev, group);
932 mutex_unlock(&smmu->lock);
933 return NULL;
934 }
935
Thierry Reding1ea54402020-08-06 17:54:04 +0200936 iommu_group_set_iommudata(group->group, group, tegra_smmu_group_release);
Nicolin Chen21d3c042020-09-11 00:16:43 -0700937 if (soc)
938 iommu_group_set_name(group->group, soc->name);
Thierry Reding7f4c9172017-10-12 16:19:16 +0200939 list_add_tail(&group->list, &smmu->groups);
940 mutex_unlock(&smmu->lock);
941
942 return group->group;
943}
944
Thierry Reding7f4c9172017-10-12 16:19:16 +0200945static int tegra_smmu_of_xlate(struct device *dev,
946 struct of_phandle_args *args)
947{
Nicolin Chen25938c72020-11-25 02:10:12 -0800948 struct platform_device *iommu_pdev = of_find_device_by_node(args->np);
949 struct tegra_mc *mc = platform_get_drvdata(iommu_pdev);
Thierry Reding7f4c9172017-10-12 16:19:16 +0200950 u32 id = args->args[0];
951
Nicolin Chen25938c72020-11-25 02:10:12 -0800952 /*
953 * Note: we are here releasing the reference of &iommu_pdev->dev, which
954 * is mc->dev. Although some functions in tegra_smmu_ops may keep using
955 * its private data beyond this point, it's still safe to do so because
956 * the SMMU parent device is the same as the MC, so the reference count
957 * isn't strictly necessary.
958 */
959 put_device(&iommu_pdev->dev);
960
961 dev_iommu_priv_set(dev, mc->smmu);
962
Thierry Reding7f4c9172017-10-12 16:19:16 +0200963 return iommu_fwspec_add_ids(dev, &id, 1);
964}
965
Thierry Reding89184652014-04-16 09:24:44 +0200966static const struct iommu_ops tegra_smmu_ops = {
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100967 .domain_alloc = tegra_smmu_domain_alloc,
Joerg Roedelb287ba72020-04-29 15:37:04 +0200968 .probe_device = tegra_smmu_probe_device,
969 .release_device = tegra_smmu_release_device,
Thierry Reding7f4c9172017-10-12 16:19:16 +0200970 .device_group = tegra_smmu_device_group,
Thierry Reding7f4c9172017-10-12 16:19:16 +0200971 .of_xlate = tegra_smmu_of_xlate,
Thierry Reding89184652014-04-16 09:24:44 +0200972 .pgsize_bitmap = SZ_4K,
Lu Baolu9a630a42022-02-16 10:52:49 +0800973 .default_domain_ops = &(const struct iommu_domain_ops) {
974 .attach_dev = tegra_smmu_attach_dev,
975 .detach_dev = tegra_smmu_detach_dev,
976 .map = tegra_smmu_map,
977 .unmap = tegra_smmu_unmap,
978 .iova_to_phys = tegra_smmu_iova_to_phys,
979 .free = tegra_smmu_domain_free,
980 }
Thierry Reding89184652014-04-16 09:24:44 +0200981};
982
983static void tegra_smmu_ahb_enable(void)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200984{
Thierry Reding89184652014-04-16 09:24:44 +0200985 static const struct of_device_id ahb_match[] = {
986 { .compatible = "nvidia,tegra30-ahb", },
987 { }
988 };
989 struct device_node *ahb;
990
991 ahb = of_find_matching_node(NULL, ahb_match);
992 if (ahb) {
993 tegra_ahb_enable_smmu(ahb);
994 of_node_put(ahb);
995 }
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200996}
997
Thierry Redingd1313e72015-01-23 09:49:25 +0100998static int tegra_smmu_swgroups_show(struct seq_file *s, void *data)
999{
1000 struct tegra_smmu *smmu = s->private;
1001 unsigned int i;
1002 u32 value;
1003
1004 seq_printf(s, "swgroup enabled ASID\n");
1005 seq_printf(s, "------------------------\n");
1006
1007 for (i = 0; i < smmu->soc->num_swgroups; i++) {
1008 const struct tegra_smmu_swgroup *group = &smmu->soc->swgroups[i];
1009 const char *status;
1010 unsigned int asid;
1011
1012 value = smmu_readl(smmu, group->reg);
1013
1014 if (value & SMMU_ASID_ENABLE)
1015 status = "yes";
1016 else
1017 status = "no";
1018
1019 asid = value & SMMU_ASID_MASK;
1020
1021 seq_printf(s, "%-9s %-7s %#04x\n", group->name, status,
1022 asid);
1023 }
1024
1025 return 0;
1026}
1027
Yangtao Li062e52a2018-11-22 08:30:47 -05001028DEFINE_SHOW_ATTRIBUTE(tegra_smmu_swgroups);
Thierry Redingd1313e72015-01-23 09:49:25 +01001029
1030static int tegra_smmu_clients_show(struct seq_file *s, void *data)
1031{
1032 struct tegra_smmu *smmu = s->private;
1033 unsigned int i;
1034 u32 value;
1035
1036 seq_printf(s, "client enabled\n");
1037 seq_printf(s, "--------------------\n");
1038
1039 for (i = 0; i < smmu->soc->num_clients; i++) {
1040 const struct tegra_mc_client *client = &smmu->soc->clients[i];
1041 const char *status;
1042
Thierry Reding4f1ac762021-06-02 18:32:51 +02001043 value = smmu_readl(smmu, client->regs.smmu.reg);
Thierry Redingd1313e72015-01-23 09:49:25 +01001044
Thierry Reding4f1ac762021-06-02 18:32:51 +02001045 if (value & BIT(client->regs.smmu.bit))
Thierry Redingd1313e72015-01-23 09:49:25 +01001046 status = "yes";
1047 else
1048 status = "no";
1049
1050 seq_printf(s, "%-12s %s\n", client->name, status);
1051 }
1052
1053 return 0;
1054}
1055
Yangtao Li062e52a2018-11-22 08:30:47 -05001056DEFINE_SHOW_ATTRIBUTE(tegra_smmu_clients);
Thierry Redingd1313e72015-01-23 09:49:25 +01001057
1058static void tegra_smmu_debugfs_init(struct tegra_smmu *smmu)
1059{
1060 smmu->debugfs = debugfs_create_dir("smmu", NULL);
1061 if (!smmu->debugfs)
1062 return;
1063
1064 debugfs_create_file("swgroups", S_IRUGO, smmu->debugfs, smmu,
1065 &tegra_smmu_swgroups_fops);
1066 debugfs_create_file("clients", S_IRUGO, smmu->debugfs, smmu,
1067 &tegra_smmu_clients_fops);
1068}
1069
1070static void tegra_smmu_debugfs_exit(struct tegra_smmu *smmu)
1071{
1072 debugfs_remove_recursive(smmu->debugfs);
1073}
1074
Thierry Reding89184652014-04-16 09:24:44 +02001075struct tegra_smmu *tegra_smmu_probe(struct device *dev,
1076 const struct tegra_smmu_soc *soc,
1077 struct tegra_mc *mc)
1078{
1079 struct tegra_smmu *smmu;
Thierry Reding89184652014-04-16 09:24:44 +02001080 u32 value;
1081 int err;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +02001082
Thierry Reding89184652014-04-16 09:24:44 +02001083 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1084 if (!smmu)
1085 return ERR_PTR(-ENOMEM);
1086
Nicolin Chen765a9d12021-02-18 14:07:02 -08001087 /*
1088 * This is a bit of a hack. Ideally we'd want to simply return this
1089 * value. However the IOMMU registration process will attempt to add
1090 * all devices to the IOMMU when bus_set_iommu() is called. In order
1091 * not to rely on global variables to track the IOMMU instance, we
1092 * set it here so that it can be looked up from the .probe_device()
1093 * callback via the IOMMU device's .drvdata field.
1094 */
1095 mc->smmu = smmu;
1096
Christophe JAILLET89374242021-09-26 15:07:18 +02001097 smmu->asids = devm_bitmap_zalloc(dev, soc->num_asids, GFP_KERNEL);
Thierry Reding89184652014-04-16 09:24:44 +02001098 if (!smmu->asids)
1099 return ERR_PTR(-ENOMEM);
1100
Thierry Reding7f4c9172017-10-12 16:19:16 +02001101 INIT_LIST_HEAD(&smmu->groups);
Thierry Reding89184652014-04-16 09:24:44 +02001102 mutex_init(&smmu->lock);
1103
1104 smmu->regs = mc->regs;
1105 smmu->soc = soc;
1106 smmu->dev = dev;
1107 smmu->mc = mc;
1108
Nicolin Chen82fa58e2020-09-11 00:16:41 -07001109 smmu->pfn_mask =
1110 BIT_MASK(mc->soc->num_address_bits - SMMU_PTE_SHIFT) - 1;
Thierry Reding804cb542015-03-27 11:07:27 +01001111 dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n",
1112 mc->soc->num_address_bits, smmu->pfn_mask);
Nicolin Chend5c152c2020-09-17 04:31:54 -07001113 smmu->tlb_mask = (1 << fls(smmu->soc->num_tlb_lines)) - 1;
Thierry Reding11cec152015-08-06 14:20:31 +02001114 dev_dbg(dev, "TLB lines: %u, mask: %#lx\n", smmu->soc->num_tlb_lines,
1115 smmu->tlb_mask);
Thierry Reding804cb542015-03-27 11:07:27 +01001116
Thierry Reding89184652014-04-16 09:24:44 +02001117 value = SMMU_PTC_CONFIG_ENABLE | SMMU_PTC_CONFIG_INDEX_MAP(0x3f);
1118
1119 if (soc->supports_request_limit)
1120 value |= SMMU_PTC_CONFIG_REQ_LIMIT(8);
1121
1122 smmu_writel(smmu, value, SMMU_PTC_CONFIG);
1123
1124 value = SMMU_TLB_CONFIG_HIT_UNDER_MISS |
Thierry Reding11cec152015-08-06 14:20:31 +02001125 SMMU_TLB_CONFIG_ACTIVE_LINES(smmu);
Thierry Reding89184652014-04-16 09:24:44 +02001126
1127 if (soc->supports_round_robin_arbitration)
1128 value |= SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION;
1129
1130 smmu_writel(smmu, value, SMMU_TLB_CONFIG);
1131
Russell Kingb8fe0382015-07-27 13:29:41 +01001132 smmu_flush_ptc_all(smmu);
Thierry Reding89184652014-04-16 09:24:44 +02001133 smmu_flush_tlb(smmu);
1134 smmu_writel(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG);
1135 smmu_flush(smmu);
1136
1137 tegra_smmu_ahb_enable();
1138
Joerg Roedel0b480e42017-08-09 17:41:52 +02001139 err = iommu_device_sysfs_add(&smmu->iommu, dev, NULL, dev_name(dev));
1140 if (err)
1141 return ERR_PTR(err);
1142
Robin Murphy2d471b22021-04-01 14:56:26 +01001143 err = iommu_device_register(&smmu->iommu, &tegra_smmu_ops, dev);
Nicolin Chen541f29b2020-11-25 02:10:13 -08001144 if (err)
1145 goto remove_sysfs;
Joerg Roedel0b480e42017-08-09 17:41:52 +02001146
Joerg Roedel96302d82017-08-30 15:06:43 +02001147 err = bus_set_iommu(&platform_bus_type, &tegra_smmu_ops);
Nicolin Chen541f29b2020-11-25 02:10:13 -08001148 if (err < 0)
1149 goto unregister;
1150
1151#ifdef CONFIG_PCI
1152 err = bus_set_iommu(&pci_bus_type, &tegra_smmu_ops);
1153 if (err < 0)
1154 goto unset_platform_bus;
1155#endif
Joerg Roedel96302d82017-08-30 15:06:43 +02001156
Thierry Redingd1313e72015-01-23 09:49:25 +01001157 if (IS_ENABLED(CONFIG_DEBUG_FS))
1158 tegra_smmu_debugfs_init(smmu);
1159
Thierry Reding89184652014-04-16 09:24:44 +02001160 return smmu;
Nicolin Chen541f29b2020-11-25 02:10:13 -08001161
1162unset_platform_bus: __maybe_unused;
1163 bus_set_iommu(&platform_bus_type, NULL);
1164unregister:
1165 iommu_device_unregister(&smmu->iommu);
1166remove_sysfs:
1167 iommu_device_sysfs_remove(&smmu->iommu);
1168
1169 return ERR_PTR(err);
Thierry Reding89184652014-04-16 09:24:44 +02001170}
Thierry Redingd1313e72015-01-23 09:49:25 +01001171
1172void tegra_smmu_remove(struct tegra_smmu *smmu)
1173{
Joerg Roedel0b480e42017-08-09 17:41:52 +02001174 iommu_device_unregister(&smmu->iommu);
1175 iommu_device_sysfs_remove(&smmu->iommu);
1176
Thierry Redingd1313e72015-01-23 09:49:25 +01001177 if (IS_ENABLED(CONFIG_DEBUG_FS))
1178 tegra_smmu_debugfs_exit(smmu);
1179}