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Srinivas Kandagatlad15891c2014-02-11 09:59:57 +00001STMicroelectronics SoC DWMAC glue layer controller
2
Giuseppe CAVALLARO53b26b92014-10-14 08:12:56 +02003This file documents differences between the core properties in
4Documentation/devicetree/bindings/net/stmmac.txt
5and what is needed on STi platforms to program the stmmac glue logic.
6
Srinivas Kandagatlad15891c2014-02-11 09:59:57 +00007The device node has following properties.
8
9Required properties:
Alain Volmat3f90faa2023-04-16 21:58:56 +020010 - compatible : "st,stih407-dwmac"
Peter Griffin9b1a6d32015-01-07 15:04:12 +000011 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
12 encompases the glue register, and the offset of the control register.
Giuseppe CAVALLARO53b26b92014-10-14 08:12:56 +020013 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
14 register available on STiH407 SoC.
Giuseppe CAVALLARO53b26b92014-10-14 08:12:56 +020015 - pinctrl-0: pin-control for all the MII mode supported.
Srinivas Kandagatlad15891c2014-02-11 09:59:57 +000016
Giuseppe CAVALLARO53b26b92014-10-14 08:12:56 +020017Optional properties:
18 - resets : phandle pointing to the system reset controller with correct
19 reset line index for ethernet reset.
20 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
21 MAC can generate it.
22 - st,tx-retime-src: This specifies which clk is wired up to the mac for
23 retimeing tx lines. This is totally board dependent and can take one of the
Bjorn Helgaas47aab532023-08-14 16:28:21 -050024 possible values from "txclk", "clk_125" or "clkgen".
Giuseppe CAVALLARO53b26b92014-10-14 08:12:56 +020025 If not passed, the internal clock will be used by default.
26 - sti-ethclk: this is the phy clock.
27 - sti-clkconf: this is an extra sysconfig register, available in new SoCs,
28 to program the clk retiming.
29 - st,gmac_en: to enable the GMAC, this only is present in some SoCs; e.g.
30 STiH407.
Srinivas Kandagatlad15891c2014-02-11 09:59:57 +000031
32Example:
33
Giuseppe CAVALLARO53b26b92014-10-14 08:12:56 +020034ethernet0: dwmac@9630000 {
35 device_type = "network";
Giuseppe CAVALLARO53b26b92014-10-14 08:12:56 +020036 compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
Peter Griffin9b1a6d32015-01-07 15:04:12 +000037 reg = <0x9630000 0x8000>;
38 reg-names = "stmmaceth";
Srinivas Kandagatlad15891c2014-02-11 09:59:57 +000039
Peter Griffin9b1a6d32015-01-07 15:04:12 +000040 st,syscon = <&syscfg_sbc_reg 0x80>;
Giuseppe CAVALLARO53b26b92014-10-14 08:12:56 +020041 st,gmac_en;
42 resets = <&softreset STIH407_ETH1_SOFTRESET>;
43 reset-names = "stmmaceth";
Srinivas Kandagatlad15891c2014-02-11 09:59:57 +000044
Giuseppe CAVALLARO53b26b92014-10-14 08:12:56 +020045 interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
46 <GIC_SPI 99 IRQ_TYPE_NONE>,
47 <GIC_SPI 100 IRQ_TYPE_NONE>;
48 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
49
50 snps,pbl = <32>;
Srinivas Kandagatlad15891c2014-02-11 09:59:57 +000051 snps,mixed-burst;
52
Giuseppe CAVALLARO53b26b92014-10-14 08:12:56 +020053 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_rgmii1>;
55
56 clock-names = "stmmaceth", "sti-ethclk";
57 clocks = <&CLK_S_C0_FLEXGEN CLK_EXT2F_A9>,
58 <&CLK_S_C0_FLEXGEN CLK_ETH_PHY>;
Srinivas Kandagatlad15891c2014-02-11 09:59:57 +000059};