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Thomas Gleixner2874c5f2019-05-27 08:55:01 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Vladimir Barinov3d9edf02007-07-10 13:03:43 +01002/*
3 * TI DaVinci GPIO Support
4 *
David Brownelldce11152008-09-07 23:41:04 -07005 * Copyright (c) 2006-2007 David Brownell
Vladimir Barinov3d9edf02007-07-10 13:03:43 +01006 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
Vladimir Barinov3d9edf02007-07-10 13:03:43 +01007 */
Andrew F. Davis79b73ff2018-08-31 14:13:26 -05008
Linus Walleij7220c432018-01-14 02:05:38 +01009#include <linux/gpio/driver.h>
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010010#include <linux/errno.h>
11#include <linux/kernel.h>
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010012#include <linux/clk.h>
13#include <linux/err.h>
14#include <linux/io.h>
KV Sujith118150f2013-08-18 10:48:58 +053015#include <linux/irq.h>
Lad, Prabhakar9211ff32013-11-21 23:45:27 +053016#include <linux/irqdomain.h>
KV Sujithc7708442013-11-21 23:45:29 +053017#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_device.h>
David Lechner3c87d7c2018-01-21 17:09:40 -060020#include <linux/pinctrl/consumer.h>
KV Sujith118150f2013-08-18 10:48:58 +053021#include <linux/platform_device.h>
22#include <linux/platform_data/gpio-davinci.h>
Grygorii Strashko0d978eb2013-11-26 21:40:09 +020023#include <linux/irqchip/chained_irq.h>
Andrew F. Davis79b73ff2018-08-31 14:13:26 -050024#include <linux/spinlock.h>
25
26#include <asm-generic/gpio.h>
27
28#define MAX_REGS_BANKS 5
29#define MAX_INT_PER_BANK 32
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010030
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040031struct davinci_gpio_regs {
32 u32 dir;
33 u32 out_data;
34 u32 set_data;
35 u32 clr_data;
36 u32 in_data;
37 u32 set_rising;
38 u32 clr_rising;
39 u32 set_falling;
40 u32 clr_falling;
41 u32 intstat;
42};
43
Grygorii Strashko0c6feb02014-02-13 17:58:45 +020044typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
45
Philip Avinash131a10a2013-08-18 10:48:57 +053046#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
47
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040048static void __iomem *gpio_base;
Keerthy8f7cf8c2017-01-17 21:49:11 +053049static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010050
Andrew F. Davis79b73ff2018-08-31 14:13:26 -050051struct davinci_gpio_irq_data {
52 void __iomem *regs;
53 struct davinci_gpio_controller *chip;
54 int bank_num;
55};
56
57struct davinci_gpio_controller {
58 struct gpio_chip chip;
59 struct irq_domain *irq_domain;
60 /* Serialize access to GPIO registers */
61 spinlock_t lock;
62 void __iomem *regs[MAX_REGS_BANKS];
63 int gpio_unbanked;
64 int irqs[MAX_INT_PER_BANK];
65};
66
67static inline u32 __gpio_mask(unsigned gpio)
68{
69 return 1 << (gpio % 32);
70}
71
Thomas Gleixner1765d672015-07-13 01:18:56 +020072static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
Kevin Hilman21ce8732010-02-25 16:49:56 -080073{
Cyril Chemparathy99e9e522010-05-01 18:37:52 -040074 struct davinci_gpio_regs __iomem *g;
Kevin Hilman21ce8732010-02-25 16:49:56 -080075
Thomas Gleixner1765d672015-07-13 01:18:56 +020076 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
Kevin Hilman21ce8732010-02-25 16:49:56 -080077
78 return g;
79}
80
Keerthyeb3744a2018-06-13 09:10:37 +053081static int davinci_gpio_irq_setup(struct platform_device *pdev);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010082
83/*--------------------------------------------------------------------------*/
84
Cyril Chemparathy5b3a05c2010-05-01 18:38:27 -040085/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040086static inline int __davinci_direction(struct gpio_chip *chip,
87 unsigned offset, bool out, int value)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010088{
Linus Walleij72a1ca22015-12-04 16:25:04 +010089 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
Keerthyb5cf3fd2017-01-13 09:50:12 +053090 struct davinci_gpio_regs __iomem *g;
Cyril Chemparathyb27b6d02010-05-01 18:37:55 -040091 unsigned long flags;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010092 u32 temp;
Keerthyb5cf3fd2017-01-13 09:50:12 +053093 int bank = offset / 32;
94 u32 mask = __gpio_mask(offset);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010095
Keerthyb5cf3fd2017-01-13 09:50:12 +053096 g = d->regs[bank];
Cyril Chemparathyb27b6d02010-05-01 18:37:55 -040097 spin_lock_irqsave(&d->lock, flags);
Lad, Prabhakar388291c2013-12-11 23:22:07 +053098 temp = readl_relaxed(&g->dir);
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040099 if (out) {
100 temp &= ~mask;
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530101 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
Cyril Chemparathyba4a9842010-05-01 18:37:51 -0400102 } else {
103 temp |= mask;
104 }
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530105 writel_relaxed(temp, &g->dir);
Cyril Chemparathyb27b6d02010-05-01 18:37:55 -0400106 spin_unlock_irqrestore(&d->lock, flags);
David Brownelldce11152008-09-07 23:41:04 -0700107
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100108 return 0;
109}
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100110
Cyril Chemparathyba4a9842010-05-01 18:37:51 -0400111static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
112{
113 return __davinci_direction(chip, offset, false, 0);
114}
115
116static int
117davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
118{
119 return __davinci_direction(chip, offset, true, value);
120}
121
David Brownelldce11152008-09-07 23:41:04 -0700122/*
123 * Read the pin's value (works even if it's set up as output);
124 * returns zero/nonzero.
125 *
126 * Note that changes are synched to the GPIO clock, so reading values back
127 * right after you've set them may give old values.
128 */
129static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100130{
Linus Walleij72a1ca22015-12-04 16:25:04 +0100131 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
Keerthyb5cf3fd2017-01-13 09:50:12 +0530132 struct davinci_gpio_regs __iomem *g;
133 int bank = offset / 32;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100134
Keerthyb5cf3fd2017-01-13 09:50:12 +0530135 g = d->regs[bank];
136
137 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
David Brownelldce11152008-09-07 23:41:04 -0700138}
139
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100140/*
David Brownelldce11152008-09-07 23:41:04 -0700141 * Assuming the pin is muxed as a gpio output, set its output value.
142 */
143static void
144davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
145{
Linus Walleij72a1ca22015-12-04 16:25:04 +0100146 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
Keerthyb5cf3fd2017-01-13 09:50:12 +0530147 struct davinci_gpio_regs __iomem *g;
148 int bank = offset / 32;
David Brownelldce11152008-09-07 23:41:04 -0700149
Keerthyb5cf3fd2017-01-13 09:50:12 +0530150 g = d->regs[bank];
151
152 writel_relaxed(__gpio_mask(offset),
153 value ? &g->set_data : &g->clr_data);
David Brownelldce11152008-09-07 23:41:04 -0700154}
155
KV Sujithc7708442013-11-21 23:45:29 +0530156static struct davinci_gpio_platform_data *
157davinci_gpio_get_pdata(struct platform_device *pdev)
158{
159 struct device_node *dn = pdev->dev.of_node;
160 struct davinci_gpio_platform_data *pdata;
161 int ret;
162 u32 val;
163
164 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
Nizam Haiderab128af2015-11-23 20:53:18 +0530165 return dev_get_platdata(&pdev->dev);
KV Sujithc7708442013-11-21 23:45:29 +0530166
167 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
168 if (!pdata)
169 return NULL;
170
171 ret = of_property_read_u32(dn, "ti,ngpio", &val);
172 if (ret)
173 goto of_err;
174
175 pdata->ngpio = val;
176
177 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
178 if (ret)
179 goto of_err;
180
181 pdata->gpio_unbanked = val;
182
183 return pdata;
184
185of_err:
186 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
187 return NULL;
188}
189
KV Sujith118150f2013-08-18 10:48:58 +0530190static int davinci_gpio_probe(struct platform_device *pdev)
David Brownelldce11152008-09-07 23:41:04 -0700191{
Andrew F. Davisc809e372018-08-31 14:13:24 -0500192 int bank, i, ret = 0;
Keerthyeb3744a2018-06-13 09:10:37 +0530193 unsigned int ngpio, nbank, nirq;
KV Sujith118150f2013-08-18 10:48:58 +0530194 struct davinci_gpio_controller *chips;
195 struct davinci_gpio_platform_data *pdata;
KV Sujith118150f2013-08-18 10:48:58 +0530196 struct device *dev = &pdev->dev;
David Brownelldce11152008-09-07 23:41:04 -0700197
KV Sujithc7708442013-11-21 23:45:29 +0530198 pdata = davinci_gpio_get_pdata(pdev);
KV Sujith118150f2013-08-18 10:48:58 +0530199 if (!pdata) {
200 dev_err(dev, "No platform data found\n");
201 return -EINVAL;
202 }
Cyril Chemparathy686b6342010-05-01 18:37:54 -0400203
KV Sujithc7708442013-11-21 23:45:29 +0530204 dev->platform_data = pdata;
205
Mark A. Greera9949552009-04-15 12:40:35 -0700206 /*
207 * The gpio banks conceptually expose a segmented bitmap,
David Brownell474dad52008-12-07 11:46:23 -0800208 * and "ngpio" is one more than the largest zero-based
209 * bit index that's valid.
210 */
KV Sujith118150f2013-08-18 10:48:58 +0530211 ngpio = pdata->ngpio;
Mark A. Greera9949552009-04-15 12:40:35 -0700212 if (ngpio == 0) {
KV Sujith118150f2013-08-18 10:48:58 +0530213 dev_err(dev, "How many GPIOs?\n");
David Brownell474dad52008-12-07 11:46:23 -0800214 return -EINVAL;
215 }
216
Grygorii Strashkoc21d5002013-11-21 17:34:35 +0200217 if (WARN_ON(ARCH_NR_GPIOS < ngpio))
218 ngpio = ARCH_NR_GPIOS;
David Brownell474dad52008-12-07 11:46:23 -0800219
Keerthyeb3744a2018-06-13 09:10:37 +0530220 /*
221 * If there are unbanked interrupts then the number of
222 * interrupts is equal to number of gpios else all are banked so
223 * number of interrupts is equal to number of banks(each with 16 gpios)
224 */
225 if (pdata->gpio_unbanked)
226 nirq = pdata->gpio_unbanked;
227 else
228 nirq = DIV_ROUND_UP(ngpio, 16);
229
Andrew F. Davisc809e372018-08-31 14:13:24 -0500230 chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL);
Jingoo Han9ea9363c2014-04-29 17:33:26 +0900231 if (!chips)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -0400232 return -ENOMEM;
KV Sujith118150f2013-08-18 10:48:58 +0530233
Bartosz Golaszewskifa7569c2019-02-20 12:12:40 +0100234 gpio_base = devm_platform_ioremap_resource(pdev, 0);
KV Sujith118150f2013-08-18 10:48:58 +0530235 if (IS_ERR(gpio_base))
236 return PTR_ERR(gpio_base);
Cyril Chemparathyb8d44292010-05-07 17:06:32 -0400237
Keerthyeb3744a2018-06-13 09:10:37 +0530238 for (i = 0; i < nirq; i++) {
239 chips->irqs[i] = platform_get_irq(pdev, i);
Krzysztof Kozlowski33b78b52020-08-27 22:08:23 +0200240 if (chips->irqs[i] < 0)
241 return dev_err_probe(dev, chips->irqs[i], "IRQ not populated\n");
Keerthyc1d013a2018-06-13 09:10:36 +0530242 }
243
Andrew F. Davis587f7a62018-08-31 14:13:23 -0500244 chips->chip.label = dev_name(dev);
David Brownelldce11152008-09-07 23:41:04 -0700245
Keerthyb5cf3fd2017-01-13 09:50:12 +0530246 chips->chip.direction_input = davinci_direction_in;
247 chips->chip.get = davinci_gpio_get;
248 chips->chip.direction_output = davinci_direction_out;
249 chips->chip.set = davinci_gpio_set;
David Brownelldce11152008-09-07 23:41:04 -0700250
Keerthyb5cf3fd2017-01-13 09:50:12 +0530251 chips->chip.ngpio = ngpio;
Bartosz Golaszewski786a9ab2018-11-21 10:35:17 +0100252 chips->chip.base = pdata->no_auto_base ? pdata->base : -1;
David Brownelldce11152008-09-07 23:41:04 -0700253
KV Sujithc7708442013-11-21 23:45:29 +0530254#ifdef CONFIG_OF_GPIO
Keerthyb5cf3fd2017-01-13 09:50:12 +0530255 chips->chip.of_gpio_n_cells = 2;
Keerthyb5cf3fd2017-01-13 09:50:12 +0530256 chips->chip.parent = dev;
257 chips->chip.of_node = dev->of_node;
Thierry Redingf0254b52020-04-01 22:05:26 +0200258 chips->chip.request = gpiochip_generic_request;
259 chips->chip.free = gpiochip_generic_free;
KV Sujithc7708442013-11-21 23:45:29 +0530260#endif
Keerthyb5cf3fd2017-01-13 09:50:12 +0530261 spin_lock_init(&chips->lock);
Cyril Chemparathyb27b6d02010-05-01 18:37:55 -0400262
Andrew F. Davisc809e372018-08-31 14:13:24 -0500263 nbank = DIV_ROUND_UP(ngpio, 32);
264 for (bank = 0; bank < nbank; bank++)
Keerthyb5cf3fd2017-01-13 09:50:12 +0530265 chips->regs[bank] = gpio_base + offset_array[bank];
David Brownelldce11152008-09-07 23:41:04 -0700266
Keerthy8327e1b2017-07-20 15:12:16 +0530267 ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
268 if (ret)
Andrew F. Davis587f7a62018-08-31 14:13:23 -0500269 return ret;
Keerthy8327e1b2017-07-20 15:12:16 +0530270
KV Sujith118150f2013-08-18 10:48:58 +0530271 platform_set_drvdata(pdev, chips);
Keerthyeb3744a2018-06-13 09:10:37 +0530272 ret = davinci_gpio_irq_setup(pdev);
Keerthy5e7a0ce2017-07-20 15:12:17 +0530273 if (ret)
Andrew F. Davis587f7a62018-08-31 14:13:23 -0500274 return ret;
Keerthy5e7a0ce2017-07-20 15:12:17 +0530275
David Brownelldce11152008-09-07 23:41:04 -0700276 return 0;
277}
David Brownelldce11152008-09-07 23:41:04 -0700278
279/*--------------------------------------------------------------------------*/
280/*
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100281 * We expect irqs will normally be set up as input pins, but they can also be
282 * used as output pins ... which is convenient for testing.
283 *
David Brownell474dad52008-12-07 11:46:23 -0800284 * NOTE: The first few GPIOs also have direct INTC hookups in addition
David Brownell7a360712009-06-25 17:01:31 -0700285 * to their GPIOBNK0 irq, with a bit less overhead.
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100286 *
David Brownell474dad52008-12-07 11:46:23 -0800287 * All those INTC hookups (direct, plus several IRQ banks) can also
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100288 * serve as EDMA event triggers.
289 */
290
Lennert Buytenhek23265442010-11-29 10:27:27 +0100291static void gpio_irq_disable(struct irq_data *d)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100292{
Thomas Gleixner1765d672015-07-13 01:18:56 +0200293 struct davinci_gpio_regs __iomem *g = irq2regs(d);
Keerthy36c05512019-06-05 13:32:57 +0530294 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100295
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530296 writel_relaxed(mask, &g->clr_falling);
297 writel_relaxed(mask, &g->clr_rising);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100298}
299
Lennert Buytenhek23265442010-11-29 10:27:27 +0100300static void gpio_irq_enable(struct irq_data *d)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100301{
Thomas Gleixner1765d672015-07-13 01:18:56 +0200302 struct davinci_gpio_regs __iomem *g = irq2regs(d);
Keerthy36c05512019-06-05 13:32:57 +0530303 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
Thomas Gleixner5093aec2011-03-24 12:47:04 +0100304 unsigned status = irqd_get_trigger_type(d);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100305
David Brownelldf4aab42009-05-04 13:14:27 -0700306 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
307 if (!status)
308 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
309
310 if (status & IRQ_TYPE_EDGE_FALLING)
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530311 writel_relaxed(mask, &g->set_falling);
David Brownelldf4aab42009-05-04 13:14:27 -0700312 if (status & IRQ_TYPE_EDGE_RISING)
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530313 writel_relaxed(mask, &g->set_rising);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100314}
315
Lennert Buytenhek23265442010-11-29 10:27:27 +0100316static int gpio_irq_type(struct irq_data *d, unsigned trigger)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100317{
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100318 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
319 return -EINVAL;
320
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100321 return 0;
322}
323
324static struct irq_chip gpio_irqchip = {
325 .name = "GPIO",
Lennert Buytenhek23265442010-11-29 10:27:27 +0100326 .irq_enable = gpio_irq_enable,
327 .irq_disable = gpio_irq_disable,
328 .irq_set_type = gpio_irq_type,
Thomas Gleixner5093aec2011-03-24 12:47:04 +0100329 .flags = IRQCHIP_SET_TYPE_MASKED,
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100330};
331
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200332static void gpio_irq_handler(struct irq_desc *desc)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100333{
Thomas Gleixner74164012011-06-06 11:51:43 +0200334 struct davinci_gpio_regs __iomem *g;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100335 u32 mask = 0xffff;
Keerthyb5cf3fd2017-01-13 09:50:12 +0530336 int bank_num;
Ido Yarivf299bb92011-07-12 00:03:11 +0300337 struct davinci_gpio_controller *d;
Keerthyb5cf3fd2017-01-13 09:50:12 +0530338 struct davinci_gpio_irq_data *irqdata;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100339
Keerthyb5cf3fd2017-01-13 09:50:12 +0530340 irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
341 bank_num = irqdata->bank_num;
342 g = irqdata->regs;
343 d = irqdata->chip;
Thomas Gleixner74164012011-06-06 11:51:43 +0200344
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100345 /* we only care about one bank */
Keerthyb5cf3fd2017-01-13 09:50:12 +0530346 if ((bank_num % 2) == 1)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100347 mask <<= 16;
348
349 /* temporarily mask (level sensitive) parent IRQ */
Grygorii Strashko0d978eb2013-11-26 21:40:09 +0200350 chained_irq_enter(irq_desc_get_chip(desc), desc);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100351 while (1) {
352 u32 status;
Lad, Prabhakar9211ff32013-11-21 23:45:27 +0530353 int bit;
Keerthyb5cf3fd2017-01-13 09:50:12 +0530354 irq_hw_number_t hw_irq;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100355
356 /* ack any irqs */
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530357 status = readl_relaxed(&g->intstat) & mask;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100358 if (!status)
359 break;
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530360 writel_relaxed(status, &g->intstat);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100361
362 /* now demux them to the right lowlevel handler */
Ido Yarivf299bb92011-07-12 00:03:11 +0300363
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100364 while (status) {
Lad, Prabhakar9211ff32013-11-21 23:45:27 +0530365 bit = __ffs(status);
366 status &= ~BIT(bit);
Keerthyb5cf3fd2017-01-13 09:50:12 +0530367 /* Max number of gpios per controller is 144 so
368 * hw_irq will be in [0..143]
369 */
370 hw_irq = (bank_num / 2) * 32 + bit;
371
Lad, Prabhakar9211ff32013-11-21 23:45:27 +0530372 generic_handle_irq(
Keerthyb5cf3fd2017-01-13 09:50:12 +0530373 irq_find_mapping(d->irq_domain, hw_irq));
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100374 }
375 }
Grygorii Strashko0d978eb2013-11-26 21:40:09 +0200376 chained_irq_exit(irq_desc_get_chip(desc), desc);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100377 /* now it may re-trigger */
378}
379
David Brownell7a360712009-06-25 17:01:31 -0700380static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
381{
Linus Walleij72a1ca22015-12-04 16:25:04 +0100382 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
David Brownell7a360712009-06-25 17:01:31 -0700383
Grygorii Strashko6075a8b2013-12-18 12:07:51 +0200384 if (d->irq_domain)
Keerthyb5cf3fd2017-01-13 09:50:12 +0530385 return irq_create_mapping(d->irq_domain, offset);
Grygorii Strashko6075a8b2013-12-18 12:07:51 +0200386 else
387 return -ENXIO;
David Brownell7a360712009-06-25 17:01:31 -0700388}
389
390static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
391{
Linus Walleij72a1ca22015-12-04 16:25:04 +0100392 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
David Brownell7a360712009-06-25 17:01:31 -0700393
Philip Avinash131a10a2013-08-18 10:48:57 +0530394 /*
395 * NOTE: we assume for now that only irqs in the first gpio_chip
David Brownell7a360712009-06-25 17:01:31 -0700396 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
397 */
Lad, Prabhakar34af1ab2013-11-08 12:15:55 +0530398 if (offset < d->gpio_unbanked)
Keerthyeb3744a2018-06-13 09:10:37 +0530399 return d->irqs[offset];
David Brownell7a360712009-06-25 17:01:31 -0700400 else
401 return -ENODEV;
402}
403
Sekhar Noriab2dde92012-03-11 18:16:11 +0530404static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
David Brownell7a360712009-06-25 17:01:31 -0700405{
Sekhar Noriab2dde92012-03-11 18:16:11 +0530406 struct davinci_gpio_controller *d;
407 struct davinci_gpio_regs __iomem *g;
Keerthyeb3744a2018-06-13 09:10:37 +0530408 u32 mask, i;
Sekhar Noriab2dde92012-03-11 18:16:11 +0530409
Jiang Liuc16edb82015-06-01 16:05:19 +0800410 d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
Keerthy7f8e2a852017-11-10 16:43:17 +0530411 g = (struct davinci_gpio_regs __iomem *)d->regs[0];
Keerthyeb3744a2018-06-13 09:10:37 +0530412 for (i = 0; i < MAX_INT_PER_BANK; i++)
413 if (data->irq == d->irqs[i])
414 break;
415
416 if (i == MAX_INT_PER_BANK)
417 return -EINVAL;
418
419 mask = __gpio_mask(i);
David Brownell7a360712009-06-25 17:01:31 -0700420
421 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
422 return -EINVAL;
423
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530424 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
David Brownell7a360712009-06-25 17:01:31 -0700425 ? &g->set_falling : &g->clr_falling);
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530426 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
David Brownell7a360712009-06-25 17:01:31 -0700427 ? &g->set_rising : &g->clr_rising);
428
429 return 0;
430}
431
Lad, Prabhakar9211ff32013-11-21 23:45:27 +0530432static int
433davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
434 irq_hw_number_t hw)
435{
Keerthy8f7cf8c2017-01-17 21:49:11 +0530436 struct davinci_gpio_controller *chips =
437 (struct davinci_gpio_controller *)d->host_data;
Keerthyb5cf3fd2017-01-13 09:50:12 +0530438 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32];
Lad, Prabhakar9211ff32013-11-21 23:45:27 +0530439
440 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
441 "davinci_gpio");
442 irq_set_irq_type(irq, IRQ_TYPE_NONE);
443 irq_set_chip_data(irq, (__force void *)g);
Keerthy36c05512019-06-05 13:32:57 +0530444 irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw));
Lad, Prabhakar9211ff32013-11-21 23:45:27 +0530445
446 return 0;
447}
448
449static const struct irq_domain_ops davinci_gpio_irq_ops = {
450 .map = davinci_gpio_irq_map,
451 .xlate = irq_domain_xlate_onetwocell,
452};
453
Grygorii Strashko0c6feb02014-02-13 17:58:45 +0200454static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
455{
456 static struct irq_chip_type gpio_unbanked;
457
Geliang Tangccdbddf2015-12-30 22:16:38 +0800458 gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
Grygorii Strashko0c6feb02014-02-13 17:58:45 +0200459
460 return &gpio_unbanked.chip;
461};
462
463static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
464{
465 static struct irq_chip gpio_unbanked;
466
467 gpio_unbanked = *irq_get_chip(irq);
468 return &gpio_unbanked;
469};
470
471static const struct of_device_id davinci_gpio_ids[];
472
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100473/*
David Brownell474dad52008-12-07 11:46:23 -0800474 * NOTE: for suspend/resume, probably best to make a platform_device with
475 * suspend_late/resume_resume calls hooking into results of the set_wake()
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100476 * calls ... so if no gpios are wakeup events the clock can be disabled,
477 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
David Brownell474dad52008-12-07 11:46:23 -0800478 * (dm6446) can be set appropriately for GPIOV33 pins.
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100479 */
480
Keerthyeb3744a2018-06-13 09:10:37 +0530481static int davinci_gpio_irq_setup(struct platform_device *pdev)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100482{
Alexander Shiyan58c0f5a2014-02-15 17:12:05 +0400483 unsigned gpio, bank;
484 int irq;
Arvind Yadav6dc00482017-05-23 14:48:57 +0530485 int ret;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100486 struct clk *clk;
David Brownell474dad52008-12-07 11:46:23 -0800487 u32 binten = 0;
Keerthyc1d013a2018-06-13 09:10:36 +0530488 unsigned ngpio;
KV Sujith118150f2013-08-18 10:48:58 +0530489 struct device *dev = &pdev->dev;
KV Sujith118150f2013-08-18 10:48:58 +0530490 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
491 struct davinci_gpio_platform_data *pdata = dev->platform_data;
492 struct davinci_gpio_regs __iomem *g;
Grygorii Strashko6075a8b2013-12-18 12:07:51 +0200493 struct irq_domain *irq_domain = NULL;
Grygorii Strashko0c6feb02014-02-13 17:58:45 +0200494 const struct of_device_id *match;
495 struct irq_chip *irq_chip;
Keerthyb5cf3fd2017-01-13 09:50:12 +0530496 struct davinci_gpio_irq_data *irqdata;
Grygorii Strashko0c6feb02014-02-13 17:58:45 +0200497 gpio_get_irq_chip_cb_t gpio_get_irq_chip;
498
499 /*
500 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
501 */
502 gpio_get_irq_chip = davinci_gpio_get_irq_chip;
503 match = of_match_device(of_match_ptr(davinci_gpio_ids),
504 dev);
505 if (match)
506 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
David Brownell474dad52008-12-07 11:46:23 -0800507
KV Sujith118150f2013-08-18 10:48:58 +0530508 ngpio = pdata->ngpio;
KV Sujith118150f2013-08-18 10:48:58 +0530509
510 clk = devm_clk_get(dev, "gpio");
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100511 if (IS_ERR(clk)) {
Keerthy1a9ef902017-07-20 15:12:18 +0530512 dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
David Brownell474dad52008-12-07 11:46:23 -0800513 return PTR_ERR(clk);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100514 }
Keerthyeb3744a2018-06-13 09:10:37 +0530515
Arvind Yadav6dc00482017-05-23 14:48:57 +0530516 ret = clk_prepare_enable(clk);
517 if (ret)
518 return ret;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100519
Grygorii Strashko6075a8b2013-12-18 12:07:51 +0200520 if (!pdata->gpio_unbanked) {
Bartosz Golaszewskia1a3c2d52017-03-04 17:23:36 +0100521 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
Grygorii Strashko6075a8b2013-12-18 12:07:51 +0200522 if (irq < 0) {
523 dev_err(dev, "Couldn't allocate IRQ numbers\n");
Arvind Yadav6dc00482017-05-23 14:48:57 +0530524 clk_disable_unprepare(clk);
Grygorii Strashko6075a8b2013-12-18 12:07:51 +0200525 return irq;
526 }
Lad, Prabhakar9211ff32013-11-21 23:45:27 +0530527
Keerthy310a7e62016-01-28 19:08:50 +0530528 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
Grygorii Strashko6075a8b2013-12-18 12:07:51 +0200529 &davinci_gpio_irq_ops,
530 chips);
531 if (!irq_domain) {
532 dev_err(dev, "Couldn't register an IRQ domain\n");
Arvind Yadav6dc00482017-05-23 14:48:57 +0530533 clk_disable_unprepare(clk);
Grygorii Strashko6075a8b2013-12-18 12:07:51 +0200534 return -ENODEV;
535 }
Lad, Prabhakar9211ff32013-11-21 23:45:27 +0530536 }
537
Philip Avinash131a10a2013-08-18 10:48:57 +0530538 /*
539 * Arrange gpio_to_irq() support, handling either direct IRQs or
David Brownell7a360712009-06-25 17:01:31 -0700540 * banked IRQs. Having GPIOs in the first GPIO bank use direct
541 * IRQs, while the others use banked IRQs, would need some setup
542 * tweaks to recognize hardware which can do that.
543 */
Keerthyb5cf3fd2017-01-13 09:50:12 +0530544 chips->chip.to_irq = gpio_to_irq_banked;
545 chips->irq_domain = irq_domain;
David Brownell7a360712009-06-25 17:01:31 -0700546
547 /*
548 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
549 * controller only handling trigger modes. We currently assume no
550 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
551 */
KV Sujith118150f2013-08-18 10:48:58 +0530552 if (pdata->gpio_unbanked) {
David Brownell7a360712009-06-25 17:01:31 -0700553 /* pass "bank 0" GPIO IRQs to AINTC */
Keerthyb5cf3fd2017-01-13 09:50:12 +0530554 chips->chip.to_irq = gpio_to_irq_unbanked;
Keerthyb5cf3fd2017-01-13 09:50:12 +0530555 chips->gpio_unbanked = pdata->gpio_unbanked;
Vitaly Andrianov3685bbc2015-07-02 14:31:30 -0400556 binten = GENMASK(pdata->gpio_unbanked / 16, 0);
David Brownell7a360712009-06-25 17:01:31 -0700557
558 /* AINTC handles mask/unmask; GPIO handles triggering */
Keerthyeb3744a2018-06-13 09:10:37 +0530559 irq = chips->irqs[0];
Grygorii Strashko0c6feb02014-02-13 17:58:45 +0200560 irq_chip = gpio_get_irq_chip(irq);
561 irq_chip->name = "GPIO-AINTC";
562 irq_chip->irq_set_type = gpio_irq_type_unbanked;
David Brownell7a360712009-06-25 17:01:31 -0700563
564 /* default trigger: both edges */
Keerthyb5cf3fd2017-01-13 09:50:12 +0530565 g = chips->regs[0];
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530566 writel_relaxed(~0, &g->set_falling);
567 writel_relaxed(~0, &g->set_rising);
David Brownell7a360712009-06-25 17:01:31 -0700568
569 /* set the direct IRQs up to use that irqchip */
Keerthyeb3744a2018-06-13 09:10:37 +0530570 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) {
571 irq_set_chip(chips->irqs[gpio], irq_chip);
572 irq_set_handler_data(chips->irqs[gpio], chips);
573 irq_set_status_flags(chips->irqs[gpio],
574 IRQ_TYPE_EDGE_BOTH);
David Brownell7a360712009-06-25 17:01:31 -0700575 }
576
577 goto done;
578 }
579
580 /*
581 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
582 * then chain through our own handler.
583 */
Keerthyeb3744a2018-06-13 09:10:37 +0530584 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) {
Keerthy8f7cf8c2017-01-17 21:49:11 +0530585 /* disabled by default, enabled only as needed
586 * There are register sets for 32 GPIOs. 2 banks of 16
587 * GPIOs are covered by each set of registers hence divide by 2
588 */
Keerthyb5cf3fd2017-01-13 09:50:12 +0530589 g = chips->regs[bank / 2];
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530590 writel_relaxed(~0, &g->clr_falling);
591 writel_relaxed(~0, &g->clr_rising);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100592
Ido Yarivf299bb92011-07-12 00:03:11 +0300593 /*
594 * Each chip handles 32 gpios, and each irq bank consists of 16
595 * gpio irqs. Pass the irq bank's corresponding controller to
596 * the chained irq handler.
597 */
Keerthyb5cf3fd2017-01-13 09:50:12 +0530598 irqdata = devm_kzalloc(&pdev->dev,
599 sizeof(struct
600 davinci_gpio_irq_data),
601 GFP_KERNEL);
Arvind Yadav6dc00482017-05-23 14:48:57 +0530602 if (!irqdata) {
603 clk_disable_unprepare(clk);
Keerthyb5cf3fd2017-01-13 09:50:12 +0530604 return -ENOMEM;
Arvind Yadav6dc00482017-05-23 14:48:57 +0530605 }
Keerthyb5cf3fd2017-01-13 09:50:12 +0530606
607 irqdata->regs = g;
608 irqdata->bank_num = bank;
609 irqdata->chip = chips;
610
Keerthyeb3744a2018-06-13 09:10:37 +0530611 irq_set_chained_handler_and_data(chips->irqs[bank],
612 gpio_irq_handler, irqdata);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100613
David Brownell474dad52008-12-07 11:46:23 -0800614 binten |= BIT(bank);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100615 }
616
David Brownell7a360712009-06-25 17:01:31 -0700617done:
Philip Avinash131a10a2013-08-18 10:48:57 +0530618 /*
619 * BINTEN -- per-bank interrupt enable. genirq would also let these
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100620 * bits be set/cleared dynamically.
621 */
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530622 writel_relaxed(binten, gpio_base + BINTEN);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100623
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100624 return 0;
625}
KV Sujith118150f2013-08-18 10:48:58 +0530626
KV Sujithc7708442013-11-21 23:45:29 +0530627static const struct of_device_id davinci_gpio_ids[] = {
Grygorii Strashko0c6feb02014-02-13 17:58:45 +0200628 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
Keerthy6a4d8b62019-06-05 13:32:58 +0530629 { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
Grygorii Strashko0c6feb02014-02-13 17:58:45 +0200630 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
KV Sujithc7708442013-11-21 23:45:29 +0530631 { /* sentinel */ },
632};
633MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
KV Sujithc7708442013-11-21 23:45:29 +0530634
KV Sujith118150f2013-08-18 10:48:58 +0530635static struct platform_driver davinci_gpio_driver = {
636 .probe = davinci_gpio_probe,
637 .driver = {
KV Sujithc7708442013-11-21 23:45:29 +0530638 .name = "davinci_gpio",
KV Sujithc7708442013-11-21 23:45:29 +0530639 .of_match_table = of_match_ptr(davinci_gpio_ids),
KV Sujith118150f2013-08-18 10:48:58 +0530640 },
641};
642
643/**
644 * GPIO driver registration needs to be done before machine_init functions
645 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
646 */
647static int __init davinci_gpio_drv_reg(void)
648{
649 return platform_driver_register(&davinci_gpio_driver);
650}
651postcore_initcall(davinci_gpio_drv_reg);