blob: 8555c779870698dc43d8b80353f3082b218d9308 [file] [log] [blame]
Thomas Gleixnerc942fdd2019-05-27 08:55:06 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Alexander Bersenevb4e3e592014-06-08 15:08:10 -03002/*
3 * Driver for Allwinner sunXi IR controller
4 *
5 * Copyright (C) 2014 Alexsey Shestacov <wingrime@linux-sunxi.org>
6 * Copyright (C) 2014 Alexander Bersenev <bay@hackerdom.ru>
7 *
8 * Based on sun5i-ir.c:
9 * Copyright (C) 2007-2012 Daniel Wang
10 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
Alexander Bersenevb4e3e592014-06-08 15:08:10 -030011 */
12
13#include <linux/clk.h>
14#include <linux/interrupt.h>
15#include <linux/module.h>
16#include <linux/of_platform.h>
Hans de Goede44f8af62014-11-20 11:59:04 -030017#include <linux/reset.h>
Alexander Bersenevb4e3e592014-06-08 15:08:10 -030018#include <media/rc-core.h>
19
20#define SUNXI_IR_DEV "sunxi-ir"
21
22/* Registers */
23/* IR Control */
24#define SUNXI_IR_CTL_REG 0x00
25/* Global Enable */
26#define REG_CTL_GEN BIT(0)
27/* RX block enable */
28#define REG_CTL_RXEN BIT(1)
29/* CIR mode */
30#define REG_CTL_MD (BIT(4) | BIT(5))
31
32/* Rx Config */
33#define SUNXI_IR_RXCTL_REG 0x10
34/* Pulse Polarity Invert flag */
35#define REG_RXCTL_RPPI BIT(2)
36
37/* Rx Data */
38#define SUNXI_IR_RXFIFO_REG 0x20
39
40/* Rx Interrupt Enable */
41#define SUNXI_IR_RXINT_REG 0x2C
Clément Péronb136d722019-06-07 20:10:51 -030042/* Rx FIFO Overflow Interrupt Enable */
Alexander Bersenevb4e3e592014-06-08 15:08:10 -030043#define REG_RXINT_ROI_EN BIT(0)
Clément Péronb136d722019-06-07 20:10:51 -030044/* Rx Packet End Interrupt Enable */
Alexander Bersenevb4e3e592014-06-08 15:08:10 -030045#define REG_RXINT_RPEI_EN BIT(1)
Clément Péronb136d722019-06-07 20:10:51 -030046/* Rx FIFO Data Available Interrupt Enable */
Alexander Bersenevb4e3e592014-06-08 15:08:10 -030047#define REG_RXINT_RAI_EN BIT(4)
48
49/* Rx FIFO available byte level */
Hans de Goedea4bca4c2014-11-20 12:10:47 -030050#define REG_RXINT_RAL(val) ((val) << 8)
Alexander Bersenevb4e3e592014-06-08 15:08:10 -030051
52/* Rx Interrupt Status */
53#define SUNXI_IR_RXSTA_REG 0x30
Clément Péronb136d722019-06-07 20:10:51 -030054/* Rx FIFO Overflow */
55#define REG_RXSTA_ROI REG_RXINT_ROI_EN
56/* Rx Packet End */
57#define REG_RXSTA_RPE REG_RXINT_RPEI_EN
58/* Rx FIFO Data Available */
59#define REG_RXSTA_RA REG_RXINT_RAI_EN
Alexander Bersenevb4e3e592014-06-08 15:08:10 -030060/* RX FIFO Get Available Counter */
Hans de Goedea4bca4c2014-11-20 12:10:47 -030061#define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1))
Alexander Bersenevb4e3e592014-06-08 15:08:10 -030062/* Clear all interrupt status value */
63#define REG_RXSTA_CLEARALL 0xff
64
65/* IR Sample Config */
66#define SUNXI_IR_CIR_REG 0x34
67/* CIR_REG register noise threshold */
68#define REG_CIR_NTHR(val) (((val) << 2) & (GENMASK(7, 2)))
69/* CIR_REG register idle threshold */
70#define REG_CIR_ITHR(val) (((val) << 8) & (GENMASK(15, 8)))
71
Philipp Rossak10e71202018-02-13 07:29:47 -050072/* Required frequency for IR0 or IR1 clock in CIR mode (default) */
Alexander Bersenevb4e3e592014-06-08 15:08:10 -030073#define SUNXI_IR_BASE_CLK 8000000
Alexander Bersenevb4e3e592014-06-08 15:08:10 -030074/* Noise threshold in samples */
75#define SUNXI_IR_RXNOISE 1
Alexander Bersenevb4e3e592014-06-08 15:08:10 -030076
Clément Péron6b197cb2019-06-07 20:10:49 -030077/**
78 * struct sunxi_ir_quirks - Differences between SoC variants.
79 *
80 * @has_reset: SoC needs reset deasserted.
81 * @fifo_size: size of the fifo.
82 */
83struct sunxi_ir_quirks {
84 bool has_reset;
85 int fifo_size;
86};
87
Alexander Bersenevb4e3e592014-06-08 15:08:10 -030088struct sunxi_ir {
89 spinlock_t ir_lock;
90 struct rc_dev *rc;
91 void __iomem *base;
92 int irq;
Hans de Goedea4bca4c2014-11-20 12:10:47 -030093 int fifo_size;
Alexander Bersenevb4e3e592014-06-08 15:08:10 -030094 struct clk *clk;
95 struct clk *apb_clk;
Hans de Goede44f8af62014-11-20 11:59:04 -030096 struct reset_control *rst;
Alexander Bersenevb4e3e592014-06-08 15:08:10 -030097 const char *map_name;
98};
99
100static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
101{
102 unsigned long status;
103 unsigned char dt;
104 unsigned int cnt, rc;
105 struct sunxi_ir *ir = dev_id;
Sean Young183e19f2018-08-21 15:57:52 -0400106 struct ir_raw_event rawir = {};
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300107
108 spin_lock(&ir->ir_lock);
109
110 status = readl(ir->base + SUNXI_IR_RXSTA_REG);
111
112 /* clean all pending statuses */
113 writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
114
Clément Péronb136d722019-06-07 20:10:51 -0300115 if (status & (REG_RXSTA_RA | REG_RXSTA_RPE)) {
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300116 /* How many messages in fifo */
117 rc = REG_RXSTA_GET_AC(status);
118 /* Sanity check */
Hans de Goedea4bca4c2014-11-20 12:10:47 -0300119 rc = rc > ir->fifo_size ? ir->fifo_size : rc;
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300120 /* If we have data */
121 for (cnt = 0; cnt < rc; cnt++) {
122 /* for each bit in fifo */
123 dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
124 rawir.pulse = (dt & 0x80) != 0;
Philipp Rossak10e71202018-02-13 07:29:47 -0500125 rawir.duration = ((dt & 0x7f) + 1) *
126 ir->rc->rx_resolution;
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300127 ir_raw_event_store_with_filter(ir->rc, &rawir);
128 }
129 }
130
Clément Péronb136d722019-06-07 20:10:51 -0300131 if (status & REG_RXSTA_ROI) {
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300132 ir_raw_event_reset(ir->rc);
Clément Péronb136d722019-06-07 20:10:51 -0300133 } else if (status & REG_RXSTA_RPE) {
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300134 ir_raw_event_set_idle(ir->rc, true);
135 ir_raw_event_handle(ir->rc);
Sean Young3f56df42020-11-09 23:16:52 +0100136 } else {
137 ir_raw_event_handle(ir->rc);
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300138 }
139
140 spin_unlock(&ir->ir_lock);
141
142 return IRQ_HANDLED;
143}
144
Sean Young371443d2020-11-10 09:30:38 +0100145/* Convert idle threshold to usec */
146static unsigned int sunxi_ithr_to_usec(unsigned int base_clk, unsigned int ithr)
147{
148 return DIV_ROUND_CLOSEST(USEC_PER_SEC * (ithr + 1),
149 base_clk / (128 * 64));
150}
151
152/* Convert usec to idle threshold */
153static unsigned int sunxi_usec_to_ithr(unsigned int base_clk, unsigned int usec)
154{
155 /* make sure we don't end up with a timeout less than requested */
156 return DIV_ROUND_UP((base_clk / (128 * 64)) * usec, USEC_PER_SEC) - 1;
157}
158
159static int sunxi_ir_set_timeout(struct rc_dev *rc_dev, unsigned int timeout)
160{
161 struct sunxi_ir *ir = rc_dev->priv;
162 unsigned int base_clk = clk_get_rate(ir->clk);
163 unsigned long flags;
164
165 unsigned int ithr = sunxi_usec_to_ithr(base_clk, timeout);
166
167 dev_dbg(rc_dev->dev.parent, "setting idle threshold to %u\n", ithr);
168
169 spin_lock_irqsave(&ir->ir_lock, flags);
170 /* Set noise threshold and idle threshold */
171 writel(REG_CIR_NTHR(SUNXI_IR_RXNOISE) | REG_CIR_ITHR(ithr),
172 ir->base + SUNXI_IR_CIR_REG);
173 spin_unlock_irqrestore(&ir->ir_lock, flags);
174
175 rc_dev->timeout = sunxi_ithr_to_usec(base_clk, ithr);
176
177 return 0;
178}
179
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300180static int sunxi_ir_probe(struct platform_device *pdev)
181{
182 int ret = 0;
183 unsigned long tmp = 0;
184
185 struct device *dev = &pdev->dev;
186 struct device_node *dn = dev->of_node;
Clément Péron6b197cb2019-06-07 20:10:49 -0300187 const struct sunxi_ir_quirks *quirks;
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300188 struct resource *res;
189 struct sunxi_ir *ir;
Philipp Rossak10e71202018-02-13 07:29:47 -0500190 u32 b_clk_freq = SUNXI_IR_BASE_CLK;
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300191
192 ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
193 if (!ir)
194 return -ENOMEM;
195
Clément Péron6b197cb2019-06-07 20:10:49 -0300196 quirks = of_device_get_match_data(&pdev->dev);
197 if (!quirks) {
198 dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
199 return -ENODEV;
200 }
201
Chen-Yu Tsai768acf42015-12-22 02:27:35 -0200202 spin_lock_init(&ir->ir_lock);
203
Clément Péron6b197cb2019-06-07 20:10:49 -0300204 ir->fifo_size = quirks->fifo_size;
Hans de Goedea4bca4c2014-11-20 12:10:47 -0300205
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300206 /* Clock */
207 ir->apb_clk = devm_clk_get(dev, "apb");
208 if (IS_ERR(ir->apb_clk)) {
209 dev_err(dev, "failed to get a apb clock.\n");
210 return PTR_ERR(ir->apb_clk);
211 }
212 ir->clk = devm_clk_get(dev, "ir");
213 if (IS_ERR(ir->clk)) {
214 dev_err(dev, "failed to get a ir clock.\n");
215 return PTR_ERR(ir->clk);
216 }
217
Philipp Rossak10e71202018-02-13 07:29:47 -0500218 /* Base clock frequency (optional) */
219 of_property_read_u32(dn, "clock-frequency", &b_clk_freq);
220
Clément Péron6b197cb2019-06-07 20:10:49 -0300221 /* Reset */
222 if (quirks->has_reset) {
223 ir->rst = devm_reset_control_get_exclusive(dev, NULL);
224 if (IS_ERR(ir->rst))
225 return PTR_ERR(ir->rst);
226 ret = reset_control_deassert(ir->rst);
227 if (ret)
228 return ret;
229 }
Hans de Goede44f8af62014-11-20 11:59:04 -0300230
Philipp Rossak10e71202018-02-13 07:29:47 -0500231 ret = clk_set_rate(ir->clk, b_clk_freq);
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300232 if (ret) {
233 dev_err(dev, "set ir base clock failed!\n");
Hans de Goede44f8af62014-11-20 11:59:04 -0300234 goto exit_reset_assert;
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300235 }
Philipp Rossak10e71202018-02-13 07:29:47 -0500236 dev_dbg(dev, "set base clock frequency to %d Hz.\n", b_clk_freq);
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300237
238 if (clk_prepare_enable(ir->apb_clk)) {
239 dev_err(dev, "try to enable apb_ir_clk failed\n");
Hans de Goede44f8af62014-11-20 11:59:04 -0300240 ret = -EINVAL;
241 goto exit_reset_assert;
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300242 }
243
244 if (clk_prepare_enable(ir->clk)) {
245 dev_err(dev, "try to enable ir_clk failed\n");
246 ret = -EINVAL;
247 goto exit_clkdisable_apb_clk;
248 }
249
250 /* IO */
251 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
252 ir->base = devm_ioremap_resource(dev, res);
253 if (IS_ERR(ir->base)) {
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300254 ret = PTR_ERR(ir->base);
255 goto exit_clkdisable_clk;
256 }
257
Andi Shyti0f7499f2016-12-16 06:50:58 -0200258 ir->rc = rc_allocate_device(RC_DRIVER_IR_RAW);
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300259 if (!ir->rc) {
260 dev_err(dev, "failed to allocate device\n");
261 ret = -ENOMEM;
262 goto exit_clkdisable_clk;
263 }
264
265 ir->rc->priv = ir;
Sean Young518f4b22017-07-01 12:13:19 -0400266 ir->rc->device_name = SUNXI_IR_DEV;
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300267 ir->rc->input_phys = "sunxi-ir/input0";
268 ir->rc->input_id.bustype = BUS_HOST;
269 ir->rc->input_id.vendor = 0x0001;
270 ir->rc->input_id.product = 0x0001;
271 ir->rc->input_id.version = 0x0100;
272 ir->map_name = of_get_property(dn, "linux,rc-map-name", NULL);
273 ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
274 ir->rc->dev.parent = dev;
Sean Young6d741bf2017-08-07 16:20:58 -0400275 ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
Sean Young371443d2020-11-10 09:30:38 +0100276 /* Frequency after IR internal divider with sample period in us */
Sean Young528222d82020-08-23 19:23:05 +0200277 ir->rc->rx_resolution = (USEC_PER_SEC / (b_clk_freq / 64));
Sean Young371443d2020-11-10 09:30:38 +0100278 ir->rc->min_timeout = sunxi_ithr_to_usec(b_clk_freq, 0);
279 ir->rc->max_timeout = sunxi_ithr_to_usec(b_clk_freq, 255);
280 ir->rc->s_timeout = sunxi_ir_set_timeout;
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300281 ir->rc->driver_name = SUNXI_IR_DEV;
282
283 ret = rc_register_device(ir->rc);
284 if (ret) {
285 dev_err(dev, "failed to register rc device\n");
286 goto exit_free_dev;
287 }
288
289 platform_set_drvdata(pdev, ir);
290
291 /* IRQ */
292 ir->irq = platform_get_irq(pdev, 0);
293 if (ir->irq < 0) {
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300294 ret = ir->irq;
295 goto exit_free_dev;
296 }
297
298 ret = devm_request_irq(dev, ir->irq, sunxi_ir_irq, 0, SUNXI_IR_DEV, ir);
299 if (ret) {
300 dev_err(dev, "failed request irq\n");
301 goto exit_free_dev;
302 }
303
304 /* Enable CIR Mode */
305 writel(REG_CTL_MD, ir->base+SUNXI_IR_CTL_REG);
306
307 /* Set noise threshold and idle threshold */
Sean Young371443d2020-11-10 09:30:38 +0100308 sunxi_ir_set_timeout(ir->rc, IR_DEFAULT_TIMEOUT);
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300309
310 /* Invert Input Signal */
311 writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG);
312
313 /* Clear All Rx Interrupt Status */
314 writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
315
316 /*
317 * Enable IRQ on overflow, packet end, FIFO available with trigger
318 * level
319 */
320 writel(REG_RXINT_ROI_EN | REG_RXINT_RPEI_EN |
Hans de Goedea4bca4c2014-11-20 12:10:47 -0300321 REG_RXINT_RAI_EN | REG_RXINT_RAL(ir->fifo_size / 2 - 1),
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300322 ir->base + SUNXI_IR_RXINT_REG);
323
324 /* Enable IR Module */
325 tmp = readl(ir->base + SUNXI_IR_CTL_REG);
326 writel(tmp | REG_CTL_GEN | REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG);
327
328 dev_info(dev, "initialized sunXi IR driver\n");
329 return 0;
330
331exit_free_dev:
332 rc_free_device(ir->rc);
333exit_clkdisable_clk:
334 clk_disable_unprepare(ir->clk);
335exit_clkdisable_apb_clk:
336 clk_disable_unprepare(ir->apb_clk);
Hans de Goede44f8af62014-11-20 11:59:04 -0300337exit_reset_assert:
Philipp Zabelc3d4fb02017-03-15 08:31:38 -0300338 reset_control_assert(ir->rst);
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300339
340 return ret;
341}
342
343static int sunxi_ir_remove(struct platform_device *pdev)
344{
345 unsigned long flags;
346 struct sunxi_ir *ir = platform_get_drvdata(pdev);
347
348 clk_disable_unprepare(ir->clk);
349 clk_disable_unprepare(ir->apb_clk);
Philipp Zabelc3d4fb02017-03-15 08:31:38 -0300350 reset_control_assert(ir->rst);
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300351
352 spin_lock_irqsave(&ir->ir_lock, flags);
353 /* disable IR IRQ */
354 writel(0, ir->base + SUNXI_IR_RXINT_REG);
355 /* clear All Rx Interrupt Status */
356 writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
357 /* disable IR */
358 writel(0, ir->base + SUNXI_IR_CTL_REG);
359 spin_unlock_irqrestore(&ir->ir_lock, flags);
360
361 rc_unregister_device(ir->rc);
362 return 0;
363}
364
Clément Péron6b197cb2019-06-07 20:10:49 -0300365static const struct sunxi_ir_quirks sun4i_a10_ir_quirks = {
366 .has_reset = false,
367 .fifo_size = 16,
368};
369
370static const struct sunxi_ir_quirks sun5i_a13_ir_quirks = {
371 .has_reset = false,
372 .fifo_size = 64,
373};
374
Clément Péron87d06092019-06-07 20:10:50 -0300375static const struct sunxi_ir_quirks sun6i_a31_ir_quirks = {
376 .has_reset = true,
377 .fifo_size = 64,
378};
379
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300380static const struct of_device_id sunxi_ir_match[] = {
Clément Péron6b197cb2019-06-07 20:10:49 -0300381 {
382 .compatible = "allwinner,sun4i-a10-ir",
383 .data = &sun4i_a10_ir_quirks,
384 },
385 {
386 .compatible = "allwinner,sun5i-a13-ir",
387 .data = &sun5i_a13_ir_quirks,
388 },
Clément Péron87d06092019-06-07 20:10:50 -0300389 {
390 .compatible = "allwinner,sun6i-a31-ir",
391 .data = &sun6i_a31_ir_quirks,
392 },
Clément Péron6b197cb2019-06-07 20:10:49 -0300393 {}
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300394};
Emilio Lópezea05e8b2016-02-21 22:26:34 -0300395MODULE_DEVICE_TABLE(of, sunxi_ir_match);
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300396
397static struct platform_driver sunxi_ir_driver = {
398 .probe = sunxi_ir_probe,
399 .remove = sunxi_ir_remove,
400 .driver = {
401 .name = SUNXI_IR_DEV,
Alexander Bersenevb4e3e592014-06-08 15:08:10 -0300402 .of_match_table = sunxi_ir_match,
403 },
404};
405
406module_platform_driver(sunxi_ir_driver);
407
408MODULE_DESCRIPTION("Allwinner sunXi IR controller driver");
409MODULE_AUTHOR("Alexsey Shestacov <wingrime@linux-sunxi.org>");
410MODULE_LICENSE("GPL");