blob: 938240714e54c2b6c41e52bc92e31c73d9819bc3 [file] [log] [blame]
Matthias Brugger13032702020-03-25 18:31:21 +01001// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: James Liao <jamesjj.liao@mediatek.com>
5 */
6
Enric Balletbo i Serraf27ef282021-09-30 10:31:49 +02007#include <linux/delay.h>
Enric Balletbo i Serra2c758e32020-03-25 18:31:22 +01008#include <linux/device.h>
Yongqiang Niu51c0e612020-10-06 21:33:17 +02009#include <linux/io.h>
Yongqiang Niua7596e62022-11-18 14:30:18 +080010#include <linux/module.h>
Rob Herringd01e0ae2023-08-03 16:42:59 -060011#include <linux/of.h>
Matthias Brugger13032702020-03-25 18:31:21 +010012#include <linux/platform_device.h>
Enric Balletbo i Serraf27ef282021-09-30 10:31:49 +020013#include <linux/reset-controller.h>
Enric Balletbo i Serra2c758e32020-03-25 18:31:22 +010014#include <linux/soc/mediatek/mtk-mmsys.h>
15
CK Hu44014762021-03-17 19:17:10 +010016#include "mtk-mmsys.h"
Fabien Parent060f7872021-04-05 22:03:53 +020017#include "mt8167-mmsys.h"
AngeloGioacchino Del Regno2a0a8d82023-03-09 11:26:16 +010018#include "mt8173-mmsys.h"
Hsin-Yi Wang1ff12702021-03-30 19:04:23 +080019#include "mt8183-mmsys.h"
Yongqiang Niu5f9b5b72022-02-22 13:28:01 +080020#include "mt8186-mmsys.h"
Nathan Lu3b1a57c2022-12-06 10:00:44 +080021#include "mt8188-mmsys.h"
Yongqiang Niud687e052021-08-02 16:59:33 +080022#include "mt8192-mmsys.h"
Jason-JH.Linb2b99a72022-09-27 23:27:01 +080023#include "mt8195-mmsys.h"
Fabien Parentbc3fc5c2021-05-19 18:18:46 +020024#include "mt8365-mmsys.h"
Matthias Brugger13032702020-03-25 18:31:21 +010025
Nancy.Lin2004f8b2023-01-13 18:44:31 +080026#define MMSYS_SW_RESET_PER_REG 32
27
Enric Balletbo i Serrac292b132020-04-01 22:17:35 +020028static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
29 .clk_driver = "clk-mt2701-mm",
CK Hu44014762021-03-17 19:17:10 +010030 .routes = mmsys_default_routing_table,
31 .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
Enric Balletbo i Serrac292b132020-04-01 22:17:35 +020032};
33
Enric Balletbo i Serra9c5a0a32020-04-01 22:17:34 +020034static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
35 .clk_driver = "clk-mt2712-mm",
CK Hu44014762021-03-17 19:17:10 +010036 .routes = mmsys_default_routing_table,
37 .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
Enric Balletbo i Serra9c5a0a32020-04-01 22:17:34 +020038};
39
Matthias Brugger32956dd2020-05-18 13:31:55 +020040static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
41 .clk_driver = "clk-mt6779-mm",
42};
43
AngeloGioacchino Del Regnoe9a6f5b2023-03-09 11:26:18 +010044static const struct mtk_mmsys_driver_data mt6795_mmsys_driver_data = {
45 .clk_driver = "clk-mt6795-mm",
46 .routes = mt8173_mmsys_routing_table,
47 .num_routes = ARRAY_SIZE(mt8173_mmsys_routing_table),
48 .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
49 .num_resets = 64,
50};
51
Matthias Bruggercad4e372020-05-18 13:31:54 +020052static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
53 .clk_driver = "clk-mt6797-mm",
54};
55
Fabien Parent060f7872021-04-05 22:03:53 +020056static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
57 .clk_driver = "clk-mt8167-mm",
58 .routes = mt8167_mmsys_routing_table,
59 .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
60};
61
Matthias Brugger13032702020-03-25 18:31:21 +010062static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
63 .clk_driver = "clk-mt8173-mm",
AngeloGioacchino Del Regno2a0a8d82023-03-09 11:26:16 +010064 .routes = mt8173_mmsys_routing_table,
65 .num_routes = ARRAY_SIZE(mt8173_mmsys_routing_table),
Rex-BC Chen62dc3012022-02-17 16:26:25 +080066 .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
AngeloGioacchino Del Regnob427d852023-03-09 11:26:17 +010067 .num_resets = 64,
Matthias Brugger13032702020-03-25 18:31:21 +010068};
69
Matthias Brugger1f9adbc2020-05-18 13:31:53 +020070static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
71 .clk_driver = "clk-mt8183-mm",
Hsin-Yi Wang1ff12702021-03-30 19:04:23 +080072 .routes = mmsys_mt8183_routing_table,
73 .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
Rex-BC Chen62dc3012022-02-17 16:26:25 +080074 .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
Nancy.Lin2004f8b2023-01-13 18:44:31 +080075 .num_resets = 32,
Matthias Brugger1f9adbc2020-05-18 13:31:53 +020076};
77
Yongqiang Niu5f9b5b72022-02-22 13:28:01 +080078static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
79 .clk_driver = "clk-mt8186-mm",
80 .routes = mmsys_mt8186_routing_table,
81 .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
Rex-BC Chen831785f2022-02-17 16:26:26 +080082 .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
Nancy.Lin2004f8b2023-01-13 18:44:31 +080083 .num_resets = 32,
Yongqiang Niu5f9b5b72022-02-22 13:28:01 +080084};
85
Nathan Lu3b1a57c2022-12-06 10:00:44 +080086static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
87 .clk_driver = "clk-mt8188-vdo0",
88 .routes = mmsys_mt8188_routing_table,
89 .num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table),
Hsiao Chien Sung27222a72023-10-24 21:00:35 +080090 .sw0_rst_offset = MT8188_VDO0_SW0_RST_B,
91 .rst_tb = mmsys_mt8188_vdo0_rst_tb,
92 .num_resets = ARRAY_SIZE(mmsys_mt8188_vdo0_rst_tb),
Nathan Lu3b1a57c2022-12-06 10:00:44 +080093};
94
Hsiao Chien Sungc0349312023-10-24 21:00:32 +080095static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = {
96 .clk_driver = "clk-mt8188-vdo1",
97 .routes = mmsys_mt8188_vdo1_routing_table,
98 .num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table),
Hsiao Chien Sung27222a72023-10-24 21:00:35 +080099 .sw0_rst_offset = MT8188_VDO1_SW0_RST_B,
100 .rst_tb = mmsys_mt8188_vdo1_rst_tb,
101 .num_resets = ARRAY_SIZE(mmsys_mt8188_vdo1_rst_tb),
Hsiao Chien Sungc0349312023-10-24 21:00:32 +0800102 .vsync_len = 1,
103};
104
yu-chang.leedfd78c12023-11-17 13:43:45 +0800105static const struct mtk_mmsys_driver_data mt8188_vppsys0_driver_data = {
106 .clk_driver = "clk-mt8188-vpp0",
107 .is_vppsys = true,
108};
109
110static const struct mtk_mmsys_driver_data mt8188_vppsys1_driver_data = {
111 .clk_driver = "clk-mt8188-vpp1",
112 .is_vppsys = true,
113};
114
Yongqiang Niud687e052021-08-02 16:59:33 +0800115static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
116 .clk_driver = "clk-mt8192-mm",
117 .routes = mmsys_mt8192_routing_table,
118 .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
AngeloGioacchino Del Regno9d7370a2022-03-23 10:19:32 +0100119 .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
Nancy.Lin2004f8b2023-01-13 18:44:31 +0800120 .num_resets = 32,
Yongqiang Niud687e052021-08-02 16:59:33 +0800121};
122
Jason-JH.Linb2b99a72022-09-27 23:27:01 +0800123static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
124 .clk_driver = "clk-mt8195-vdo0",
125 .routes = mmsys_mt8195_routing_table,
126 .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
127};
128
Nancy.Lin39170122023-01-13 18:44:27 +0800129static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
130 .clk_driver = "clk-mt8195-vdo1",
131 .routes = mmsys_mt8195_vdo1_routing_table,
132 .num_routes = ARRAY_SIZE(mmsys_mt8195_vdo1_routing_table),
Nancy.Lin7f0a38f2023-01-13 18:44:32 +0800133 .sw0_rst_offset = MT8195_VDO1_SW0_RST_B,
134 .num_resets = 64,
Nancy.Lin39170122023-01-13 18:44:27 +0800135};
136
Roy-CW.Yeh78ce3092023-01-18 11:15:09 +0800137static const struct mtk_mmsys_driver_data mt8195_vppsys0_driver_data = {
138 .clk_driver = "clk-mt8195-vpp0",
139 .is_vppsys = true,
140};
141
142static const struct mtk_mmsys_driver_data mt8195_vppsys1_driver_data = {
143 .clk_driver = "clk-mt8195-vpp1",
144 .is_vppsys = true,
145};
146
Fabien Parentbc3fc5c2021-05-19 18:18:46 +0200147static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
148 .clk_driver = "clk-mt8365-mm",
149 .routes = mt8365_mmsys_routing_table,
150 .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
151};
152
CK Huce15e7f2021-03-17 19:17:09 +0100153struct mtk_mmsys {
154 void __iomem *regs;
155 const struct mtk_mmsys_driver_data *data;
AngeloGioacchino Del Regno1ef3e782023-02-22 10:42:45 +0100156 struct platform_device *clks_pdev;
157 struct platform_device *drm_pdev;
Enric Balletbo i Serraf27ef282021-09-30 10:31:49 +0200158 spinlock_t lock; /* protects mmsys_sw_rst_b reg */
159 struct reset_controller_dev rcdev;
Nancy.Lin8af1f6b2023-01-13 18:44:30 +0800160 struct cmdq_client_reg cmdq_base;
CK Huce15e7f2021-03-17 19:17:09 +0100161};
162
Nancy.Lin8af1f6b2023-01-13 18:44:30 +0800163static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val,
164 struct cmdq_pkt *cmdq_pkt)
Nancy.Lin0a815032023-01-13 18:44:28 +0800165{
AngeloGioacchino Del Regnob34884b2023-02-22 10:42:53 +0100166 int ret;
Nancy.Lin0a815032023-01-13 18:44:28 +0800167 u32 tmp;
168
AngeloGioacchino Del Regnob34884b2023-02-22 10:42:53 +0100169 if (mmsys->cmdq_base.size && cmdq_pkt) {
170 ret = cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
171 mmsys->cmdq_base.offset + offset, val,
172 mask);
173 if (ret)
174 pr_debug("CMDQ unavailable: using CPU write\n");
175 else
Nancy.Lin8af1f6b2023-01-13 18:44:30 +0800176 return;
Nancy.Lin8af1f6b2023-01-13 18:44:30 +0800177 }
Nancy.Lin0a815032023-01-13 18:44:28 +0800178 tmp = readl_relaxed(mmsys->regs + offset);
179 tmp = (tmp & ~mask) | (val & mask);
180 writel_relaxed(tmp, mmsys->regs + offset);
181}
182
Enric Balletbo i Serra2c758e32020-03-25 18:31:22 +0100183void mtk_mmsys_ddp_connect(struct device *dev,
184 enum mtk_ddp_comp_id cur,
185 enum mtk_ddp_comp_id next)
186{
CK Huce15e7f2021-03-17 19:17:09 +0100187 struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
CK Hu44014762021-03-17 19:17:10 +0100188 const struct mtk_mmsys_routes *routes = mmsys->data->routes;
CK Hu44014762021-03-17 19:17:10 +0100189 int i;
Enric Balletbo i Serra2c758e32020-03-25 18:31:22 +0100190
CK Hu44014762021-03-17 19:17:10 +0100191 for (i = 0; i < mmsys->data->num_routes; i++)
Nancy.Lin0a815032023-01-13 18:44:28 +0800192 if (cur == routes[i].from_comp && next == routes[i].to_comp)
193 mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask,
Nancy.Lin8af1f6b2023-01-13 18:44:30 +0800194 routes[i].val, NULL);
Hsiao Chien Sungc0349312023-10-24 21:00:32 +0800195
196 if (mmsys->data->vsync_len)
197 mtk_mmsys_update_bits(mmsys, MT8188_VDO1_MIXER_VSYNC_LEN, GENMASK(31, 0),
198 mmsys->data->vsync_len, NULL);
Enric Balletbo i Serra2c758e32020-03-25 18:31:22 +0100199}
200EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
201
202void mtk_mmsys_ddp_disconnect(struct device *dev,
203 enum mtk_ddp_comp_id cur,
204 enum mtk_ddp_comp_id next)
205{
CK Huce15e7f2021-03-17 19:17:09 +0100206 struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
CK Hu44014762021-03-17 19:17:10 +0100207 const struct mtk_mmsys_routes *routes = mmsys->data->routes;
CK Hu44014762021-03-17 19:17:10 +0100208 int i;
Enric Balletbo i Serra2c758e32020-03-25 18:31:22 +0100209
CK Hu44014762021-03-17 19:17:10 +0100210 for (i = 0; i < mmsys->data->num_routes; i++)
Nancy.Lin0a815032023-01-13 18:44:28 +0800211 if (cur == routes[i].from_comp && next == routes[i].to_comp)
Nancy.Lin8af1f6b2023-01-13 18:44:30 +0800212 mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, 0, NULL);
Enric Balletbo i Serra2c758e32020-03-25 18:31:22 +0100213}
214EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
215
Nancy.Lin8af1f6b2023-01-13 18:44:30 +0800216void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height,
217 struct cmdq_pkt *cmdq_pkt)
Nancy.Lin3dd20b72023-01-13 18:44:29 +0800218{
219 mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MERGE0_ASYNC_CFG_WD + 0x10 * idx,
Nancy.Lin8af1f6b2023-01-13 18:44:30 +0800220 ~0, height << 16 | width, cmdq_pkt);
Nancy.Lin3dd20b72023-01-13 18:44:29 +0800221}
222EXPORT_SYMBOL_GPL(mtk_mmsys_merge_async_config);
223
Nancy.Lin8af1f6b2023-01-13 18:44:30 +0800224void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height,
225 struct cmdq_pkt *cmdq_pkt)
Nancy.Lin3dd20b72023-01-13 18:44:29 +0800226{
227 mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_HDRBE_ASYNC_CFG_WD, ~0,
Nancy.Lin8af1f6b2023-01-13 18:44:30 +0800228 be_height << 16 | be_width, cmdq_pkt);
Nancy.Lin3dd20b72023-01-13 18:44:29 +0800229}
230EXPORT_SYMBOL_GPL(mtk_mmsys_hdr_config);
231
232void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha,
Nancy.Lin8af1f6b2023-01-13 18:44:30 +0800233 u8 mode, u32 biwidth, struct cmdq_pkt *cmdq_pkt)
Nancy.Lin3dd20b72023-01-13 18:44:29 +0800234{
235 struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
236
237 mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx - 1) * 4, ~0,
Nancy.Lin8af1f6b2023-01-13 18:44:30 +0800238 alpha << 16 | alpha, cmdq_pkt);
Hsiao Chien Sung7cc069d2024-06-20 00:50:24 +0800239 mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(15 + idx), 0, cmdq_pkt);
Nancy.Lin3dd20b72023-01-13 18:44:29 +0800240 mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 + idx),
Nancy.Lin8af1f6b2023-01-13 18:44:30 +0800241 alpha_sel << (19 + idx), cmdq_pkt);
Nancy.Lin3dd20b72023-01-13 18:44:29 +0800242 mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
Nancy.Lin8af1f6b2023-01-13 18:44:30 +0800243 GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode, cmdq_pkt);
Nancy.Lin3dd20b72023-01-13 18:44:29 +0800244}
245EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config);
246
Nancy.Lin8af1f6b2023-01-13 18:44:30 +0800247void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap,
248 struct cmdq_pkt *cmdq_pkt)
Nancy.Lin3dd20b72023-01-13 18:44:29 +0800249{
250 mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
Nancy.Lin8af1f6b2023-01-13 18:44:30 +0800251 BIT(4), channel_swap << 4, cmdq_pkt);
Nancy.Lin3dd20b72023-01-13 18:44:29 +0800252}
253EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_channel_swap);
254
Xinlei Leeb404cb42022-09-14 21:21:00 +0800255void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)
256{
Xinlei Leee6c7e622022-11-08 19:23:27 +0100257 struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
258
259 switch (val) {
260 case MTK_DPI_RGB888_SDR_CON:
261 mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT,
Nancy.Lin8af1f6b2023-01-13 18:44:30 +0800262 MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_SDR_CON, NULL);
Xinlei Leee6c7e622022-11-08 19:23:27 +0100263 break;
264 case MTK_DPI_RGB565_SDR_CON:
265 mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT,
Nancy.Lin8af1f6b2023-01-13 18:44:30 +0800266 MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_SDR_CON, NULL);
Xinlei Leee6c7e622022-11-08 19:23:27 +0100267 break;
268 case MTK_DPI_RGB565_DDR_CON:
269 mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT,
Nancy.Lin8af1f6b2023-01-13 18:44:30 +0800270 MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_DDR_CON, NULL);
Xinlei Leee6c7e622022-11-08 19:23:27 +0100271 break;
272 case MTK_DPI_RGB888_DDR_CON:
273 default:
274 mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT,
Nancy.Lin8af1f6b2023-01-13 18:44:30 +0800275 MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_DDR_CON, NULL);
Xinlei Leee6c7e622022-11-08 19:23:27 +0100276 break;
277 }
Xinlei Leeb404cb42022-09-14 21:21:00 +0800278}
279EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_dpi_fmt_config);
280
Roy-CW.Yehdd4f3732023-02-06 17:11:07 +0800281void mtk_mmsys_vpp_rsz_merge_config(struct device *dev, u32 id, bool enable,
282 struct cmdq_pkt *cmdq_pkt)
283{
284 u32 reg;
285
286 switch (id) {
287 case 2:
288 reg = MT8195_SVPP2_BUF_BF_RSZ_SWITCH;
289 break;
290 case 3:
291 reg = MT8195_SVPP3_BUF_BF_RSZ_SWITCH;
292 break;
293 default:
294 dev_err(dev, "Invalid id %d\n", id);
295 return;
296 }
297
298 mtk_mmsys_update_bits(dev_get_drvdata(dev), reg, ~0, enable, cmdq_pkt);
299}
300EXPORT_SYMBOL_GPL(mtk_mmsys_vpp_rsz_merge_config);
301
302void mtk_mmsys_vpp_rsz_dcm_config(struct device *dev, bool enable,
303 struct cmdq_pkt *cmdq_pkt)
304{
305 u32 client;
306
307 client = MT8195_SVPP1_MDP_RSZ;
308 mtk_mmsys_update_bits(dev_get_drvdata(dev),
309 MT8195_VPP1_HW_DCM_1ST_DIS0, client,
310 ((enable) ? client : 0), cmdq_pkt);
311 mtk_mmsys_update_bits(dev_get_drvdata(dev),
312 MT8195_VPP1_HW_DCM_2ND_DIS0, client,
313 ((enable) ? client : 0), cmdq_pkt);
314
315 client = MT8195_SVPP2_MDP_RSZ | MT8195_SVPP3_MDP_RSZ;
316 mtk_mmsys_update_bits(dev_get_drvdata(dev),
317 MT8195_VPP1_HW_DCM_1ST_DIS1, client,
318 ((enable) ? client : 0), cmdq_pkt);
319 mtk_mmsys_update_bits(dev_get_drvdata(dev),
320 MT8195_VPP1_HW_DCM_2ND_DIS1, client,
321 ((enable) ? client : 0), cmdq_pkt);
322}
323EXPORT_SYMBOL_GPL(mtk_mmsys_vpp_rsz_dcm_config);
324
Enric Balletbo i Serraf27ef282021-09-30 10:31:49 +0200325static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
326 bool assert)
327{
328 struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
329 unsigned long flags;
Nancy.Lin2004f8b2023-01-13 18:44:31 +0800330 u32 offset;
331 u32 reg;
332
Hsiao Chien Sung67637de2023-10-24 21:00:34 +0800333 if (mmsys->data->rst_tb) {
334 if (id >= mmsys->data->num_resets) {
335 dev_err(rcdev->dev, "Invalid reset ID: %lu (>=%u)\n",
336 id, mmsys->data->num_resets);
337 return -EINVAL;
338 }
339 id = mmsys->data->rst_tb[id];
340 }
341
Nancy.Lin2004f8b2023-01-13 18:44:31 +0800342 offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
343 id = id % MMSYS_SW_RESET_PER_REG;
344 reg = mmsys->data->sw0_rst_offset + offset;
Enric Balletbo i Serraf27ef282021-09-30 10:31:49 +0200345
346 spin_lock_irqsave(&mmsys->lock, flags);
347
Enric Balletbo i Serraf27ef282021-09-30 10:31:49 +0200348 if (assert)
Nancy.Lin2004f8b2023-01-13 18:44:31 +0800349 mtk_mmsys_update_bits(mmsys, reg, BIT(id), 0, NULL);
Enric Balletbo i Serraf27ef282021-09-30 10:31:49 +0200350 else
Nancy.Lin2004f8b2023-01-13 18:44:31 +0800351 mtk_mmsys_update_bits(mmsys, reg, BIT(id), BIT(id), NULL);
Enric Balletbo i Serraf27ef282021-09-30 10:31:49 +0200352
353 spin_unlock_irqrestore(&mmsys->lock, flags);
354
355 return 0;
356}
357
358static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
359{
360 return mtk_mmsys_reset_update(rcdev, id, true);
361}
362
363static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
364{
365 return mtk_mmsys_reset_update(rcdev, id, false);
366}
367
368static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id)
369{
370 int ret;
371
372 ret = mtk_mmsys_reset_assert(rcdev, id);
373 if (ret)
374 return ret;
375
376 usleep_range(1000, 1100);
377
378 return mtk_mmsys_reset_deassert(rcdev, id);
379}
380
381static const struct reset_control_ops mtk_mmsys_reset_ops = {
382 .assert = mtk_mmsys_reset_assert,
383 .deassert = mtk_mmsys_reset_deassert,
384 .reset = mtk_mmsys_reset,
385};
386
Matthias Brugger13032702020-03-25 18:31:21 +0100387static int mtk_mmsys_probe(struct platform_device *pdev)
388{
Enric Balletbo i Serra2c758e32020-03-25 18:31:22 +0100389 struct device *dev = &pdev->dev;
Matthias Brugger13032702020-03-25 18:31:21 +0100390 struct platform_device *clks;
Enric Balletbo i Serra667c7692020-03-25 18:31:23 +0100391 struct platform_device *drm;
CK Huce15e7f2021-03-17 19:17:09 +0100392 struct mtk_mmsys *mmsys;
Enric Balletbo i Serra2c758e32020-03-25 18:31:22 +0100393 int ret;
394
CK Huce15e7f2021-03-17 19:17:09 +0100395 mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
396 if (!mmsys)
397 return -ENOMEM;
398
399 mmsys->regs = devm_platform_ioremap_resource(pdev, 0);
400 if (IS_ERR(mmsys->regs)) {
401 ret = PTR_ERR(mmsys->regs);
Enric Balletbo i Serracc657602020-10-06 21:33:18 +0200402 dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
Enric Balletbo i Serra2c758e32020-03-25 18:31:22 +0100403 return ret;
404 }
405
Jason-JH.Lin8d8ccdd2022-09-27 23:27:00 +0800406 mmsys->data = of_device_get_match_data(&pdev->dev);
Nancy.Lin8af1f6b2023-01-13 18:44:30 +0800407
Nancy.Lin2004f8b2023-01-13 18:44:31 +0800408 if (mmsys->data->num_resets > 0) {
409 spin_lock_init(&mmsys->lock);
410
411 mmsys->rcdev.owner = THIS_MODULE;
412 mmsys->rcdev.nr_resets = mmsys->data->num_resets;
413 mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
414 mmsys->rcdev.of_node = pdev->dev.of_node;
415 ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
416 if (ret) {
417 dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
418 return ret;
419 }
420 }
421
AngeloGioacchino Del Regnob34884b2023-02-22 10:42:53 +0100422 /* CMDQ is optional */
Nancy.Lin8af1f6b2023-01-13 18:44:30 +0800423 ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
424 if (ret)
425 dev_dbg(dev, "No mediatek,gce-client-reg!\n");
Nancy.Lin8af1f6b2023-01-13 18:44:30 +0800426
CK Huce15e7f2021-03-17 19:17:09 +0100427 platform_set_drvdata(pdev, mmsys);
Matthias Brugger13032702020-03-25 18:31:21 +0100428
CK Huce15e7f2021-03-17 19:17:09 +0100429 clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
Matthias Brugger13032702020-03-25 18:31:21 +0100430 PLATFORM_DEVID_AUTO, NULL, 0);
431 if (IS_ERR(clks))
432 return PTR_ERR(clks);
AngeloGioacchino Del Regno1ef3e782023-02-22 10:42:45 +0100433 mmsys->clks_pdev = clks;
Matthias Brugger13032702020-03-25 18:31:21 +0100434
Roy-CW.Yeh78ce3092023-01-18 11:15:09 +0800435 if (mmsys->data->is_vppsys)
436 goto out_probe_done;
437
Enric Balletbo i Serra667c7692020-03-25 18:31:23 +0100438 drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
439 PLATFORM_DEVID_AUTO, NULL, 0);
Wei Yongjunff34e172020-05-06 14:13:17 +0000440 if (IS_ERR(drm)) {
441 platform_device_unregister(clks);
Enric Balletbo i Serra667c7692020-03-25 18:31:23 +0100442 return PTR_ERR(drm);
Wei Yongjunff34e172020-05-06 14:13:17 +0000443 }
AngeloGioacchino Del Regno1ef3e782023-02-22 10:42:45 +0100444 mmsys->drm_pdev = drm;
Enric Balletbo i Serra667c7692020-03-25 18:31:23 +0100445
Roy-CW.Yeh78ce3092023-01-18 11:15:09 +0800446out_probe_done:
Matthias Brugger13032702020-03-25 18:31:21 +0100447 return 0;
448}
449
Uwe Kleine-König630cc5e2023-09-25 11:55:06 +0200450static void mtk_mmsys_remove(struct platform_device *pdev)
AngeloGioacchino Del Regno1ef3e782023-02-22 10:42:45 +0100451{
452 struct mtk_mmsys *mmsys = platform_get_drvdata(pdev);
453
454 platform_device_unregister(mmsys->drm_pdev);
455 platform_device_unregister(mmsys->clks_pdev);
AngeloGioacchino Del Regno1ef3e782023-02-22 10:42:45 +0100456}
457
Matthias Brugger13032702020-03-25 18:31:21 +0100458static const struct of_device_id of_match_mtk_mmsys[] = {
AngeloGioacchino Del Regno0fe09bf2023-02-22 10:42:47 +0100459 { .compatible = "mediatek,mt2701-mmsys", .data = &mt2701_mmsys_driver_data },
460 { .compatible = "mediatek,mt2712-mmsys", .data = &mt2712_mmsys_driver_data },
461 { .compatible = "mediatek,mt6779-mmsys", .data = &mt6779_mmsys_driver_data },
AngeloGioacchino Del Regnoe9a6f5b2023-03-09 11:26:18 +0100462 { .compatible = "mediatek,mt6795-mmsys", .data = &mt6795_mmsys_driver_data },
AngeloGioacchino Del Regno0fe09bf2023-02-22 10:42:47 +0100463 { .compatible = "mediatek,mt6797-mmsys", .data = &mt6797_mmsys_driver_data },
464 { .compatible = "mediatek,mt8167-mmsys", .data = &mt8167_mmsys_driver_data },
465 { .compatible = "mediatek,mt8173-mmsys", .data = &mt8173_mmsys_driver_data },
466 { .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data },
467 { .compatible = "mediatek,mt8186-mmsys", .data = &mt8186_mmsys_driver_data },
468 { .compatible = "mediatek,mt8188-vdosys0", .data = &mt8188_vdosys0_driver_data },
Hsiao Chien Sungc0349312023-10-24 21:00:32 +0800469 { .compatible = "mediatek,mt8188-vdosys1", .data = &mt8188_vdosys1_driver_data },
yu-chang.leedfd78c12023-11-17 13:43:45 +0800470 { .compatible = "mediatek,mt8188-vppsys0", .data = &mt8188_vppsys0_driver_data },
471 { .compatible = "mediatek,mt8188-vppsys1", .data = &mt8188_vppsys1_driver_data },
AngeloGioacchino Del Regno0fe09bf2023-02-22 10:42:47 +0100472 { .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data },
473 /* "mediatek,mt8195-mmsys" compatible is deprecated */
474 { .compatible = "mediatek,mt8195-mmsys", .data = &mt8195_vdosys0_driver_data },
475 { .compatible = "mediatek,mt8195-vdosys0", .data = &mt8195_vdosys0_driver_data },
476 { .compatible = "mediatek,mt8195-vdosys1", .data = &mt8195_vdosys1_driver_data },
477 { .compatible = "mediatek,mt8195-vppsys0", .data = &mt8195_vppsys0_driver_data },
478 { .compatible = "mediatek,mt8195-vppsys1", .data = &mt8195_vppsys1_driver_data },
479 { .compatible = "mediatek,mt8365-mmsys", .data = &mt8365_mmsys_driver_data },
480 { /* sentinel */ }
Matthias Brugger13032702020-03-25 18:31:21 +0100481};
AngeloGioacchino Del Regno10687632023-02-22 10:42:48 +0100482MODULE_DEVICE_TABLE(of, of_match_mtk_mmsys);
Matthias Brugger13032702020-03-25 18:31:21 +0100483
484static struct platform_driver mtk_mmsys_drv = {
485 .driver = {
486 .name = "mtk-mmsys",
487 .of_match_table = of_match_mtk_mmsys,
488 },
489 .probe = mtk_mmsys_probe,
Uwe Kleine-König630cc5e2023-09-25 11:55:06 +0200490 .remove_new = mtk_mmsys_remove,
Matthias Brugger13032702020-03-25 18:31:21 +0100491};
AngeloGioacchino Del Regno683c7d32023-02-22 10:42:46 +0100492module_platform_driver(mtk_mmsys_drv);
Yongqiang Niua7596e62022-11-18 14:30:18 +0800493
494MODULE_AUTHOR("Yongqiang Niu <yongqiang.niu@mediatek.com>");
495MODULE_DESCRIPTION("MediaTek SoC MMSYS driver");
496MODULE_LICENSE("GPL");