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Thomas Gleixner3c910ec2019-06-01 10:09:00 +02001// SPDX-License-Identifier: GPL-2.0-only
Beniamino Galvani6ac73092015-01-17 19:15:14 +01002/*
3 * Pin controller and GPIO driver for Amlogic Meson SoCs
4 *
5 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
Beniamino Galvani6ac73092015-01-17 19:15:14 +01006 */
7
8/*
9 * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO,
Carlo Caionefaa246d2015-03-19 22:34:11 +010010 * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and
11 * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a
12 * variable number of pins.
Beniamino Galvani6ac73092015-01-17 19:15:14 +010013 *
14 * The AO bank is special because it belongs to the Always-On power
15 * domain which can't be powered off; the bank also uses a set of
16 * registers different from the other banks.
17 *
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +020018 * For each pin controller there are 4 different register ranges that
19 * control the following properties of the pins:
Beniamino Galvani6ac73092015-01-17 19:15:14 +010020 * 1) pin muxing
21 * 2) pull enable/disable
22 * 3) pull up/down
23 * 4) GPIO direction, output value, input value
24 *
25 * In some cases the register ranges for pull enable and pull
26 * direction are the same and thus there are only 3 register ranges.
27 *
Xingyu Chene66dd482019-01-17 11:23:14 +010028 * Since Meson G12A SoC, the ao register ranges for gpio, pull enable
29 * and pull direction are the same, so there are only 2 register ranges.
30 *
Beniamino Galvani6ac73092015-01-17 19:15:14 +010031 * For the pull and GPIO configuration every bank uses a contiguous
32 * set of bits in the register sets described above; the same register
33 * can be shared by more banks with different offsets.
34 *
35 * In addition to this there are some registers shared between all
36 * banks that control the IRQ functionality. This feature is not
37 * supported at the moment by the driver.
38 */
39
40#include <linux/device.h>
Linus Walleij1c5fb662018-09-13 13:58:21 +020041#include <linux/gpio/driver.h>
Beniamino Galvani6ac73092015-01-17 19:15:14 +010042#include <linux/init.h>
43#include <linux/io.h>
Beniamino Galvani6ac73092015-01-17 19:15:14 +010044#include <linux/of.h>
45#include <linux/of_address.h>
46#include <linux/pinctrl/pinconf-generic.h>
47#include <linux/pinctrl/pinconf.h>
48#include <linux/pinctrl/pinctrl.h>
49#include <linux/pinctrl/pinmux.h>
50#include <linux/platform_device.h>
Andy Shevchenkoedc56012022-04-01 13:36:02 +030051#include <linux/property.h>
Beniamino Galvani6ac73092015-01-17 19:15:14 +010052#include <linux/regmap.h>
53#include <linux/seq_file.h>
54
55#include "../core.h"
56#include "../pinctrl-utils.h"
57#include "pinctrl-meson.h"
58
Hyeonki Hongf088ab62020-06-18 11:59:22 +090059static const unsigned int meson_bit_strides[] = {
60 1, 1, 1, 1, 1, 2, 1
61};
62
Beniamino Galvani6ac73092015-01-17 19:15:14 +010063/**
64 * meson_get_bank() - find the bank containing a given pin
65 *
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +020066 * @pc: the pinctrl instance
Beniamino Galvani6ac73092015-01-17 19:15:14 +010067 * @pin: the pin number
68 * @bank: the found bank
69 *
70 * Return: 0 on success, a negative value on error
71 */
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +020072static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin,
Beniamino Galvani6ac73092015-01-17 19:15:14 +010073 struct meson_bank **bank)
74{
75 int i;
76
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +020077 for (i = 0; i < pc->data->num_banks; i++) {
78 if (pin >= pc->data->banks[i].first &&
79 pin <= pc->data->banks[i].last) {
80 *bank = &pc->data->banks[i];
Beniamino Galvani6ac73092015-01-17 19:15:14 +010081 return 0;
82 }
83 }
84
85 return -EINVAL;
86}
87
88/**
Beniamino Galvani6ac73092015-01-17 19:15:14 +010089 * meson_calc_reg_and_bit() - calculate register and bit for a pin
90 *
91 * @bank: the bank containing the pin
92 * @pin: the pin number
93 * @reg_type: the type of register needed (pull-enable, pull, etc...)
94 * @reg: the computed register offset
95 * @bit: the computed bit
96 */
97static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin,
98 enum meson_reg_type reg_type,
99 unsigned int *reg, unsigned int *bit)
100{
101 struct meson_reg_desc *desc = &bank->regs[reg_type];
102
Hyeonki Hongf088ab62020-06-18 11:59:22 +0900103 *bit = (desc->bit + pin - bank->first) * meson_bit_strides[reg_type];
104 *reg = (desc->reg + (*bit / 32)) * 4;
105 *bit &= 0x1f;
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100106}
107
108static int meson_get_groups_count(struct pinctrl_dev *pcdev)
109{
110 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
111
112 return pc->data->num_groups;
113}
114
115static const char *meson_get_group_name(struct pinctrl_dev *pcdev,
116 unsigned selector)
117{
118 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
119
120 return pc->data->groups[selector].name;
121}
122
123static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector,
124 const unsigned **pins, unsigned *num_pins)
125{
126 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
127
128 *pins = pc->data->groups[selector].pins;
129 *num_pins = pc->data->groups[selector].num_pins;
130
131 return 0;
132}
133
134static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s,
135 unsigned offset)
136{
137 seq_printf(s, " %s", dev_name(pcdev->dev));
138}
139
140static const struct pinctrl_ops meson_pctrl_ops = {
141 .get_groups_count = meson_get_groups_count,
142 .get_group_name = meson_get_group_name,
143 .get_group_pins = meson_get_group_pins,
144 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
Irina Tirdead32f7fd2016-03-31 14:44:42 +0300145 .dt_free_map = pinctrl_utils_free_map,
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100146 .pin_dbg_show = meson_pin_dbg_show,
147};
148
Jerome Brunetce385aa2017-10-12 14:40:26 +0200149int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev)
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100150{
151 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
152
153 return pc->data->num_funcs;
154}
Kevin Hilman9c654412020-10-26 11:30:25 -0700155EXPORT_SYMBOL_GPL(meson_pmx_get_funcs_count);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100156
Jerome Brunetce385aa2017-10-12 14:40:26 +0200157const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev,
158 unsigned selector)
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100159{
160 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
161
162 return pc->data->funcs[selector].name;
163}
Kevin Hilman9c654412020-10-26 11:30:25 -0700164EXPORT_SYMBOL_GPL(meson_pmx_get_func_name);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100165
Jerome Brunetce385aa2017-10-12 14:40:26 +0200166int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector,
167 const char * const **groups,
168 unsigned * const num_groups)
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100169{
170 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
171
172 *groups = pc->data->funcs[selector].groups;
173 *num_groups = pc->data->funcs[selector].num_groups;
174
175 return 0;
176}
Kevin Hilman9c654412020-10-26 11:30:25 -0700177EXPORT_SYMBOL_GPL(meson_pmx_get_groups);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100178
Jerome Brunetb22a7f82019-05-16 17:13:39 +0200179static int meson_pinconf_set_gpio_bit(struct meson_pinctrl *pc,
180 unsigned int pin,
181 unsigned int reg_type,
182 bool arg)
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100183{
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100184 struct meson_bank *bank;
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100185 unsigned int reg, bit;
Jerome Brunetb22a7f82019-05-16 17:13:39 +0200186 int ret;
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100187
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200188 ret = meson_get_bank(pc, pin, &bank);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100189 if (ret)
190 return ret;
191
Jerome Brunetb22a7f82019-05-16 17:13:39 +0200192 meson_calc_reg_and_bit(bank, pin, reg_type, &reg, &bit);
193 return regmap_update_bits(pc->reg_gpio, reg, BIT(bit),
194 arg ? BIT(bit) : 0);
195}
196
197static int meson_pinconf_get_gpio_bit(struct meson_pinctrl *pc,
198 unsigned int pin,
199 unsigned int reg_type)
200{
201 struct meson_bank *bank;
202 unsigned int reg, bit, val;
203 int ret;
204
205 ret = meson_get_bank(pc, pin, &bank);
206 if (ret)
207 return ret;
208
209 meson_calc_reg_and_bit(bank, pin, reg_type, &reg, &bit);
210 ret = regmap_read(pc->reg_gpio, reg, &val);
211 if (ret)
212 return ret;
213
214 return BIT(bit) & val ? 1 : 0;
215}
216
217static int meson_pinconf_set_output(struct meson_pinctrl *pc,
218 unsigned int pin,
219 bool out)
220{
Andy Shevchenko2b2dce82022-04-01 13:36:00 +0300221 return meson_pinconf_set_gpio_bit(pc, pin, MESON_REG_DIR, !out);
Jerome Brunetb22a7f82019-05-16 17:13:39 +0200222}
223
224static int meson_pinconf_get_output(struct meson_pinctrl *pc,
225 unsigned int pin)
226{
Andy Shevchenko2b2dce82022-04-01 13:36:00 +0300227 int ret = meson_pinconf_get_gpio_bit(pc, pin, MESON_REG_DIR);
Jerome Brunetb22a7f82019-05-16 17:13:39 +0200228
229 if (ret < 0)
230 return ret;
231
232 return !ret;
233}
234
235static int meson_pinconf_set_drive(struct meson_pinctrl *pc,
236 unsigned int pin,
237 bool high)
238{
Andy Shevchenko2b2dce82022-04-01 13:36:00 +0300239 return meson_pinconf_set_gpio_bit(pc, pin, MESON_REG_OUT, high);
Jerome Brunetb22a7f82019-05-16 17:13:39 +0200240}
241
242static int meson_pinconf_get_drive(struct meson_pinctrl *pc,
243 unsigned int pin)
244{
Andy Shevchenko2b2dce82022-04-01 13:36:00 +0300245 return meson_pinconf_get_gpio_bit(pc, pin, MESON_REG_OUT);
Jerome Brunetb22a7f82019-05-16 17:13:39 +0200246}
247
248static int meson_pinconf_set_output_drive(struct meson_pinctrl *pc,
249 unsigned int pin,
250 bool high)
251{
252 int ret;
253
254 ret = meson_pinconf_set_output(pc, pin, true);
255 if (ret)
256 return ret;
257
258 return meson_pinconf_set_drive(pc, pin, high);
259}
260
Guillaume La Roque9959d9a2019-05-14 10:26:50 +0200261static int meson_pinconf_disable_bias(struct meson_pinctrl *pc,
262 unsigned int pin)
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100263{
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100264 struct meson_bank *bank;
Guillaume La Roque9959d9a2019-05-14 10:26:50 +0200265 unsigned int reg, bit = 0;
266 int ret;
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100267
268 ret = meson_get_bank(pc, pin, &bank);
269 if (ret)
270 return ret;
271
Andy Shevchenko2b2dce82022-04-01 13:36:00 +0300272 meson_calc_reg_and_bit(bank, pin, MESON_REG_PULLEN, &reg, &bit);
Guillaume La Roque9959d9a2019-05-14 10:26:50 +0200273 ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), 0);
274 if (ret)
275 return ret;
276
277 return 0;
278}
279
280static int meson_pinconf_enable_bias(struct meson_pinctrl *pc, unsigned int pin,
281 bool pull_up)
282{
283 struct meson_bank *bank;
284 unsigned int reg, bit, val = 0;
285 int ret;
286
287 ret = meson_get_bank(pc, pin, &bank);
288 if (ret)
289 return ret;
290
Andy Shevchenko2b2dce82022-04-01 13:36:00 +0300291 meson_calc_reg_and_bit(bank, pin, MESON_REG_PULL, &reg, &bit);
Guillaume La Roque9959d9a2019-05-14 10:26:50 +0200292 if (pull_up)
293 val = BIT(bit);
294
295 ret = regmap_update_bits(pc->reg_pull, reg, BIT(bit), val);
296 if (ret)
297 return ret;
298
Andy Shevchenko2b2dce82022-04-01 13:36:00 +0300299 meson_calc_reg_and_bit(bank, pin, MESON_REG_PULLEN, &reg, &bit);
Guillaume La Roque9959d9a2019-05-14 10:26:50 +0200300 ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), BIT(bit));
301 if (ret)
302 return ret;
303
304 return 0;
305}
306
Guillaume La Roque6ea3e3b2019-05-14 10:26:51 +0200307static int meson_pinconf_set_drive_strength(struct meson_pinctrl *pc,
308 unsigned int pin,
309 u16 drive_strength_ua)
310{
311 struct meson_bank *bank;
312 unsigned int reg, bit, ds_val;
313 int ret;
314
315 if (!pc->reg_ds) {
316 dev_err(pc->dev, "drive-strength not supported\n");
317 return -ENOTSUPP;
318 }
319
320 ret = meson_get_bank(pc, pin, &bank);
321 if (ret)
322 return ret;
323
Andy Shevchenko2b2dce82022-04-01 13:36:00 +0300324 meson_calc_reg_and_bit(bank, pin, MESON_REG_DS, &reg, &bit);
Guillaume La Roque6ea3e3b2019-05-14 10:26:51 +0200325
326 if (drive_strength_ua <= 500) {
327 ds_val = MESON_PINCONF_DRV_500UA;
328 } else if (drive_strength_ua <= 2500) {
329 ds_val = MESON_PINCONF_DRV_2500UA;
330 } else if (drive_strength_ua <= 3000) {
331 ds_val = MESON_PINCONF_DRV_3000UA;
332 } else if (drive_strength_ua <= 4000) {
333 ds_val = MESON_PINCONF_DRV_4000UA;
334 } else {
335 dev_warn_once(pc->dev,
336 "pin %u: invalid drive-strength : %d , default to 4mA\n",
337 pin, drive_strength_ua);
338 ds_val = MESON_PINCONF_DRV_4000UA;
339 }
340
341 ret = regmap_update_bits(pc->reg_ds, reg, 0x3 << bit, ds_val << bit);
342 if (ret)
343 return ret;
344
345 return 0;
346}
347
Guillaume La Roque9959d9a2019-05-14 10:26:50 +0200348static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
349 unsigned long *configs, unsigned num_configs)
350{
351 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
352 enum pin_config_param param;
Jerome Brunetb22a7f82019-05-16 17:13:39 +0200353 unsigned int arg = 0;
Guillaume La Roque9959d9a2019-05-14 10:26:50 +0200354 int i, ret;
355
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100356 for (i = 0; i < num_configs; i++) {
357 param = pinconf_to_config_param(configs[i]);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100358
359 switch (param) {
Jerome Brunetb22a7f82019-05-16 17:13:39 +0200360 case PIN_CONFIG_DRIVE_STRENGTH_UA:
361 case PIN_CONFIG_OUTPUT_ENABLE:
362 case PIN_CONFIG_OUTPUT:
363 arg = pinconf_to_config_argument(configs[i]);
364 break;
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100365
Jerome Brunetb22a7f82019-05-16 17:13:39 +0200366 default:
367 break;
368 }
369
370 switch (param) {
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100371 case PIN_CONFIG_BIAS_DISABLE:
Guillaume La Roque9959d9a2019-05-14 10:26:50 +0200372 ret = meson_pinconf_disable_bias(pc, pin);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100373 break;
374 case PIN_CONFIG_BIAS_PULL_UP:
Guillaume La Roque9959d9a2019-05-14 10:26:50 +0200375 ret = meson_pinconf_enable_bias(pc, pin, true);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100376 break;
377 case PIN_CONFIG_BIAS_PULL_DOWN:
Guillaume La Roque9959d9a2019-05-14 10:26:50 +0200378 ret = meson_pinconf_enable_bias(pc, pin, false);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100379 break;
Guillaume La Roque6ea3e3b2019-05-14 10:26:51 +0200380 case PIN_CONFIG_DRIVE_STRENGTH_UA:
Jerome Brunetb22a7f82019-05-16 17:13:39 +0200381 ret = meson_pinconf_set_drive_strength(pc, pin, arg);
382 break;
383 case PIN_CONFIG_OUTPUT_ENABLE:
384 ret = meson_pinconf_set_output(pc, pin, arg);
385 break;
386 case PIN_CONFIG_OUTPUT:
387 ret = meson_pinconf_set_output_drive(pc, pin, arg);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100388 break;
389 default:
Jerome Brunetb22a7f82019-05-16 17:13:39 +0200390 ret = -ENOTSUPP;
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100391 }
Jerome Brunetb22a7f82019-05-16 17:13:39 +0200392
393 if (ret)
394 return ret;
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100395 }
396
397 return 0;
398}
399
400static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin)
401{
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100402 struct meson_bank *bank;
403 unsigned int reg, bit, val;
404 int ret, conf;
405
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200406 ret = meson_get_bank(pc, pin, &bank);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100407 if (ret)
408 return ret;
409
Andy Shevchenko2b2dce82022-04-01 13:36:00 +0300410 meson_calc_reg_and_bit(bank, pin, MESON_REG_PULLEN, &reg, &bit);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100411
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200412 ret = regmap_read(pc->reg_pullen, reg, &val);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100413 if (ret)
414 return ret;
415
416 if (!(val & BIT(bit))) {
417 conf = PIN_CONFIG_BIAS_DISABLE;
418 } else {
Andy Shevchenko2b2dce82022-04-01 13:36:00 +0300419 meson_calc_reg_and_bit(bank, pin, MESON_REG_PULL, &reg, &bit);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100420
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200421 ret = regmap_read(pc->reg_pull, reg, &val);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100422 if (ret)
423 return ret;
424
425 if (val & BIT(bit))
426 conf = PIN_CONFIG_BIAS_PULL_UP;
427 else
428 conf = PIN_CONFIG_BIAS_PULL_DOWN;
429 }
430
431 return conf;
432}
433
Guillaume La Roque6ea3e3b2019-05-14 10:26:51 +0200434static int meson_pinconf_get_drive_strength(struct meson_pinctrl *pc,
435 unsigned int pin,
436 u16 *drive_strength_ua)
437{
438 struct meson_bank *bank;
439 unsigned int reg, bit;
440 unsigned int val;
441 int ret;
442
443 if (!pc->reg_ds)
444 return -ENOTSUPP;
445
446 ret = meson_get_bank(pc, pin, &bank);
447 if (ret)
448 return ret;
449
Andy Shevchenko2b2dce82022-04-01 13:36:00 +0300450 meson_calc_reg_and_bit(bank, pin, MESON_REG_DS, &reg, &bit);
Guillaume La Roque6ea3e3b2019-05-14 10:26:51 +0200451
452 ret = regmap_read(pc->reg_ds, reg, &val);
453 if (ret)
454 return ret;
455
456 switch ((val >> bit) & 0x3) {
457 case MESON_PINCONF_DRV_500UA:
458 *drive_strength_ua = 500;
459 break;
460 case MESON_PINCONF_DRV_2500UA:
461 *drive_strength_ua = 2500;
462 break;
463 case MESON_PINCONF_DRV_3000UA:
464 *drive_strength_ua = 3000;
465 break;
466 case MESON_PINCONF_DRV_4000UA:
467 *drive_strength_ua = 4000;
468 break;
469 default:
470 return -EINVAL;
471 }
472
473 return 0;
474}
475
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100476static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin,
477 unsigned long *config)
478{
479 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
480 enum pin_config_param param = pinconf_to_config_param(*config);
481 u16 arg;
Guillaume La Roque6ea3e3b2019-05-14 10:26:51 +0200482 int ret;
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100483
484 switch (param) {
485 case PIN_CONFIG_BIAS_DISABLE:
486 case PIN_CONFIG_BIAS_PULL_DOWN:
487 case PIN_CONFIG_BIAS_PULL_UP:
488 if (meson_pinconf_get_pull(pc, pin) == param)
489 arg = 1;
490 else
491 return -EINVAL;
492 break;
Guillaume La Roque6ea3e3b2019-05-14 10:26:51 +0200493 case PIN_CONFIG_DRIVE_STRENGTH_UA:
494 ret = meson_pinconf_get_drive_strength(pc, pin, &arg);
495 if (ret)
496 return ret;
497 break;
Jerome Brunetb22a7f82019-05-16 17:13:39 +0200498 case PIN_CONFIG_OUTPUT_ENABLE:
499 ret = meson_pinconf_get_output(pc, pin);
500 if (ret <= 0)
501 return -EINVAL;
502 arg = 1;
503 break;
504 case PIN_CONFIG_OUTPUT:
505 ret = meson_pinconf_get_output(pc, pin);
506 if (ret <= 0)
507 return -EINVAL;
508
509 ret = meson_pinconf_get_drive(pc, pin);
510 if (ret < 0)
511 return -EINVAL;
512
513 arg = ret;
514 break;
515
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100516 default:
517 return -ENOTSUPP;
518 }
519
520 *config = pinconf_to_config_packed(param, arg);
521 dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config);
522
523 return 0;
524}
525
526static int meson_pinconf_group_set(struct pinctrl_dev *pcdev,
527 unsigned int num_group,
528 unsigned long *configs, unsigned num_configs)
529{
530 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
531 struct meson_pmx_group *group = &pc->data->groups[num_group];
532 int i;
533
534 dev_dbg(pc->dev, "set pinconf for group %s\n", group->name);
535
536 for (i = 0; i < group->num_pins; i++) {
537 meson_pinconf_set(pcdev, group->pins[i], configs,
538 num_configs);
539 }
540
541 return 0;
542}
543
544static int meson_pinconf_group_get(struct pinctrl_dev *pcdev,
545 unsigned int group, unsigned long *config)
546{
Jerome Brunet1ffbf502017-09-20 16:08:15 +0200547 return -ENOTSUPP;
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100548}
549
550static const struct pinconf_ops meson_pinconf_ops = {
551 .pin_config_get = meson_pinconf_get,
552 .pin_config_set = meson_pinconf_set,
553 .pin_config_group_get = meson_pinconf_group_get,
554 .pin_config_group_set = meson_pinconf_group_set,
555 .is_generic = true,
556};
557
Martin Blumenstinglef1d0bc2020-04-17 20:33:48 +0200558static int meson_gpio_get_direction(struct gpio_chip *chip, unsigned gpio)
559{
560 struct meson_pinctrl *pc = gpiochip_get_data(chip);
561 int ret;
562
563 ret = meson_pinconf_get_output(pc, gpio);
564 if (ret < 0)
565 return ret;
566
567 return ret ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
568}
569
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100570static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
571{
Jerome Brunetb22a7f82019-05-16 17:13:39 +0200572 return meson_pinconf_set_output(gpiochip_get_data(chip), gpio, false);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100573}
574
575static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
576 int value)
577{
Jerome Brunetb22a7f82019-05-16 17:13:39 +0200578 return meson_pinconf_set_output_drive(gpiochip_get_data(chip),
579 gpio, value);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100580}
581
582static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
583{
Jerome Brunetb22a7f82019-05-16 17:13:39 +0200584 meson_pinconf_set_drive(gpiochip_get_data(chip), gpio, value);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100585}
586
587static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
588{
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200589 struct meson_pinctrl *pc = gpiochip_get_data(chip);
Jerome Brunet70e5ecb2017-09-20 15:39:25 +0200590 unsigned int reg, bit, val;
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100591 struct meson_bank *bank;
592 int ret;
593
Jerome Brunet70e5ecb2017-09-20 15:39:25 +0200594 ret = meson_get_bank(pc, gpio, &bank);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100595 if (ret)
596 return ret;
597
Andy Shevchenko2b2dce82022-04-01 13:36:00 +0300598 meson_calc_reg_and_bit(bank, gpio, MESON_REG_IN, &reg, &bit);
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200599 regmap_read(pc->reg_gpio, reg, &val);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100600
601 return !!(val & BIT(bit));
602}
603
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100604static int meson_gpiolib_register(struct meson_pinctrl *pc)
605{
Carlo Caione9dab1862016-03-01 23:04:34 +0100606 int ret;
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100607
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200608 pc->chip.label = pc->data->name;
609 pc->chip.parent = pc->dev;
Andy Shevchenko827eb272022-09-05 21:00:34 +0300610 pc->chip.fwnode = pc->fwnode;
Jerome Brunet634e40b2017-09-20 15:39:20 +0200611 pc->chip.request = gpiochip_generic_request;
612 pc->chip.free = gpiochip_generic_free;
Martin Blumenstinglf8f0aa02020-04-17 20:33:49 +0200613 pc->chip.set_config = gpiochip_generic_config;
Martin Blumenstinglef1d0bc2020-04-17 20:33:48 +0200614 pc->chip.get_direction = meson_gpio_get_direction;
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200615 pc->chip.direction_input = meson_gpio_direction_input;
616 pc->chip.direction_output = meson_gpio_direction_output;
617 pc->chip.get = meson_gpio_get;
618 pc->chip.set = meson_gpio_set;
Jerome Brunet634e40b2017-09-20 15:39:20 +0200619 pc->chip.base = -1;
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200620 pc->chip.ngpio = pc->data->num_pins;
621 pc->chip.can_sleep = false;
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100622
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200623 ret = gpiochip_add_data(&pc->chip, pc);
Carlo Caione9dab1862016-03-01 23:04:34 +0100624 if (ret) {
625 dev_err(pc->dev, "can't add gpio chip %s\n",
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200626 pc->data->name);
Neil Armstrongc7fc5fb2017-03-23 17:27:28 +0100627 return ret;
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100628 }
629
630 return 0;
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100631}
632
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100633static struct regmap_config meson_regmap_config = {
634 .reg_bits = 32,
635 .val_bits = 32,
636 .reg_stride = 4,
637};
638
639static struct regmap *meson_map_resource(struct meson_pinctrl *pc,
640 struct device_node *node, char *name)
641{
642 struct resource res;
643 void __iomem *base;
644 int i;
645
646 i = of_property_match_string(node, "reg-names", name);
647 if (of_address_to_resource(node, i, &res))
Qianggui Songfd422962019-11-15 20:03:47 +0800648 return NULL;
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100649
650 base = devm_ioremap_resource(pc->dev, &res);
651 if (IS_ERR(base))
652 return ERR_CAST(base);
653
654 meson_regmap_config.max_register = resource_size(&res) - 4;
655 meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL,
Rob Herring94f4e542018-08-27 20:52:41 -0500656 "%pOFn-%s", node,
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100657 name);
658 if (!meson_regmap_config.name)
659 return ERR_PTR(-ENOMEM);
660
661 return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config);
662}
663
Andy Shevchenkoedc56012022-04-01 13:36:02 +0300664static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc)
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100665{
Andy Shevchenkoedc56012022-04-01 13:36:02 +0300666 struct device_node *gpio_np;
667 unsigned int chips;
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100668
Andy Shevchenkoedc56012022-04-01 13:36:02 +0300669 chips = gpiochip_node_count(pc->dev);
670 if (!chips) {
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200671 dev_err(pc->dev, "no gpio node found\n");
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100672 return -EINVAL;
673 }
Andy Shevchenkoedc56012022-04-01 13:36:02 +0300674 if (chips > 1) {
675 dev_err(pc->dev, "multiple gpio nodes\n");
676 return -EINVAL;
677 }
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100678
Andy Shevchenko827eb272022-09-05 21:00:34 +0300679 pc->fwnode = gpiochip_node_get_first(pc->dev);
680 gpio_np = to_of_node(pc->fwnode);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100681
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200682 pc->reg_mux = meson_map_resource(pc, gpio_np, "mux");
Qianggui Songfd422962019-11-15 20:03:47 +0800683 if (IS_ERR_OR_NULL(pc->reg_mux)) {
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200684 dev_err(pc->dev, "mux registers not found\n");
Qianggui Songfd422962019-11-15 20:03:47 +0800685 return pc->reg_mux ? PTR_ERR(pc->reg_mux) : -ENOENT;
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200686 }
Carlo Caione9dab1862016-03-01 23:04:34 +0100687
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200688 pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
Qianggui Songfd422962019-11-15 20:03:47 +0800689 if (IS_ERR_OR_NULL(pc->reg_gpio)) {
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200690 dev_err(pc->dev, "gpio registers not found\n");
Qianggui Songfd422962019-11-15 20:03:47 +0800691 return pc->reg_gpio ? PTR_ERR(pc->reg_gpio) : -ENOENT;
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100692 }
693
Xingyu Chene66dd482019-01-17 11:23:14 +0100694 pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
Xingyu Chene66dd482019-01-17 11:23:14 +0100695 if (IS_ERR(pc->reg_pull))
Qianggui Songfd422962019-11-15 20:03:47 +0800696 pc->reg_pull = NULL;
Xingyu Chene66dd482019-01-17 11:23:14 +0100697
698 pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable");
Xingyu Chene66dd482019-01-17 11:23:14 +0100699 if (IS_ERR(pc->reg_pullen))
Qianggui Songfd422962019-11-15 20:03:47 +0800700 pc->reg_pullen = NULL;
Xingyu Chene66dd482019-01-17 11:23:14 +0100701
Jerome Brunet64856972019-01-17 11:23:15 +0100702 pc->reg_ds = meson_map_resource(pc, gpio_np, "ds");
703 if (IS_ERR(pc->reg_ds)) {
704 dev_dbg(pc->dev, "ds registers not found - skipping\n");
705 pc->reg_ds = NULL;
706 }
707
Qianggui Songfd422962019-11-15 20:03:47 +0800708 if (pc->data->parse_dt)
709 return pc->data->parse_dt(pc);
710
711 return 0;
712}
713
714int meson8_aobus_parse_dt_extra(struct meson_pinctrl *pc)
715{
716 if (!pc->reg_pull)
717 return -EINVAL;
718
719 pc->reg_pullen = pc->reg_pull;
720
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100721 return 0;
722}
Kevin Hilman9c654412020-10-26 11:30:25 -0700723EXPORT_SYMBOL_GPL(meson8_aobus_parse_dt_extra);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100724
Qianggui Songdabad1f2019-11-15 20:03:48 +0800725int meson_a1_parse_dt_extra(struct meson_pinctrl *pc)
726{
727 pc->reg_pull = pc->reg_gpio;
728 pc->reg_pullen = pc->reg_gpio;
729 pc->reg_ds = pc->reg_gpio;
730
731 return 0;
732}
Kevin Hilman9c654412020-10-26 11:30:25 -0700733EXPORT_SYMBOL_GPL(meson_a1_parse_dt_extra);
Qianggui Songdabad1f2019-11-15 20:03:48 +0800734
Jerome Brunet277d14e2017-10-12 14:40:25 +0200735int meson_pinctrl_probe(struct platform_device *pdev)
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100736{
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100737 struct device *dev = &pdev->dev;
738 struct meson_pinctrl *pc;
739 int ret;
740
741 pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL);
742 if (!pc)
743 return -ENOMEM;
744
745 pc->dev = dev;
Jerome Brunet277d14e2017-10-12 14:40:25 +0200746 pc->data = (struct meson_pinctrl_data *) of_device_get_match_data(dev);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100747
Andy Shevchenkoedc56012022-04-01 13:36:02 +0300748 ret = meson_pinctrl_parse_dt(pc);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100749 if (ret)
750 return ret;
751
752 pc->desc.name = "pinctrl-meson";
753 pc->desc.owner = THIS_MODULE;
754 pc->desc.pctlops = &meson_pctrl_ops;
Jerome Brunetce385aa2017-10-12 14:40:26 +0200755 pc->desc.pmxops = pc->data->pmx_ops;
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100756 pc->desc.confops = &meson_pinconf_ops;
757 pc->desc.pins = pc->data->pins;
758 pc->desc.npins = pc->data->num_pins;
759
Laxman Dewangane649f7e2016-02-24 14:44:07 +0530760 pc->pcdev = devm_pinctrl_register(pc->dev, &pc->desc, pc);
Masahiro Yamada323de9e2015-06-09 13:01:16 +0900761 if (IS_ERR(pc->pcdev)) {
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100762 dev_err(pc->dev, "can't register pinctrl device");
Masahiro Yamada323de9e2015-06-09 13:01:16 +0900763 return PTR_ERR(pc->pcdev);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100764 }
765
Wei Yongjun5b236d02016-07-26 14:51:58 +0000766 return meson_gpiolib_register(pc);
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100767}
Kevin Hilman9c654412020-10-26 11:30:25 -0700768EXPORT_SYMBOL_GPL(meson_pinctrl_probe);
769
770MODULE_LICENSE("GPL v2");