blob: dfd908630631a30851a8f573e41dbe8b21af5f19 [file] [log] [blame]
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001config ARM64
2 def_bool y
Suthikulpanit, Suraveeb6197b92015-06-10 11:08:53 -05003 select ACPI_CCA_REQUIRED if ACPI
Lorenzo Pieralisid8f4f162015-03-24 17:58:51 +00004 select ACPI_GENERIC_GSI if ACPI
Fu Wei5f1ae4e2017-04-01 01:51:01 +08005 select ACPI_GTDT if ACPI
Lorenzo Pieralisic6bb8f892017-06-14 17:37:12 +01006 select ACPI_IORT if ACPI
Al Stone6933de02015-03-24 14:02:51 +00007 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
Tomasz Nowicki0cb07862016-06-10 21:55:19 +02008 select ACPI_MCFG if ACPI
Aleksey Makarov888125a2016-09-27 23:54:14 +03009 select ACPI_SPCR_TABLE if ACPI
Scott Wood1d8f51d2016-09-22 03:35:18 -050010 select ARCH_CLOCKSOURCE_DATA
Laura Abbottec6d06e2017-01-10 13:35:50 -080011 select ARCH_HAS_DEBUG_VIRTUAL
Dan Williams21266be2015-11-19 18:19:29 -080012 select ARCH_HAS_DEVMEM_IS_ALLOWED
Jon Masters38b04a72016-06-20 13:56:13 +030013 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
Kees Cook2b68f6c2015-04-14 15:48:00 -070014 select ARCH_HAS_ELF_RANDOMIZE
Daniel Micay6974f0c2017-07-12 14:36:10 -070015 select ARCH_HAS_FORTIFY_SOURCE
Riku Voipio957e3fa2014-12-12 16:57:44 -080016 select ARCH_HAS_GCOV_PROFILE_ALL
Aneesh Kumar K.Ve1073d12017-07-06 15:39:17 -070017 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
Alexander Potapenko5e4c7542016-06-16 18:39:52 +020018 select ARCH_HAS_KCOV
Daniel Borkmannd2852a22017-02-21 16:09:33 +010019 select ARCH_HAS_SET_MEMORY
Laura Abbott308c09f2014-08-08 14:23:25 -070020 select ARCH_HAS_SG_CHAIN
Laura Abbottad21fc42017-02-06 16:31:57 -080021 select ARCH_HAS_STRICT_KERNEL_RWX
22 select ARCH_HAS_STRICT_MODULE_RWX
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +010023 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
Tyler Baicar7edda082017-06-21 12:17:09 -060024 select ARCH_HAVE_NMI_SAFE_CMPXCHG if ACPI_APEI_SEA
Sudeep Hollac63c8702014-05-09 10:33:01 +010025 select ARCH_USE_CMPXCHG_LOCKREF
Jonathan (Zhixiong) Zhangc484f252017-06-08 18:25:29 +010026 select ARCH_SUPPORTS_MEMORY_FAILURE
Peter Zijlstra4badad32014-06-06 19:53:16 +020027 select ARCH_SUPPORTS_ATOMIC_RMW
Ganapatrao Kulkarni56166232016-04-08 15:50:28 -070028 select ARCH_SUPPORTS_NUMA_BALANCING
Will Deacon6212a512012-11-07 14:16:28 +000029 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
Catalin Marinasb6f35982013-01-29 18:25:41 +000030 select ARCH_WANT_FRAME_POINTERS
Yang Shif0b7f8a42016-02-05 15:50:18 -080031 select ARCH_HAS_UBSAN_SANITIZE_ALL
Catalin Marinas25c92a32012-12-18 15:26:13 +000032 select ARM_AMBA
Mark Rutland1aee5d72012-11-20 10:06:00 +000033 select ARM_ARCH_TIMER
Catalin Marinasc4188ed2013-01-14 12:39:31 +000034 select ARM_GIC
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010035 select AUDIT_ARCH_COMPAT_GENERIC
Arnd Bergmann3ee803642016-06-15 15:47:33 -050036 select ARM_GIC_V2M if PCI
Marc Zyngier021f6532014-06-30 16:01:31 +010037 select ARM_GIC_V3
Arnd Bergmann3ee803642016-06-15 15:47:33 -050038 select ARM_GIC_V3_ITS if PCI
Mark Rutlandbff607922015-07-31 15:46:16 +010039 select ARM_PSCI_FW
Will Deaconadace892013-05-08 17:29:24 +010040 select BUILDTIME_EXTABLE_SORT
Catalin Marinasdb2789b2012-12-18 15:27:25 +000041 select CLONE_BACKWARDS
Deepak Saxena7ca2ef33e2012-09-22 10:33:36 -070042 select COMMON_CLK
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +000043 select CPU_PM if (SUSPEND || CPU_IDLE)
Will Deacon7bc13fd2013-11-06 19:32:13 +000044 select DCACHE_WORD_ACCESS
Catalin Marinasef375662015-07-07 17:15:39 +010045 select EDAC_SUPPORT
Yang Shi2f34f172015-11-09 10:09:55 -080046 select FRAME_POINTER
Laura Abbottd4932f92014-10-09 15:26:44 -070047 select GENERIC_ALLOCATOR
Juri Lelli2ef7a292017-05-31 17:59:28 +010048 select GENERIC_ARCH_TOPOLOGY
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010049 select GENERIC_CLOCKEVENTS
Will Deacon4b3dc962015-05-29 18:28:44 +010050 select GENERIC_CLOCKEVENTS_BROADCAST
Ard Biesheuvel3be1a5c2014-03-04 01:10:04 +000051 select GENERIC_CPU_AUTOPROBE
Mark Salterbf4b5582014-04-07 15:39:52 -070052 select GENERIC_EARLY_IOREMAP
Leo Yan2314ee42015-08-21 04:40:22 +010053 select GENERIC_IDLE_POLL_SETUP
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010054 select GENERIC_IRQ_PROBE
55 select GENERIC_IRQ_SHOW
Sudeep Holla6544e672015-04-22 18:16:33 +010056 select GENERIC_IRQ_SHOW_LEVEL
Arnd Bergmanncb61f672014-11-19 14:09:07 +010057 select GENERIC_PCI_IOMAP
Stephen Boyd65cd4f62013-07-18 16:21:18 -070058 select GENERIC_SCHED_CLOCK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010059 select GENERIC_SMP_IDLE_THREAD
Will Deacon12a0ef72013-11-06 17:20:22 +000060 select GENERIC_STRNCPY_FROM_USER
61 select GENERIC_STRNLEN_USER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010062 select GENERIC_TIME_VSYSCALL
Marc Zyngiera1ddc742014-08-26 11:03:17 +010063 select HANDLE_DOMAIN_IRQ
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010064 select HARDIRQS_SW_RESEND
Tomasz Nowicki9f9a35a2016-12-01 21:51:12 +080065 select HAVE_ACPI_APEI if (ACPI && EFI)
Steve Capper5284e1b2014-10-24 13:22:20 +010066 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010067 select HAVE_ARCH_AUDITSYSCALL
Yalin Wang8e7a4ce2014-11-03 03:02:23 +010068 select HAVE_ARCH_BITREVERSE
Ard Biesheuvel324420b2016-02-16 13:52:35 +010069 select HAVE_ARCH_HUGE_VMAP
Jiang Liu9732caf2014-01-07 22:17:13 +080070 select HAVE_ARCH_JUMP_LABEL
Andrey Ryabininf1b90322015-11-17 18:47:08 +030071 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
Vijaya Kumar K95292472014-01-28 11:20:22 +000072 select HAVE_ARCH_KGDB
Daniel Cashman8f0d3aa2016-01-14 15:20:01 -080073 select HAVE_ARCH_MMAP_RND_BITS
74 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +000075 select HAVE_ARCH_SECCOMP_FILTER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010076 select HAVE_ARCH_TRACEHOOK
Yang Shi8ee70872016-04-18 11:16:14 -070077 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
78 select HAVE_ARM_SMCCC
Daniel Borkmann60777762016-05-13 19:08:28 +020079 select HAVE_EBPF_JIT
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010080 select HAVE_C_RECORDMCOUNT
Laura Abbottc0c264a2014-06-25 23:55:03 +010081 select HAVE_CC_STACKPROTECTOR
Steve Capper5284e1b2014-10-24 13:22:20 +010082 select HAVE_CMPXCHG_DOUBLE
Will Deacon95eff6b2015-05-29 14:57:47 +010083 select HAVE_CMPXCHG_LOCAL
Yang Shi8ee70872016-04-18 11:16:14 -070084 select HAVE_CONTEXT_TRACKING
Catalin Marinas9b2a60c2012-10-08 16:28:13 -070085 select HAVE_DEBUG_BUGVERBOSE
Catalin Marinasb69ec422012-10-08 16:28:11 -070086 select HAVE_DEBUG_KMEMLEAK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010087 select HAVE_DMA_API_DEBUG
Laura Abbott6ac21042013-12-12 19:28:33 +000088 select HAVE_DMA_CONTIGUOUS
AKASHI Takahirobd7d38d2014-04-30 10:54:34 +010089 select HAVE_DYNAMIC_FTRACE
Will Deacon50afc332013-12-16 17:50:08 +000090 select HAVE_EFFICIENT_UNALIGNED_ACCESS
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010091 select HAVE_FTRACE_MCOUNT_RECORD
AKASHI Takahiro819e50e2014-04-30 18:54:33 +090092 select HAVE_FUNCTION_TRACER
93 select HAVE_FUNCTION_GRAPH_TRACER
Emese Revfy6b90bd42016-05-24 00:09:38 +020094 select HAVE_GCC_PLUGINS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010095 select HAVE_GENERIC_DMA_COHERENT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010096 select HAVE_HW_BREAKPOINT if PERF_EVENTS
Will Deacon24da2082015-11-23 15:12:59 +000097 select HAVE_IRQ_TIME_ACCOUNTING
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010098 select HAVE_MEMBLOCK
Ganapatrao Kulkarni1a2db302016-04-08 15:50:27 -070099 select HAVE_MEMBLOCK_NODE_MAP if NUMA
Tyler Baicar7edda082017-06-21 12:17:09 -0600100 select HAVE_NMI if ACPI_APEI_SEA
Mark Rutland55834a72014-02-07 17:12:45 +0000101 select HAVE_PATA_PLATFORM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100102 select HAVE_PERF_EVENTS
Jean Pihet2ee0d7f2014-02-03 19:18:27 +0100103 select HAVE_PERF_REGS
104 select HAVE_PERF_USER_STACK_DUMP
David A. Long0a8ea522016-07-08 12:35:45 -0400105 select HAVE_REGS_AND_STACK_ACCESS_API
Steve Capper5e5f6dc2014-10-09 15:29:23 -0700106 select HAVE_RCU_TABLE_FREE
AKASHI Takahiro055b1212014-04-30 10:54:36 +0100107 select HAVE_SYSCALL_TRACEPOINTS
Sandeepa Prabhu2dd0e8d2016-07-08 12:35:48 -0400108 select HAVE_KPROBES
Masami Hiramatsucd1ee3b2017-02-06 18:54:33 +0900109 select HAVE_KRETPROBES
Robin Murphy876945d2015-10-01 20:14:00 +0100110 select IOMMU_DMA if IOMMU_SUPPORT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100111 select IRQ_DOMAIN
Anders Roxelle8557d12015-04-27 22:53:09 +0200112 select IRQ_FORCED_THREADING
Catalin Marinasfea2aca2012-10-16 11:26:57 +0100113 select MODULES_USE_ELF_RELA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100114 select NO_BOOTMEM
115 select OF
116 select OF_EARLY_FLATTREE
Marek Szyprowski9bf14b72014-02-28 14:42:55 +0100117 select OF_RESERVED_MEM
Tomasz Nowicki0cb07862016-06-10 21:55:19 +0200118 select PCI_ECAM if ACPI
Catalin Marinasaa1e8ec12013-02-28 18:14:37 +0000119 select POWER_RESET
120 select POWER_SUPPLY
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100121 select SPARSE_IRQ
Catalin Marinas7ac57a82012-10-08 16:28:16 -0700122 select SYSCTL_EXCEPTION_TRACE
Mark Rutlandc02433d2016-11-03 20:23:13 +0000123 select THREAD_INFO_IN_TASK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100124 help
125 ARM 64-bit (AArch64) Linux support.
126
127config 64BIT
128 def_bool y
129
130config ARCH_PHYS_ADDR_T_64BIT
131 def_bool y
132
133config MMU
134 def_bool y
135
Mark Rutland030c4d22016-05-31 15:57:59 +0100136config ARM64_PAGE_SHIFT
137 int
138 default 16 if ARM64_64K_PAGES
139 default 14 if ARM64_16K_PAGES
140 default 12
141
142config ARM64_CONT_SHIFT
143 int
144 default 5 if ARM64_64K_PAGES
145 default 7 if ARM64_16K_PAGES
146 default 4
147
Daniel Cashman8f0d3aa2016-01-14 15:20:01 -0800148config ARCH_MMAP_RND_BITS_MIN
149 default 14 if ARM64_64K_PAGES
150 default 16 if ARM64_16K_PAGES
151 default 18
152
153# max bits determined by the following formula:
154# VA_BITS - PAGE_SHIFT - 3
155config ARCH_MMAP_RND_BITS_MAX
156 default 19 if ARM64_VA_BITS=36
157 default 24 if ARM64_VA_BITS=39
158 default 27 if ARM64_VA_BITS=42
159 default 30 if ARM64_VA_BITS=47
160 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
161 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
162 default 33 if ARM64_VA_BITS=48
163 default 14 if ARM64_64K_PAGES
164 default 16 if ARM64_16K_PAGES
165 default 18
166
167config ARCH_MMAP_RND_COMPAT_BITS_MIN
168 default 7 if ARM64_64K_PAGES
169 default 9 if ARM64_16K_PAGES
170 default 11
171
172config ARCH_MMAP_RND_COMPAT_BITS_MAX
173 default 16
174
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -0700175config NO_IOPORT_MAP
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100176 def_bool y if !PCI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100177
178config STACKTRACE_SUPPORT
179 def_bool y
180
Jeff Vander Stoepbf0c4e02015-08-18 20:50:10 +0100181config ILLEGAL_POINTER_VALUE
182 hex
183 default 0xdead000000000000
184
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100185config LOCKDEP_SUPPORT
186 def_bool y
187
188config TRACE_IRQFLAGS_SUPPORT
189 def_bool y
190
Will Deaconc209f792014-03-14 17:47:05 +0000191config RWSEM_XCHGADD_ALGORITHM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100192 def_bool y
193
Dave P Martin9fb74102015-07-24 16:37:48 +0100194config GENERIC_BUG
195 def_bool y
196 depends on BUG
197
198config GENERIC_BUG_RELATIVE_POINTERS
199 def_bool y
200 depends on GENERIC_BUG
201
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100202config GENERIC_HWEIGHT
203 def_bool y
204
205config GENERIC_CSUM
206 def_bool y
207
208config GENERIC_CALIBRATE_DELAY
209 def_bool y
210
Catalin Marinas19e76402014-02-27 12:09:22 +0000211config ZONE_DMA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100212 def_bool y
213
Kirill A. Shutemove5855132017-06-06 14:31:20 +0300214config HAVE_GENERIC_GUP
Steve Capper29e56942014-10-09 15:29:25 -0700215 def_bool y
216
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100217config ARCH_DMA_ADDR_T_64BIT
218 def_bool y
219
220config NEED_DMA_MAP_STATE
221 def_bool y
222
223config NEED_SG_DMA_LENGTH
224 def_bool y
225
Will Deacon4b3dc962015-05-29 18:28:44 +0100226config SMP
227 def_bool y
228
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100229config SWIOTLB
230 def_bool y
231
232config IOMMU_HELPER
233 def_bool SWIOTLB
234
Ard Biesheuvel4cfb3612013-07-09 14:18:12 +0100235config KERNEL_MODE_NEON
236 def_bool y
237
Rob Herring92cc15f2014-04-18 17:19:59 -0500238config FIX_EARLYCON_MEM
239 def_bool y
240
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700241config PGTABLE_LEVELS
242 int
Suzuki K. Poulose21539932015-10-19 14:19:38 +0100243 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700244 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
245 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
246 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100247 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
248 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700249
Pratyush Anand9842cea2016-11-02 14:40:46 +0530250config ARCH_SUPPORTS_UPROBES
251 def_bool y
252
Ard Biesheuvel8f360942017-06-14 12:43:55 +0200253config ARCH_PROC_KCORE_TEXT
254 def_bool y
255
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100256source "init/Kconfig"
257
258source "kernel/Kconfig.freezer"
259
Olof Johansson6a377492015-07-20 12:09:16 -0700260source "arch/arm64/Kconfig.platforms"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100261
262menu "Bus support"
263
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100264config PCI
265 bool "PCI support"
266 help
267 This feature enables support for PCI bus system. If you say Y
268 here, the kernel will include drivers and infrastructure code
269 to support PCI bus devices.
270
271config PCI_DOMAINS
272 def_bool PCI
273
274config PCI_DOMAINS_GENERIC
275 def_bool PCI
276
277config PCI_SYSCALL
278 def_bool PCI
279
280source "drivers/pci/Kconfig"
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100281
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100282endmenu
283
284menu "Kernel Features"
285
Andre Przywarac0a01b82014-11-14 15:54:12 +0000286menu "ARM errata workarounds via the alternatives framework"
287
288config ARM64_ERRATUM_826319
289 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
290 default y
291 help
292 This option adds an alternative code sequence to work around ARM
293 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
294 AXI master interface and an L2 cache.
295
296 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
297 and is unable to accept a certain write via this interface, it will
298 not progress on read data presented on the read data channel and the
299 system can deadlock.
300
301 The workaround promotes data cache clean instructions to
302 data cache clean-and-invalidate.
303 Please note that this does not necessarily enable the workaround,
304 as it depends on the alternative framework, which will only patch
305 the kernel if an affected CPU is detected.
306
307 If unsure, say Y.
308
309config ARM64_ERRATUM_827319
310 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
311 default y
312 help
313 This option adds an alternative code sequence to work around ARM
314 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
315 master interface and an L2 cache.
316
317 Under certain conditions this erratum can cause a clean line eviction
318 to occur at the same time as another transaction to the same address
319 on the AMBA 5 CHI interface, which can cause data corruption if the
320 interconnect reorders the two transactions.
321
322 The workaround promotes data cache clean instructions to
323 data cache clean-and-invalidate.
324 Please note that this does not necessarily enable the workaround,
325 as it depends on the alternative framework, which will only patch
326 the kernel if an affected CPU is detected.
327
328 If unsure, say Y.
329
330config ARM64_ERRATUM_824069
331 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
332 default y
333 help
334 This option adds an alternative code sequence to work around ARM
335 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
336 to a coherent interconnect.
337
338 If a Cortex-A53 processor is executing a store or prefetch for
339 write instruction at the same time as a processor in another
340 cluster is executing a cache maintenance operation to the same
341 address, then this erratum might cause a clean cache line to be
342 incorrectly marked as dirty.
343
344 The workaround promotes data cache clean instructions to
345 data cache clean-and-invalidate.
346 Please note that this option does not necessarily enable the
347 workaround, as it depends on the alternative framework, which will
348 only patch the kernel if an affected CPU is detected.
349
350 If unsure, say Y.
351
352config ARM64_ERRATUM_819472
353 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
354 default y
355 help
356 This option adds an alternative code sequence to work around ARM
357 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
358 present when it is connected to a coherent interconnect.
359
360 If the processor is executing a load and store exclusive sequence at
361 the same time as a processor in another cluster is executing a cache
362 maintenance operation to the same address, then this erratum might
363 cause data corruption.
364
365 The workaround promotes data cache clean instructions to
366 data cache clean-and-invalidate.
367 Please note that this does not necessarily enable the workaround,
368 as it depends on the alternative framework, which will only patch
369 the kernel if an affected CPU is detected.
370
371 If unsure, say Y.
372
373config ARM64_ERRATUM_832075
374 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
375 default y
376 help
377 This option adds an alternative code sequence to work around ARM
378 erratum 832075 on Cortex-A57 parts up to r1p2.
379
380 Affected Cortex-A57 parts might deadlock when exclusive load/store
381 instructions to Write-Back memory are mixed with Device loads.
382
383 The workaround is to promote device loads to use Load-Acquire
384 semantics.
385 Please note that this does not necessarily enable the workaround,
386 as it depends on the alternative framework, which will only patch
387 the kernel if an affected CPU is detected.
388
389 If unsure, say Y.
390
Marc Zyngier498cd5c2015-11-16 10:28:18 +0000391config ARM64_ERRATUM_834220
392 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
393 depends on KVM
394 default y
395 help
396 This option adds an alternative code sequence to work around ARM
397 erratum 834220 on Cortex-A57 parts up to r1p2.
398
399 Affected Cortex-A57 parts might report a Stage 2 translation
400 fault as the result of a Stage 1 fault for load crossing a
401 page boundary when there is a permission or device memory
402 alignment fault at Stage 1 and a translation fault at Stage 2.
403
404 The workaround is to verify that the Stage 1 translation
405 doesn't generate a fault before handling the Stage 2 fault.
406 Please note that this does not necessarily enable the workaround,
407 as it depends on the alternative framework, which will only patch
408 the kernel if an affected CPU is detected.
409
410 If unsure, say Y.
411
Will Deacon905e8c52015-03-23 19:07:02 +0000412config ARM64_ERRATUM_845719
413 bool "Cortex-A53: 845719: a load might read incorrect data"
414 depends on COMPAT
415 default y
416 help
417 This option adds an alternative code sequence to work around ARM
418 erratum 845719 on Cortex-A53 parts up to r0p4.
419
420 When running a compat (AArch32) userspace on an affected Cortex-A53
421 part, a load at EL0 from a virtual address that matches the bottom 32
422 bits of the virtual address used by a recent load at (AArch64) EL1
423 might return incorrect data.
424
425 The workaround is to write the contextidr_el1 register on exception
426 return to a 32-bit task.
427 Please note that this does not necessarily enable the workaround,
428 as it depends on the alternative framework, which will only patch
429 the kernel if an affected CPU is detected.
430
431 If unsure, say Y.
432
Will Deacondf057cc2015-03-17 12:15:02 +0000433config ARM64_ERRATUM_843419
434 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
Will Deacondf057cc2015-03-17 12:15:02 +0000435 default y
Will Deacon6ffe9922016-08-22 11:58:36 +0100436 select ARM64_MODULE_CMODEL_LARGE if MODULES
Will Deacondf057cc2015-03-17 12:15:02 +0000437 help
Will Deacon6ffe9922016-08-22 11:58:36 +0100438 This option links the kernel with '--fix-cortex-a53-843419' and
439 builds modules using the large memory model in order to avoid the use
440 of the ADRP instruction, which can cause a subsequent memory access
441 to use an incorrect address on Cortex-A53 parts up to r0p4.
Will Deacondf057cc2015-03-17 12:15:02 +0000442
443 If unsure, say Y.
444
Robert Richter94100972015-09-21 22:58:38 +0200445config CAVIUM_ERRATUM_22375
446 bool "Cavium erratum 22375, 24313"
447 default y
448 help
449 Enable workaround for erratum 22375, 24313.
450
451 This implements two gicv3-its errata workarounds for ThunderX. Both
452 with small impact affecting only ITS table allocation.
453
454 erratum 22375: only alloc 8MB table size
455 erratum 24313: ignore memory access type
456
457 The fixes are in ITS initialization and basically ignore memory access
458 type and table size provided by the TYPER and BASER registers.
459
460 If unsure, say Y.
461
Ganapatrao Kulkarnifbf8f402016-05-25 15:29:20 +0200462config CAVIUM_ERRATUM_23144
463 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
464 depends on NUMA
465 default y
466 help
467 ITS SYNC command hang for cross node io and collections/cpu mapping.
468
469 If unsure, say Y.
470
Robert Richter6d4e11c2015-09-21 22:58:35 +0200471config CAVIUM_ERRATUM_23154
472 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
473 default y
474 help
475 The gicv3 of ThunderX requires a modified version for
476 reading the IAR status to ensure data synchronization
477 (access to icc_iar1_el1 is not sync'ed before and after).
478
479 If unsure, say Y.
480
Andrew Pinski104a0c02016-02-24 17:44:57 -0800481config CAVIUM_ERRATUM_27456
482 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
483 default y
484 help
485 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
486 instructions may cause the icache to become corrupted if it
487 contains data for a non-current ASID. The fix is to
488 invalidate the icache when changing the mm context.
489
490 If unsure, say Y.
491
David Daney690a3412017-06-09 12:49:48 +0100492config CAVIUM_ERRATUM_30115
493 bool "Cavium erratum 30115: Guest may disable interrupts in host"
494 default y
495 help
496 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
497 1.2, and T83 Pass 1.0, KVM guest execution may disable
498 interrupts in host. Trapping both GICv3 group-0 and group-1
499 accesses sidesteps the issue.
500
501 If unsure, say Y.
502
Christopher Covington38fd94b2017-02-08 15:08:37 -0500503config QCOM_FALKOR_ERRATUM_1003
504 bool "Falkor E1003: Incorrect translation due to ASID change"
505 default y
506 select ARM64_PAN if ARM64_SW_TTBR0_PAN
507 help
508 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
509 and BADDR are changed together in TTBRx_EL1. The workaround for this
510 issue is to use a reserved ASID in cpu_do_switch_mm() before
511 switching to the new ASID. Saying Y here selects ARM64_PAN if
512 ARM64_SW_TTBR0_PAN is selected. This is done because implementing and
513 maintaining the E1003 workaround in the software PAN emulation code
514 would be an unnecessary complication. The affected Falkor v1 CPU
515 implements ARMv8.1 hardware PAN support and using hardware PAN
516 support versus software PAN emulation is mutually exclusive at
517 runtime.
518
519 If unsure, say Y.
520
Christopher Covingtond9ff80f2017-01-31 12:50:19 -0500521config QCOM_FALKOR_ERRATUM_1009
522 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
523 default y
524 help
525 On Falkor v1, the CPU may prematurely complete a DSB following a
526 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
527 one more time to fix the issue.
528
529 If unsure, say Y.
530
Shanker Donthineni90922a22017-03-07 08:20:38 -0600531config QCOM_QDF2400_ERRATUM_0065
532 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
533 default y
534 help
535 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
536 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
537 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
538
539 If unsure, say Y.
540
Andre Przywarac0a01b82014-11-14 15:54:12 +0000541endmenu
542
543
Jungseok Leee41ceed2014-05-12 10:40:38 +0100544choice
545 prompt "Page size"
546 default ARM64_4K_PAGES
547 help
548 Page size (translation granule) configuration.
549
550config ARM64_4K_PAGES
551 bool "4KB"
552 help
553 This feature enables 4KB pages support.
554
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100555config ARM64_16K_PAGES
556 bool "16KB"
557 help
558 The system will use 16KB pages support. AArch32 emulation
559 requires applications compiled with 16K (or a multiple of 16K)
560 aligned segments.
561
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100562config ARM64_64K_PAGES
Jungseok Leee41ceed2014-05-12 10:40:38 +0100563 bool "64KB"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100564 help
565 This feature enables 64KB pages support (4KB by default)
566 allowing only two levels of page tables and faster TLB
Suzuki K. Poulosedb488be2015-10-19 14:19:34 +0100567 look-up. AArch32 emulation requires applications compiled
568 with 64K aligned segments.
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100569
Jungseok Leee41ceed2014-05-12 10:40:38 +0100570endchoice
571
572choice
573 prompt "Virtual address space size"
574 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100575 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
Jungseok Leee41ceed2014-05-12 10:40:38 +0100576 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
577 help
578 Allows choosing one of multiple possible virtual address
579 space sizes. The level of translation table is determined by
580 a combination of page size and virtual address space size.
581
Suzuki K. Poulose21539932015-10-19 14:19:38 +0100582config ARM64_VA_BITS_36
Catalin Marinas56a3f302015-10-20 14:59:20 +0100583 bool "36-bit" if EXPERT
Suzuki K. Poulose21539932015-10-19 14:19:38 +0100584 depends on ARM64_16K_PAGES
585
Jungseok Leee41ceed2014-05-12 10:40:38 +0100586config ARM64_VA_BITS_39
587 bool "39-bit"
588 depends on ARM64_4K_PAGES
589
590config ARM64_VA_BITS_42
591 bool "42-bit"
592 depends on ARM64_64K_PAGES
593
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100594config ARM64_VA_BITS_47
595 bool "47-bit"
596 depends on ARM64_16K_PAGES
597
Jungseok Leec79b954b2014-05-12 18:40:51 +0900598config ARM64_VA_BITS_48
599 bool "48-bit"
Jungseok Leec79b954b2014-05-12 18:40:51 +0900600
Jungseok Leee41ceed2014-05-12 10:40:38 +0100601endchoice
602
603config ARM64_VA_BITS
604 int
Suzuki K. Poulose21539932015-10-19 14:19:38 +0100605 default 36 if ARM64_VA_BITS_36
Jungseok Leee41ceed2014-05-12 10:40:38 +0100606 default 39 if ARM64_VA_BITS_39
607 default 42 if ARM64_VA_BITS_42
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100608 default 47 if ARM64_VA_BITS_47
Jungseok Leec79b954b2014-05-12 18:40:51 +0900609 default 48 if ARM64_VA_BITS_48
Jungseok Leee41ceed2014-05-12 10:40:38 +0100610
Will Deacona8720132013-10-11 14:52:19 +0100611config CPU_BIG_ENDIAN
612 bool "Build big-endian kernel"
613 help
614 Say Y if you plan on running a kernel in big-endian mode.
615
Mark Brownf6e763b2014-03-04 07:51:17 +0000616config SCHED_MC
617 bool "Multi-core scheduler support"
Mark Brownf6e763b2014-03-04 07:51:17 +0000618 help
619 Multi-core scheduler support improves the CPU scheduler's decision
620 making when dealing with multi-core CPU chips at a cost of slightly
621 increased overhead in some places. If unsure say N here.
622
623config SCHED_SMT
624 bool "SMT scheduler support"
Mark Brownf6e763b2014-03-04 07:51:17 +0000625 help
626 Improves the CPU scheduler's decision making when dealing with
627 MultiThreading at a cost of slightly increased overhead in some
628 places. If unsure say N here.
629
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100630config NR_CPUS
Ganapatrao Kulkarni62aa9652015-03-18 11:01:18 +0000631 int "Maximum number of CPUs (2-4096)"
632 range 2 4096
Vinayak Kale15942852013-04-24 10:06:57 +0100633 # These have to remain sorted largest to smallest
Robert Richtere3672642014-09-08 12:44:48 +0100634 default "64"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100635
Mark Rutland9327e2c2013-10-24 20:30:18 +0100636config HOTPLUG_CPU
637 bool "Support for hot-pluggable CPUs"
Yang Yingliang217d4532015-09-24 17:32:14 +0800638 select GENERIC_IRQ_MIGRATION
Mark Rutland9327e2c2013-10-24 20:30:18 +0100639 help
640 Say Y here to experiment with turning CPUs off and on. CPUs
641 can be controlled through /sys/devices/system/cpu.
642
Ganapatrao Kulkarni1a2db302016-04-08 15:50:27 -0700643# Common NUMA Features
644config NUMA
645 bool "Numa Memory Allocation and Scheduler Support"
Kefeng Wang0c2a6cc2016-09-26 15:36:50 +0800646 select ACPI_NUMA if ACPI
647 select OF_NUMA
Ganapatrao Kulkarni1a2db302016-04-08 15:50:27 -0700648 help
649 Enable NUMA (Non Uniform Memory Access) support.
650
651 The kernel will try to allocate memory used by a CPU on the
652 local memory of the CPU and add some more
653 NUMA awareness to the kernel.
654
655config NODES_SHIFT
656 int "Maximum NUMA Nodes (as a power of 2)"
657 range 1 10
658 default "2"
659 depends on NEED_MULTIPLE_NODES
660 help
661 Specify the maximum number of NUMA Nodes available on the target
662 system. Increases memory reserved to accommodate various tables.
663
664config USE_PERCPU_NUMA_NODE_ID
665 def_bool y
666 depends on NUMA
667
Zhen Lei7af3a0a2016-09-01 14:55:00 +0800668config HAVE_SETUP_PER_CPU_AREA
669 def_bool y
670 depends on NUMA
671
672config NEED_PER_CPU_EMBED_FIRST_CHUNK
673 def_bool y
674 depends on NUMA
675
Ard Biesheuvel6d526ee22016-12-14 09:11:47 +0000676config HOLES_IN_ZONE
677 def_bool y
678 depends on NUMA
679
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100680source kernel/Kconfig.preempt
Kefeng Wangf90df5e2015-10-26 11:48:16 +0800681source kernel/Kconfig.hz
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100682
Laura Abbott83863f22016-02-05 16:24:47 -0800683config ARCH_SUPPORTS_DEBUG_PAGEALLOC
684 def_bool y
685
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100686config ARCH_HAS_HOLES_MEMORYMODEL
687 def_bool y if SPARSEMEM
688
689config ARCH_SPARSEMEM_ENABLE
690 def_bool y
691 select SPARSEMEM_VMEMMAP_ENABLE
692
693config ARCH_SPARSEMEM_DEFAULT
694 def_bool ARCH_SPARSEMEM_ENABLE
695
696config ARCH_SELECT_MEMORY_MODEL
697 def_bool ARCH_SPARSEMEM_ENABLE
698
699config HAVE_ARCH_PFN_VALID
700 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
701
702config HW_PERF_EVENTS
Mark Rutland6475b2d2015-10-02 10:55:03 +0100703 def_bool y
704 depends on ARM_PMU
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100705
Steve Capper084bd292013-04-10 13:48:00 +0100706config SYS_SUPPORTS_HUGETLBFS
707 def_bool y
708
Steve Capper084bd292013-04-10 13:48:00 +0100709config ARCH_WANT_HUGE_PMD_SHARE
Suzuki K. Poulose21539932015-10-19 14:19:38 +0100710 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
Steve Capper084bd292013-04-10 13:48:00 +0100711
Catalin Marinasa41dc0e2014-04-03 17:48:54 +0100712config ARCH_HAS_CACHE_LINE_SIZE
713 def_bool y
714
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100715source "mm/Kconfig"
716
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +0000717config SECCOMP
718 bool "Enable seccomp to safely compute untrusted bytecode"
719 ---help---
720 This kernel feature is useful for number crunching applications
721 that may need to compute untrusted bytecode during their
722 execution. By using pipes or other transports made available to
723 the process as file descriptors supporting the read/write
724 syscalls, it's possible to isolate those applications in
725 their own address space using seccomp. Once seccomp is
726 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
727 and the task is only allowed to execute a few safe syscalls
728 defined by each seccomp mode.
729
Stefano Stabellinidfd57bc2015-11-23 10:33:49 +0000730config PARAVIRT
731 bool "Enable paravirtualization code"
732 help
733 This changes the kernel so it can modify itself when it is run
734 under a hypervisor, potentially improving performance significantly
735 over full virtualization.
736
737config PARAVIRT_TIME_ACCOUNTING
738 bool "Paravirtual steal time accounting"
739 select PARAVIRT
740 default n
741 help
742 Select this option to enable fine granularity task steal time
743 accounting. Time spent executing other tasks in parallel with
744 the current vCPU is discounted from the vCPU power. To account for
745 that, there can be a small performance impact.
746
747 If in doubt, say N here.
748
Geoff Levandd28f6df2016-06-23 17:54:48 +0000749config KEXEC
750 depends on PM_SLEEP_SMP
751 select KEXEC_CORE
752 bool "kexec system call"
753 ---help---
754 kexec is a system call that implements the ability to shutdown your
755 current kernel, and to start another kernel. It is like a reboot
756 but it is independent of the system firmware. And like a reboot
757 you can start any kernel with it, not just Linux.
758
AKASHI Takahiroe62aaea2017-04-03 11:24:38 +0900759config CRASH_DUMP
760 bool "Build kdump crash kernel"
761 help
762 Generate crash dump after being started by kexec. This should
763 be normally only set in special crash dump kernels which are
764 loaded in the main kernel with kexec-tools into a specially
765 reserved region and then later executed after a crash by
766 kdump/kexec.
767
768 For more details see Documentation/kdump/kdump.txt
769
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000770config XEN_DOM0
771 def_bool y
772 depends on XEN
773
774config XEN
Julien Grallc2ba1f72014-09-17 14:07:06 -0700775 bool "Xen guest support on ARM64"
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000776 depends on ARM64 && OF
Stefano Stabellini83862cc2013-10-10 13:40:44 +0000777 select SWIOTLB_XEN
Stefano Stabellinidfd57bc2015-11-23 10:33:49 +0000778 select PARAVIRT
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000779 help
780 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
781
Steve Capperd03bb142013-04-25 15:19:21 +0100782config FORCE_MAX_ZONEORDER
783 int
784 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100785 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
Steve Capperd03bb142013-04-25 15:19:21 +0100786 default "11"
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100787 help
788 The kernel memory allocator divides physically contiguous memory
789 blocks into "zones", where each zone is a power of two number of
790 pages. This option selects the largest power of two that the kernel
791 keeps in the memory allocator. If you need to allocate very large
792 blocks of physically contiguous memory, then you may need to
793 increase this value.
794
795 This config option is actually maximum order plus one. For example,
796 a value of 11 means that the largest free memory block is 2^10 pages.
797
798 We make sure that we can allocate upto a HugePage size for each configuration.
799 Hence we have :
800 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
801
802 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
803 4M allocations matching the default size used by generic code.
Steve Capperd03bb142013-04-25 15:19:21 +0100804
Will Deacon1b907f42014-11-20 16:51:10 +0000805menuconfig ARMV8_DEPRECATED
806 bool "Emulate deprecated/obsolete ARMv8 instructions"
807 depends on COMPAT
808 help
809 Legacy software support may require certain instructions
810 that have been deprecated or obsoleted in the architecture.
811
812 Enable this config to enable selective emulation of these
813 features.
814
815 If unsure, say Y
816
817if ARMV8_DEPRECATED
818
819config SWP_EMULATION
820 bool "Emulate SWP/SWPB instructions"
821 help
822 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
823 they are always undefined. Say Y here to enable software
824 emulation of these instructions for userspace using LDXR/STXR.
825
826 In some older versions of glibc [<=2.8] SWP is used during futex
827 trylock() operations with the assumption that the code will not
828 be preempted. This invalid assumption may be more likely to fail
829 with SWP emulation enabled, leading to deadlock of the user
830 application.
831
832 NOTE: when accessing uncached shared regions, LDXR/STXR rely
833 on an external transaction monitoring block called a global
834 monitor to maintain update atomicity. If your system does not
835 implement a global monitor, this option can cause programs that
836 perform SWP operations to uncached memory to deadlock.
837
838 If unsure, say Y
839
840config CP15_BARRIER_EMULATION
841 bool "Emulate CP15 Barrier instructions"
842 help
843 The CP15 barrier instructions - CP15ISB, CP15DSB, and
844 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
845 strongly recommended to use the ISB, DSB, and DMB
846 instructions instead.
847
848 Say Y here to enable software emulation of these
849 instructions for AArch32 userspace code. When this option is
850 enabled, CP15 barrier usage is traced which can help
851 identify software that needs updating.
852
853 If unsure, say Y
854
Suzuki K. Poulose2d888f42015-01-21 12:43:11 +0000855config SETEND_EMULATION
856 bool "Emulate SETEND instruction"
857 help
858 The SETEND instruction alters the data-endianness of the
859 AArch32 EL0, and is deprecated in ARMv8.
860
861 Say Y here to enable software emulation of the instruction
862 for AArch32 userspace code.
863
864 Note: All the cpus on the system must have mixed endian support at EL0
865 for this feature to be enabled. If a new CPU - which doesn't support mixed
866 endian - is hotplugged in after this feature has been enabled, there could
867 be unexpected results in the applications.
868
869 If unsure, say Y
Will Deacon1b907f42014-11-20 16:51:10 +0000870endif
871
Catalin Marinasba428222016-07-01 18:25:31 +0100872config ARM64_SW_TTBR0_PAN
873 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
874 help
875 Enabling this option prevents the kernel from accessing
876 user-space memory directly by pointing TTBR0_EL1 to a reserved
877 zeroed area and reserved ASID. The user access routines
878 restore the valid TTBR0_EL1 temporarily.
879
Will Deacon0e4a0702015-07-27 15:54:13 +0100880menu "ARMv8.1 architectural features"
881
882config ARM64_HW_AFDBM
883 bool "Support for hardware updates of the Access and Dirty page flags"
884 default y
885 help
886 The ARMv8.1 architecture extensions introduce support for
887 hardware updates of the access and dirty information in page
888 table entries. When enabled in TCR_EL1 (HA and HD bits) on
889 capable processors, accesses to pages with PTE_AF cleared will
890 set this bit instead of raising an access flag fault.
891 Similarly, writes to read-only pages with the DBM bit set will
892 clear the read-only bit (AP[2]) instead of raising a
893 permission fault.
894
895 Kernels built with this configuration option enabled continue
896 to work on pre-ARMv8.1 hardware and the performance impact is
897 minimal. If unsure, say Y.
898
899config ARM64_PAN
900 bool "Enable support for Privileged Access Never (PAN)"
901 default y
902 help
903 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
904 prevents the kernel or hypervisor from accessing user-space (EL0)
905 memory directly.
906
907 Choosing this option will cause any unprotected (not using
908 copy_to_user et al) memory access to fail with a permission fault.
909
910 The feature is detected at runtime, and will remain as a 'nop'
911 instruction if the cpu does not implement the feature.
912
913config ARM64_LSE_ATOMICS
914 bool "Atomic instructions"
915 help
916 As part of the Large System Extensions, ARMv8.1 introduces new
917 atomic instructions that are designed specifically to scale in
918 very large systems.
919
920 Say Y here to make use of these instructions for the in-kernel
921 atomic routines. This incurs a small overhead on CPUs that do
922 not support these instructions and requires the kernel to be
923 built with binutils >= 2.25.
924
Marc Zyngier1f364c82014-02-19 09:33:14 +0000925config ARM64_VHE
926 bool "Enable support for Virtualization Host Extensions (VHE)"
927 default y
928 help
929 Virtualization Host Extensions (VHE) allow the kernel to run
930 directly at EL2 (instead of EL1) on processors that support
931 it. This leads to better performance for KVM, as they reduce
932 the cost of the world switch.
933
934 Selecting this option allows the VHE feature to be detected
935 at runtime, and does not affect processors that do not
936 implement this feature.
937
Will Deacon0e4a0702015-07-27 15:54:13 +0100938endmenu
939
Will Deaconf9933182016-02-26 16:30:14 +0000940menu "ARMv8.2 architectural features"
941
James Morse57f49592016-02-05 14:58:48 +0000942config ARM64_UAO
943 bool "Enable support for User Access Override (UAO)"
944 default y
945 help
946 User Access Override (UAO; part of the ARMv8.2 Extensions)
947 causes the 'unprivileged' variant of the load/store instructions to
948 be overriden to be privileged.
949
950 This option changes get_user() and friends to use the 'unprivileged'
951 variant of the load/store instructions. This ensures that user-space
952 really did have access to the supplied memory. When addr_limit is
953 set to kernel memory the UAO bit will be set, allowing privileged
954 access to kernel memory.
955
956 Choosing this option will cause copy_to_user() et al to use user-space
957 memory permissions.
958
959 The feature is detected at runtime, the kernel will use the
960 regular load/store instructions if the cpu does not implement the
961 feature.
962
Will Deaconf9933182016-02-26 16:30:14 +0000963endmenu
964
Ard Biesheuvelfd045f62015-11-24 12:37:35 +0100965config ARM64_MODULE_CMODEL_LARGE
966 bool
967
968config ARM64_MODULE_PLTS
969 bool
970 select ARM64_MODULE_CMODEL_LARGE
971 select HAVE_MOD_ARCH_SPECIFIC
972
Ard Biesheuvel1e48ef72016-01-26 09:13:44 +0100973config RELOCATABLE
974 bool
975 help
976 This builds the kernel as a Position Independent Executable (PIE),
977 which retains all relocation metadata required to relocate the
978 kernel binary at runtime to a different virtual address than the
979 address it was linked at.
980 Since AArch64 uses the RELA relocation format, this requires a
981 relocation pass at runtime even if the kernel is loaded at the
982 same address it was linked at.
983
Ard Biesheuvelf80fb3a2016-01-26 14:12:01 +0100984config RANDOMIZE_BASE
985 bool "Randomize the address of the kernel image"
Catalin Marinasb9c220b2016-07-26 10:16:55 -0700986 select ARM64_MODULE_PLTS if MODULES
Ard Biesheuvelf80fb3a2016-01-26 14:12:01 +0100987 select RELOCATABLE
988 help
989 Randomizes the virtual address at which the kernel image is
990 loaded, as a security feature that deters exploit attempts
991 relying on knowledge of the location of kernel internals.
992
993 It is the bootloader's job to provide entropy, by passing a
994 random u64 value in /chosen/kaslr-seed at kernel entry.
995
Ard Biesheuvel2b5fe072016-01-26 14:48:29 +0100996 When booting via the UEFI stub, it will invoke the firmware's
997 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
998 to the kernel proper. In addition, it will randomise the physical
999 location of the kernel Image as well.
1000
Ard Biesheuvelf80fb3a2016-01-26 14:12:01 +01001001 If unsure, say N.
1002
1003config RANDOMIZE_MODULE_REGION_FULL
1004 bool "Randomize the module region independently from the core kernel"
Ard Biesheuvele71a4e1b2017-06-06 17:00:22 +00001005 depends on RANDOMIZE_BASE
Ard Biesheuvelf80fb3a2016-01-26 14:12:01 +01001006 default y
1007 help
1008 Randomizes the location of the module region without considering the
1009 location of the core kernel. This way, it is impossible for modules
1010 to leak information about the location of core kernel data structures
1011 but it does imply that function calls between modules and the core
1012 kernel will need to be resolved via veneers in the module PLT.
1013
1014 When this option is not set, the module region will be randomized over
1015 a limited range that contains the [_stext, _etext] interval of the
1016 core kernel, so branch relocations are always in range.
1017
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001018endmenu
1019
1020menu "Boot options"
1021
Lorenzo Pieralisi5e89c552016-01-26 11:10:38 +00001022config ARM64_ACPI_PARKING_PROTOCOL
1023 bool "Enable support for the ARM64 ACPI parking protocol"
1024 depends on ACPI
1025 help
1026 Enable support for the ARM64 ACPI parking protocol. If disabled
1027 the kernel will not allow booting through the ARM64 ACPI parking
1028 protocol even if the corresponding data is present in the ACPI
1029 MADT table.
1030
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001031config CMDLINE
1032 string "Default kernel command string"
1033 default ""
1034 help
1035 Provide a set of default command-line options at build time by
1036 entering them here. As a minimum, you should specify the the
1037 root device (e.g. root=/dev/nfs).
1038
1039config CMDLINE_FORCE
1040 bool "Always use the default kernel command string"
1041 help
1042 Always use the default kernel command string, even if the boot
1043 loader passes other arguments to the kernel.
1044 This is useful if you cannot or don't want to change the
1045 command-line options your boot loader passes to the kernel.
1046
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +02001047config EFI_STUB
1048 bool
1049
Mark Salterf84d0272014-04-15 21:59:30 -04001050config EFI
1051 bool "UEFI runtime support"
1052 depends on OF && !CPU_BIG_ENDIAN
1053 select LIBFDT
1054 select UCS2_STRING
1055 select EFI_PARAMS_FROM_FDT
Ard Biesheuvele15dd492014-07-04 19:41:53 +02001056 select EFI_RUNTIME_WRAPPERS
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +02001057 select EFI_STUB
1058 select EFI_ARMSTUB
Mark Salterf84d0272014-04-15 21:59:30 -04001059 default y
1060 help
1061 This option provides support for runtime services provided
1062 by UEFI firmware (such as non-volatile variables, realtime
Mark Salter3c7f2552014-04-15 22:47:52 -04001063 clock, and platform reset). A UEFI stub is also provided to
1064 allow the kernel to be booted as an EFI application. This
1065 is only useful on systems that have UEFI firmware.
Mark Salterf84d0272014-04-15 21:59:30 -04001066
Yi Lid1ae8c02014-10-04 23:46:43 +08001067config DMI
1068 bool "Enable support for SMBIOS (DMI) tables"
1069 depends on EFI
1070 default y
1071 help
1072 This enables SMBIOS/DMI feature for systems.
1073
1074 This option is only useful on systems that have UEFI firmware.
1075 However, even with this option, the resultant kernel should
1076 continue to boot on existing non-UEFI platforms.
1077
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001078endmenu
1079
1080menu "Userspace binary formats"
1081
1082source "fs/Kconfig.binfmt"
1083
1084config COMPAT
1085 bool "Kernel support for 32-bit EL0"
Suzuki K. Poulose755e70b2015-10-19 14:19:32 +01001086 depends on ARM64_4K_PAGES || EXPERT
Kefeng Wang2e449042017-01-26 11:19:55 +08001087 select COMPAT_BINFMT_ELF if BINFMT_ELF
Catalin Marinasaf1839e2012-10-08 16:28:08 -07001088 select HAVE_UID16
Al Viro84b9e9b2012-12-25 16:29:11 -05001089 select OLD_SIGSUSPEND3
Al Viro51682032012-12-25 19:31:29 -05001090 select COMPAT_OLD_SIGACTION
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001091 help
1092 This option enables support for a 32-bit EL0 running under a 64-bit
1093 kernel at EL1. AArch32-specific components such as system calls,
1094 the user helper functions, VFP support and the ptrace interface are
1095 handled appropriately by the kernel.
1096
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +01001097 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1098 that you will only be able to execute AArch32 binaries that were compiled
1099 with page size aligned segments.
Alexander Grafa8fcd8b2015-03-16 16:32:23 +00001100
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001101 If you want to execute 32-bit userspace applications, say Y.
1102
1103config SYSVIPC_COMPAT
1104 def_bool y
1105 depends on COMPAT && SYSVIPC
1106
1107endmenu
1108
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +00001109menu "Power management options"
1110
1111source "kernel/power/Kconfig"
1112
James Morse82869ac2016-04-27 17:47:12 +01001113config ARCH_HIBERNATION_POSSIBLE
1114 def_bool y
1115 depends on CPU_PM
1116
1117config ARCH_HIBERNATION_HEADER
1118 def_bool y
1119 depends on HIBERNATION
1120
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +00001121config ARCH_SUSPEND_POSSIBLE
1122 def_bool y
1123
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +00001124endmenu
1125
Lorenzo Pieralisi13072202013-07-17 14:54:21 +01001126menu "CPU Power Management"
1127
1128source "drivers/cpuidle/Kconfig"
1129
Rob Herring52e7e812014-02-24 11:27:57 +09001130source "drivers/cpufreq/Kconfig"
1131
1132endmenu
1133
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001134source "net/Kconfig"
1135
1136source "drivers/Kconfig"
1137
Mark Salterf84d0272014-04-15 21:59:30 -04001138source "drivers/firmware/Kconfig"
1139
Graeme Gregoryb6a02172015-03-24 14:02:53 +00001140source "drivers/acpi/Kconfig"
1141
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001142source "fs/Kconfig"
1143
Marc Zyngierc3eb5b12013-07-04 13:34:32 +01001144source "arch/arm64/kvm/Kconfig"
1145
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001146source "arch/arm64/Kconfig.debug"
1147
1148source "security/Kconfig"
1149
1150source "crypto/Kconfig"
Ard Biesheuvel2c988332014-03-06 16:23:33 +08001151if CRYPTO
1152source "arch/arm64/crypto/Kconfig"
1153endif
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001154
1155source "lib/Kconfig"