blob: 56e85395ac24112faf17b4b06a1aa950e671df0b [file] [log] [blame]
Terje Bergstrom75471682013-03-22 16:34:01 +02001/*
2 * Tegra host1x Syncpoints
3 *
4 * Copyright (c) 2010-2013, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/io.h>
20
Thierry Redingfc3be3e2013-10-09 10:32:54 +020021#include "../dev.h"
22#include "../syncpt.h"
Terje Bergstrom75471682013-03-22 16:34:01 +020023
24/*
25 * Write the current syncpoint value back to hw.
26 */
27static void syncpt_restore(struct host1x_syncpt *sp)
28{
29 struct host1x *host = sp->host;
30 int min = host1x_syncpt_read_min(sp);
31 host1x_sync_writel(host, min, HOST1X_SYNC_SYNCPT(sp->id));
32}
33
34/*
35 * Write the current waitbase value back to hw.
36 */
37static void syncpt_restore_wait_base(struct host1x_syncpt *sp)
38{
39 struct host1x *host = sp->host;
40 host1x_sync_writel(host, sp->base_val,
41 HOST1X_SYNC_SYNCPT_BASE(sp->id));
42}
43
44/*
45 * Read waitbase value from hw.
46 */
47static void syncpt_read_wait_base(struct host1x_syncpt *sp)
48{
49 struct host1x *host = sp->host;
50 sp->base_val =
51 host1x_sync_readl(host, HOST1X_SYNC_SYNCPT_BASE(sp->id));
52}
53
54/*
55 * Updates the last value read from hardware.
56 */
57static u32 syncpt_load(struct host1x_syncpt *sp)
58{
59 struct host1x *host = sp->host;
60 u32 old, live;
61
62 /* Loop in case there's a race writing to min_val */
63 do {
64 old = host1x_syncpt_read_min(sp);
65 live = host1x_sync_readl(host, HOST1X_SYNC_SYNCPT(sp->id));
66 } while ((u32)atomic_cmpxchg(&sp->min_val, old, live) != old);
67
68 if (!host1x_syncpt_check_max(sp, live))
69 dev_err(host->dev, "%s failed: id=%u, min=%d, max=%d\n",
70 __func__, sp->id, host1x_syncpt_read_min(sp),
71 host1x_syncpt_read_max(sp));
72
73 return live;
74}
75
76/*
77 * Write a cpu syncpoint increment to the hardware, without touching
78 * the cache.
79 */
Arto Merilainenebae30b2013-05-29 13:26:08 +030080static int syncpt_cpu_incr(struct host1x_syncpt *sp)
Terje Bergstrom75471682013-03-22 16:34:01 +020081{
82 struct host1x *host = sp->host;
83 u32 reg_offset = sp->id / 32;
84
85 if (!host1x_syncpt_client_managed(sp) &&
Arto Merilainenebae30b2013-05-29 13:26:08 +030086 host1x_syncpt_idle(sp))
87 return -EINVAL;
Terje Bergstrom75471682013-03-22 16:34:01 +020088 host1x_sync_writel(host, BIT_MASK(sp->id),
89 HOST1X_SYNC_SYNCPT_CPU_INCR(reg_offset));
90 wmb();
Arto Merilainenebae30b2013-05-29 13:26:08 +030091
92 return 0;
Terje Bergstrom75471682013-03-22 16:34:01 +020093}
94
Terje Bergstrom65793242013-03-22 16:34:03 +020095/* remove a wait pointed to by patch_addr */
96static int syncpt_patch_wait(struct host1x_syncpt *sp, void *patch_addr)
97{
98 u32 override = host1x_class_host_wait_syncpt(
99 HOST1X_SYNCPT_RESERVED, 0);
100
101 *((u32 *)patch_addr) = override;
102 return 0;
103}
104
Terje Bergstrom75471682013-03-22 16:34:01 +0200105static const struct host1x_syncpt_ops host1x_syncpt_ops = {
106 .restore = syncpt_restore,
107 .restore_wait_base = syncpt_restore_wait_base,
108 .load_wait_base = syncpt_read_wait_base,
109 .load = syncpt_load,
110 .cpu_incr = syncpt_cpu_incr,
Terje Bergstrom65793242013-03-22 16:34:03 +0200111 .patch_wait = syncpt_patch_wait,
Terje Bergstrom75471682013-03-22 16:34:01 +0200112};