blob: 1d740a8c42ab32ed9d36dd6d38635d6032a48215 [file] [log] [blame]
Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001// SPDX-License-Identifier: GPL-2.0
Yoshinori Sato618b9022015-01-28 02:52:42 +09002/*
3 * linux/arch/h8300/kernel/cpu/timer/timer8.c
4 *
5 * Yoshinori Sato <ysato@users.sourcefoge.jp>
6 *
7 * 8bit Timer driver
8 *
9 */
10
11#include <linux/errno.h>
Yoshinori Sato618b9022015-01-28 02:52:42 +090012#include <linux/kernel.h>
13#include <linux/interrupt.h>
14#include <linux/init.h>
Yoshinori Sato618b9022015-01-28 02:52:42 +090015#include <linux/clockchips.h>
Yoshinori Sato618b9022015-01-28 02:52:42 +090016#include <linux/clk.h>
17#include <linux/io.h>
18#include <linux/of.h>
Yoshinori Sato4633f4c2015-11-07 01:31:44 +090019#include <linux/of_address.h>
20#include <linux/of_irq.h>
Yoshinori Sato618b9022015-01-28 02:52:42 +090021
Yoshinori Sato618b9022015-01-28 02:52:42 +090022#define _8TCR 0
23#define _8TCSR 2
24#define TCORA 4
25#define TCORB 6
26#define _8TCNT 8
27
Yoshinori Satod33f2502015-12-05 02:48:18 +090028#define CMIEA 6
29#define CMFA 6
30
Yoshinori Sato618b9022015-01-28 02:52:42 +090031#define FLAG_STARTED (1 << 3)
32
Yoshinori Sato4633f4c2015-11-07 01:31:44 +090033#define SCALE 64
34
Yoshinori Satod33f2502015-12-05 02:48:18 +090035#define bset(b, a) iowrite8(ioread8(a) | (1 << (b)), (a))
36#define bclr(b, a) iowrite8(ioread8(a) & ~(1 << (b)), (a))
37
Yoshinori Sato618b9022015-01-28 02:52:42 +090038struct timer8_priv {
Yoshinori Sato618b9022015-01-28 02:52:42 +090039 struct clock_event_device ced;
Daniel Lezcano75160512015-11-08 22:55:12 +010040 void __iomem *mapbase;
Yoshinori Sato618b9022015-01-28 02:52:42 +090041 unsigned long flags;
42 unsigned int rate;
Yoshinori Sato618b9022015-01-28 02:52:42 +090043};
44
Yoshinori Sato618b9022015-01-28 02:52:42 +090045static irqreturn_t timer8_interrupt(int irq, void *dev_id)
46{
47 struct timer8_priv *p = dev_id;
48
Daniel Lezcano7053fda2015-11-08 18:07:38 +010049 if (clockevent_state_oneshot(&p->ced))
Yoshinori Satod33f2502015-12-05 02:48:18 +090050 iowrite16be(0x0000, p->mapbase + _8TCR);
Daniel Lezcano7053fda2015-11-08 18:07:38 +010051
52 p->ced.event_handler(&p->ced);
Yoshinori Sato618b9022015-01-28 02:52:42 +090053
Yoshinori Satod33f2502015-12-05 02:48:18 +090054 bclr(CMFA, p->mapbase + _8TCSR);
Yoshinori Satof37632d2015-12-05 02:48:16 +090055
Yoshinori Sato618b9022015-01-28 02:52:42 +090056 return IRQ_HANDLED;
57}
58
59static void timer8_set_next(struct timer8_priv *p, unsigned long delta)
60{
Yoshinori Sato618b9022015-01-28 02:52:42 +090061 if (delta >= 0x10000)
Daniel Lezcano8c09b7d2015-11-09 09:02:38 +010062 pr_warn("delta out of range\n");
Yoshinori Satod33f2502015-12-05 02:48:18 +090063 bclr(CMIEA, p->mapbase + _8TCR);
64 iowrite16be(delta, p->mapbase + TCORA);
65 iowrite16be(0x0000, p->mapbase + _8TCNT);
66 bclr(CMFA, p->mapbase + _8TCSR);
67 bset(CMIEA, p->mapbase + _8TCR);
Yoshinori Sato618b9022015-01-28 02:52:42 +090068}
69
70static int timer8_enable(struct timer8_priv *p)
71{
Yoshinori Satod33f2502015-12-05 02:48:18 +090072 iowrite16be(0xffff, p->mapbase + TCORA);
73 iowrite16be(0x0000, p->mapbase + _8TCNT);
74 iowrite16be(0x0c02, p->mapbase + _8TCR);
Yoshinori Sato618b9022015-01-28 02:52:42 +090075
76 return 0;
77}
78
79static int timer8_start(struct timer8_priv *p)
80{
Daniel Lezcanocce483e2015-11-08 23:24:28 +010081 int ret;
Yoshinori Sato618b9022015-01-28 02:52:42 +090082
Daniel Lezcanocce483e2015-11-08 23:24:28 +010083 if ((p->flags & FLAG_STARTED))
84 return 0;
Yoshinori Sato618b9022015-01-28 02:52:42 +090085
Daniel Lezcanocce483e2015-11-08 23:24:28 +010086 ret = timer8_enable(p);
87 if (!ret)
88 p->flags |= FLAG_STARTED;
Yoshinori Sato618b9022015-01-28 02:52:42 +090089
Yoshinori Sato618b9022015-01-28 02:52:42 +090090 return ret;
91}
92
93static void timer8_stop(struct timer8_priv *p)
94{
Yoshinori Satod33f2502015-12-05 02:48:18 +090095 iowrite16be(0x0000, p->mapbase + _8TCR);
Yoshinori Sato618b9022015-01-28 02:52:42 +090096}
97
98static inline struct timer8_priv *ced_to_priv(struct clock_event_device *ced)
99{
100 return container_of(ced, struct timer8_priv, ced);
101}
102
Daniel Lezcano1f058d52015-11-08 17:46:54 +0100103static void timer8_clock_event_start(struct timer8_priv *p, unsigned long delta)
Yoshinori Sato618b9022015-01-28 02:52:42 +0900104{
Yoshinori Sato618b9022015-01-28 02:52:42 +0900105 timer8_start(p);
Daniel Lezcano1f058d52015-11-08 17:46:54 +0100106 timer8_set_next(p, delta);
Yoshinori Sato618b9022015-01-28 02:52:42 +0900107}
108
Viresh Kumarfc2b2f52015-07-27 15:02:00 +0530109static int timer8_clock_event_shutdown(struct clock_event_device *ced)
110{
111 timer8_stop(ced_to_priv(ced));
112 return 0;
113}
114
115static int timer8_clock_event_periodic(struct clock_event_device *ced)
Yoshinori Sato618b9022015-01-28 02:52:42 +0900116{
117 struct timer8_priv *p = ced_to_priv(ced);
118
Yoshinori Sato4633f4c2015-11-07 01:31:44 +0900119 pr_info("%s: used for periodic clock events\n", ced->name);
Viresh Kumarfc2b2f52015-07-27 15:02:00 +0530120 timer8_stop(p);
Daniel Lezcano1f058d52015-11-08 17:46:54 +0100121 timer8_clock_event_start(p, (p->rate + HZ/2) / HZ);
Viresh Kumarfc2b2f52015-07-27 15:02:00 +0530122
123 return 0;
124}
125
126static int timer8_clock_event_oneshot(struct clock_event_device *ced)
127{
128 struct timer8_priv *p = ced_to_priv(ced);
129
Yoshinori Sato4633f4c2015-11-07 01:31:44 +0900130 pr_info("%s: used for oneshot clock events\n", ced->name);
Viresh Kumarfc2b2f52015-07-27 15:02:00 +0530131 timer8_stop(p);
Daniel Lezcano1f058d52015-11-08 17:46:54 +0100132 timer8_clock_event_start(p, 0x10000);
Viresh Kumarfc2b2f52015-07-27 15:02:00 +0530133
134 return 0;
Yoshinori Sato618b9022015-01-28 02:52:42 +0900135}
136
137static int timer8_clock_event_next(unsigned long delta,
138 struct clock_event_device *ced)
139{
140 struct timer8_priv *p = ced_to_priv(ced);
141
Viresh Kumarfc2b2f52015-07-27 15:02:00 +0530142 BUG_ON(!clockevent_state_oneshot(ced));
Yoshinori Sato618b9022015-01-28 02:52:42 +0900143 timer8_set_next(p, delta - 1);
144
145 return 0;
146}
147
Yoshinori Sato4633f4c2015-11-07 01:31:44 +0900148static struct timer8_priv timer8_priv = {
149 .ced = {
150 .name = "h8300_8timer",
151 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
152 .rating = 200,
153 .set_next_event = timer8_clock_event_next,
154 .set_state_shutdown = timer8_clock_event_shutdown,
155 .set_state_periodic = timer8_clock_event_periodic,
156 .set_state_oneshot = timer8_clock_event_oneshot,
157 },
158};
159
Daniel Lezcano691f8f82016-06-06 17:56:37 +0200160static int __init h8300_8timer_init(struct device_node *node)
Yoshinori Sato618b9022015-01-28 02:52:42 +0900161{
Yoshinori Sato4633f4c2015-11-07 01:31:44 +0900162 void __iomem *base;
Daniel Lezcano691f8f82016-06-06 17:56:37 +0200163 int irq, ret;
Yoshinori Sato4633f4c2015-11-07 01:31:44 +0900164 struct clk *clk;
Yoshinori Sato618b9022015-01-28 02:52:42 +0900165
Yoshinori Sato4633f4c2015-11-07 01:31:44 +0900166 clk = of_clk_get(node, 0);
167 if (IS_ERR(clk)) {
168 pr_err("failed to get clock for clockevent\n");
Daniel Lezcano691f8f82016-06-06 17:56:37 +0200169 return PTR_ERR(clk);
Yoshinori Sato618b9022015-01-28 02:52:42 +0900170 }
171
Daniel Lezcano691f8f82016-06-06 17:56:37 +0200172 ret = ENXIO;
Yoshinori Sato4633f4c2015-11-07 01:31:44 +0900173 base = of_iomap(node, 0);
174 if (!base) {
175 pr_err("failed to map registers for clockevent\n");
176 goto free_clk;
177 }
178
Daniel Lezcano691f8f82016-06-06 17:56:37 +0200179 ret = -EINVAL;
Yoshinori Sato4633f4c2015-11-07 01:31:44 +0900180 irq = irq_of_parse_and_map(node, 0);
Daniel Lezcano54a0cd52015-11-08 17:56:18 +0100181 if (!irq) {
Yoshinori Sato4633f4c2015-11-07 01:31:44 +0900182 pr_err("failed to get irq for clockevent\n");
183 goto unmap_reg;
Yoshinori Sato618b9022015-01-28 02:52:42 +0900184 }
185
Daniel Lezcano75160512015-11-08 22:55:12 +0100186 timer8_priv.mapbase = base;
Daniel Lezcanocce483e2015-11-08 23:24:28 +0100187
Yoshinori Sato6f2b6112015-12-05 02:48:17 +0900188 timer8_priv.rate = clk_get_rate(clk) / SCALE;
189 if (!timer8_priv.rate) {
Daniel Lezcanocce483e2015-11-08 23:24:28 +0100190 pr_err("Failed to get rate for the clocksource\n");
191 goto unmap_reg;
192 }
Yoshinori Sato618b9022015-01-28 02:52:42 +0900193
Yoshinori Sato6f2b6112015-12-05 02:48:17 +0900194 if (request_irq(irq, timer8_interrupt, IRQF_TIMER,
195 timer8_priv.ced.name, &timer8_priv) < 0) {
Yoshinori Sato4633f4c2015-11-07 01:31:44 +0900196 pr_err("failed to request irq %d for clockevent\n", irq);
197 goto unmap_reg;
Yoshinori Sato618b9022015-01-28 02:52:42 +0900198 }
Yoshinori Sato618b9022015-01-28 02:52:42 +0900199
Yoshinori Sato6f2b6112015-12-05 02:48:17 +0900200 clockevents_config_and_register(&timer8_priv.ced,
201 timer8_priv.rate, 1, 0x0000ffff);
Daniel Lezcanocce483e2015-11-08 23:24:28 +0100202
Daniel Lezcano691f8f82016-06-06 17:56:37 +0200203 return 0;
Yoshinori Sato4633f4c2015-11-07 01:31:44 +0900204unmap_reg:
205 iounmap(base);
206free_clk:
207 clk_put(clk);
Daniel Lezcano691f8f82016-06-06 17:56:37 +0200208 return ret;
Yoshinori Sato618b9022015-01-28 02:52:42 +0900209}
210
Daniel Lezcano17273392017-05-26 16:56:11 +0200211TIMER_OF_DECLARE(h8300_8bit, "renesas,8bit-timer", h8300_8timer_init);