Thomas Gleixner | ec8f24b | 2019-05-19 13:07:45 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
Jerome Brunet | 7b5c572 | 2020-08-28 17:47:35 +0200 | [diff] [blame] | 2 | menu "Clock support for Amlogic platforms" |
| 3 | depends on ARCH_MESON || COMPILE_TEST |
| 4 | |
Jerome Brunet | 889c2b7 | 2019-02-01 13:58:41 +0100 | [diff] [blame] | 5 | config COMMON_CLK_MESON_REGMAP |
| 6 | tristate |
Jerome Brunet | ea11dda | 2018-02-12 15:58:32 +0100 | [diff] [blame] | 7 | select REGMAP |
| 8 | |
Jerome Brunet | 889c2b7 | 2019-02-01 13:58:41 +0100 | [diff] [blame] | 9 | config COMMON_CLK_MESON_DUALDIV |
| 10 | tristate |
| 11 | select COMMON_CLK_MESON_REGMAP |
| 12 | |
| 13 | config COMMON_CLK_MESON_MPLL |
| 14 | tristate |
| 15 | select COMMON_CLK_MESON_REGMAP |
| 16 | |
| 17 | config COMMON_CLK_MESON_PHASE |
| 18 | tristate |
| 19 | select COMMON_CLK_MESON_REGMAP |
| 20 | |
| 21 | config COMMON_CLK_MESON_PLL |
| 22 | tristate |
| 23 | select COMMON_CLK_MESON_REGMAP |
| 24 | |
| 25 | config COMMON_CLK_MESON_SCLK_DIV |
| 26 | tristate |
| 27 | select COMMON_CLK_MESON_REGMAP |
| 28 | |
| 29 | config COMMON_CLK_MESON_VID_PLL_DIV |
| 30 | tristate |
| 31 | select COMMON_CLK_MESON_REGMAP |
| 32 | |
| 33 | config COMMON_CLK_MESON_AO_CLKC |
| 34 | tristate |
| 35 | select COMMON_CLK_MESON_REGMAP |
Jerome Brunet | 889c2b7 | 2019-02-01 13:58:41 +0100 | [diff] [blame] | 36 | select RESET_CONTROLLER |
| 37 | |
Jerome Brunet | 6682bd4 | 2019-02-01 15:53:45 +0100 | [diff] [blame] | 38 | config COMMON_CLK_MESON_EE_CLKC |
| 39 | tristate |
| 40 | select COMMON_CLK_MESON_REGMAP |
Jerome Brunet | 6682bd4 | 2019-02-01 15:53:45 +0100 | [diff] [blame] | 41 | |
Neil Armstrong | 26d3443 | 2019-07-31 10:40:17 +0200 | [diff] [blame] | 42 | config COMMON_CLK_MESON_CPU_DYNDIV |
| 43 | tristate |
| 44 | select COMMON_CLK_MESON_REGMAP |
| 45 | |
Michael Turquette | cb7c47d | 2016-05-23 14:29:13 -0700 | [diff] [blame] | 46 | config COMMON_CLK_MESON8B |
Jerome Brunet | 7b5c572 | 2020-08-28 17:47:35 +0200 | [diff] [blame] | 47 | bool "Meson8 SoC Clock controller support" |
| 48 | depends on ARM |
| 49 | default y |
Jerome Brunet | 889c2b7 | 2019-02-01 13:58:41 +0100 | [diff] [blame] | 50 | select COMMON_CLK_MESON_REGMAP |
| 51 | select COMMON_CLK_MESON_MPLL |
| 52 | select COMMON_CLK_MESON_PLL |
| 53 | select MFD_SYSCON |
Martin Blumenstingl | 1896217 | 2017-07-28 23:13:12 +0200 | [diff] [blame] | 54 | select RESET_CONTROLLER |
Michael Turquette | cb7c47d | 2016-05-23 14:29:13 -0700 | [diff] [blame] | 55 | help |
Martin Blumenstingl | 855f06a | 2017-06-04 20:33:39 +0200 | [diff] [blame] | 56 | Support for the clock controller on AmLogic S802 (Meson8), |
| 57 | S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you |
| 58 | want peripherals and CPU frequency scaling to work. |
Michael Turquette | 738f66d | 2016-05-23 15:44:26 -0700 | [diff] [blame] | 59 | |
| 60 | config COMMON_CLK_GXBB |
Kevin Hilman | 20425f6 | 2020-11-18 11:14:05 -0800 | [diff] [blame] | 61 | tristate "GXBB and GXL SoC clock controllers support" |
Jerome Brunet | 7b5c572 | 2020-08-28 17:47:35 +0200 | [diff] [blame] | 62 | depends on ARM64 |
| 63 | default y |
Jerome Brunet | 889c2b7 | 2019-02-01 13:58:41 +0100 | [diff] [blame] | 64 | select COMMON_CLK_MESON_REGMAP |
| 65 | select COMMON_CLK_MESON_DUALDIV |
| 66 | select COMMON_CLK_MESON_VID_PLL_DIV |
| 67 | select COMMON_CLK_MESON_MPLL |
| 68 | select COMMON_CLK_MESON_PLL |
| 69 | select COMMON_CLK_MESON_AO_CLKC |
Jerome Brunet | 6682bd4 | 2019-02-01 15:53:45 +0100 | [diff] [blame] | 70 | select COMMON_CLK_MESON_EE_CLKC |
Jerome Brunet | 4162dd5b | 2018-02-12 15:58:46 +0100 | [diff] [blame] | 71 | select MFD_SYSCON |
Michael Turquette | 738f66d | 2016-05-23 15:44:26 -0700 | [diff] [blame] | 72 | help |
| 73 | Support for the clock controller on AmLogic S905 devices, aka gxbb. |
| 74 | Say Y if you want peripherals and CPU frequency scaling to work. |
Qiufang Dai | 78b4af3 | 2017-12-11 22:13:46 +0800 | [diff] [blame] | 75 | |
| 76 | config COMMON_CLK_AXG |
Kevin Hilman | 20425f6 | 2020-11-18 11:14:05 -0800 | [diff] [blame] | 77 | tristate "AXG SoC clock controllers support" |
Jerome Brunet | 7b5c572 | 2020-08-28 17:47:35 +0200 | [diff] [blame] | 78 | depends on ARM64 |
| 79 | default y |
Jerome Brunet | 889c2b7 | 2019-02-01 13:58:41 +0100 | [diff] [blame] | 80 | select COMMON_CLK_MESON_REGMAP |
| 81 | select COMMON_CLK_MESON_DUALDIV |
| 82 | select COMMON_CLK_MESON_MPLL |
| 83 | select COMMON_CLK_MESON_PLL |
| 84 | select COMMON_CLK_MESON_AO_CLKC |
Jerome Brunet | 6682bd4 | 2019-02-01 15:53:45 +0100 | [diff] [blame] | 85 | select COMMON_CLK_MESON_EE_CLKC |
Jerome Brunet | 4162dd5b | 2018-02-12 15:58:46 +0100 | [diff] [blame] | 86 | select MFD_SYSCON |
Qiufang Dai | 78b4af3 | 2017-12-11 22:13:46 +0800 | [diff] [blame] | 87 | help |
| 88 | Support for the clock controller on AmLogic A113D devices, aka axg. |
| 89 | Say Y if you want peripherals and CPU frequency scaling to work. |
Jerome Brunet | 1cd5018 | 2018-05-22 18:34:57 +0200 | [diff] [blame] | 90 | |
| 91 | config COMMON_CLK_AXG_AUDIO |
| 92 | tristate "Meson AXG Audio Clock Controller Driver" |
Jerome Brunet | 7b5c572 | 2020-08-28 17:47:35 +0200 | [diff] [blame] | 93 | depends on ARM64 |
Jerome Brunet | 889c2b7 | 2019-02-01 13:58:41 +0100 | [diff] [blame] | 94 | select COMMON_CLK_MESON_REGMAP |
| 95 | select COMMON_CLK_MESON_PHASE |
| 96 | select COMMON_CLK_MESON_SCLK_DIV |
Jerome Brunet | cb78ba7 | 2019-02-01 13:58:40 +0100 | [diff] [blame] | 97 | select REGMAP_MMIO |
Jerome Brunet | 1cd5018 | 2018-05-22 18:34:57 +0200 | [diff] [blame] | 98 | help |
| 99 | Support for the audio clock controller on AmLogic A113D devices, |
| 100 | aka axg, Say Y if you want audio subsystem to work. |
Jian Hu | 085a4ea | 2019-02-01 15:53:44 +0100 | [diff] [blame] | 101 | |
| 102 | config COMMON_CLK_G12A |
Kevin Hilman | 20425f6 | 2020-11-18 11:14:05 -0800 | [diff] [blame] | 103 | tristate "G12 and SM1 SoC clock controllers support" |
Jerome Brunet | 7b5c572 | 2020-08-28 17:47:35 +0200 | [diff] [blame] | 104 | depends on ARM64 |
| 105 | default y |
Jian Hu | 085a4ea | 2019-02-01 15:53:44 +0100 | [diff] [blame] | 106 | select COMMON_CLK_MESON_REGMAP |
Neil Armstrong | 042f01b | 2019-02-12 17:28:59 +0100 | [diff] [blame] | 107 | select COMMON_CLK_MESON_DUALDIV |
Jian Hu | 085a4ea | 2019-02-01 15:53:44 +0100 | [diff] [blame] | 108 | select COMMON_CLK_MESON_MPLL |
| 109 | select COMMON_CLK_MESON_PLL |
Neil Armstrong | 042f01b | 2019-02-12 17:28:59 +0100 | [diff] [blame] | 110 | select COMMON_CLK_MESON_AO_CLKC |
Jerome Brunet | 6682bd4 | 2019-02-01 15:53:45 +0100 | [diff] [blame] | 111 | select COMMON_CLK_MESON_EE_CLKC |
Neil Armstrong | 26d3443 | 2019-07-31 10:40:17 +0200 | [diff] [blame] | 112 | select COMMON_CLK_MESON_CPU_DYNDIV |
Kevin Hilman | bae69bf | 2020-11-18 11:09:30 -0800 | [diff] [blame] | 113 | select COMMON_CLK_MESON_VID_PLL_DIV |
Jian Hu | 085a4ea | 2019-02-01 15:53:44 +0100 | [diff] [blame] | 114 | select MFD_SYSCON |
| 115 | help |
| 116 | Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2 |
| 117 | devices, aka g12a. Say Y if you want peripherals to work. |
Jerome Brunet | 7b5c572 | 2020-08-28 17:47:35 +0200 | [diff] [blame] | 118 | endmenu |