Changbin Du | 0c7180f | 2019-05-08 23:21:28 +0800 | [diff] [blame] | 1 | .. SPDX-License-Identifier: GPL-2.0 |
| 2 | |
| 3 | ===================== |
| 4 | AMD Memory Encryption |
| 5 | ===================== |
| 6 | |
Brijesh Singh | 33e63ac | 2017-10-20 09:30:43 -0500 | [diff] [blame] | 7 | Secure Memory Encryption (SME) and Secure Encrypted Virtualization (SEV) are |
| 8 | features found on AMD processors. |
Tom Lendacky | c262f3b | 2017-07-17 16:09:58 -0500 | [diff] [blame] | 9 | |
| 10 | SME provides the ability to mark individual pages of memory as encrypted using |
| 11 | the standard x86 page tables. A page that is marked encrypted will be |
| 12 | automatically decrypted when read from DRAM and encrypted when written to |
| 13 | DRAM. SME can therefore be used to protect the contents of DRAM from physical |
| 14 | attacks on the system. |
| 15 | |
Brijesh Singh | 33e63ac | 2017-10-20 09:30:43 -0500 | [diff] [blame] | 16 | SEV enables running encrypted virtual machines (VMs) in which the code and data |
| 17 | of the guest VM are secured so that a decrypted version is available only |
| 18 | within the VM itself. SEV guest VMs have the concept of private and shared |
| 19 | memory. Private memory is encrypted with the guest-specific key, while shared |
| 20 | memory may be encrypted with hypervisor key. When SME is enabled, the hypervisor |
| 21 | key is the same key which is used in SME. |
| 22 | |
Tom Lendacky | c262f3b | 2017-07-17 16:09:58 -0500 | [diff] [blame] | 23 | A page is encrypted when a page table entry has the encryption bit set (see |
| 24 | below on how to determine its position). The encryption bit can also be |
| 25 | specified in the cr3 register, allowing the PGD table to be encrypted. Each |
| 26 | successive level of page tables can also be encrypted by setting the encryption |
| 27 | bit in the page table entry that points to the next table. This allows the full |
| 28 | page table hierarchy to be encrypted. Note, this means that just because the |
Brijesh Singh | 33e63ac | 2017-10-20 09:30:43 -0500 | [diff] [blame] | 29 | encryption bit is set in cr3, doesn't imply the full hierarchy is encrypted. |
Tom Lendacky | c262f3b | 2017-07-17 16:09:58 -0500 | [diff] [blame] | 30 | Each page table entry in the hierarchy needs to have the encryption bit set to |
| 31 | achieve that. So, theoretically, you could have the encryption bit set in cr3 |
| 32 | so that the PGD is encrypted, but not set the encryption bit in the PGD entry |
| 33 | for a PUD which results in the PUD pointed to by that entry to not be |
| 34 | encrypted. |
| 35 | |
Brijesh Singh | 33e63ac | 2017-10-20 09:30:43 -0500 | [diff] [blame] | 36 | When SEV is enabled, instruction pages and guest page tables are always treated |
| 37 | as private. All the DMA operations inside the guest must be performed on shared |
| 38 | memory. Since the memory encryption bit is controlled by the guest OS when it |
| 39 | is operating in 64-bit or 32-bit PAE mode, in all other modes the SEV hardware |
| 40 | forces the memory encryption bit to 1. |
| 41 | |
| 42 | Support for SME and SEV can be determined through the CPUID instruction. The |
Changbin Du | 0c7180f | 2019-05-08 23:21:28 +0800 | [diff] [blame] | 43 | CPUID function 0x8000001f reports information related to SME:: |
Tom Lendacky | c262f3b | 2017-07-17 16:09:58 -0500 | [diff] [blame] | 44 | |
| 45 | 0x8000001f[eax]: |
| 46 | Bit[0] indicates support for SME |
Brijesh Singh | 33e63ac | 2017-10-20 09:30:43 -0500 | [diff] [blame] | 47 | Bit[1] indicates support for SEV |
Tom Lendacky | c262f3b | 2017-07-17 16:09:58 -0500 | [diff] [blame] | 48 | 0x8000001f[ebx]: |
| 49 | Bits[5:0] pagetable bit number used to activate memory |
| 50 | encryption |
| 51 | Bits[11:6] reduction in physical address space, in bits, when |
| 52 | memory encryption is enabled (this only affects |
| 53 | system physical addresses, not guest physical |
| 54 | addresses) |
| 55 | |
Brijesh Singh | 059e5c3 | 2021-04-27 06:16:36 -0500 | [diff] [blame] | 56 | If support for SME is present, MSR 0xc00100010 (MSR_AMD64_SYSCFG) can be used to |
Changbin Du | 0c7180f | 2019-05-08 23:21:28 +0800 | [diff] [blame] | 57 | determine if SME is enabled and/or to enable memory encryption:: |
Tom Lendacky | c262f3b | 2017-07-17 16:09:58 -0500 | [diff] [blame] | 58 | |
| 59 | 0xc0010010: |
| 60 | Bit[23] 0 = memory encryption features are disabled |
| 61 | 1 = memory encryption features are enabled |
| 62 | |
Brijesh Singh | 33e63ac | 2017-10-20 09:30:43 -0500 | [diff] [blame] | 63 | If SEV is supported, MSR 0xc0010131 (MSR_AMD64_SEV) can be used to determine if |
Changbin Du | 0c7180f | 2019-05-08 23:21:28 +0800 | [diff] [blame] | 64 | SEV is active:: |
Brijesh Singh | 33e63ac | 2017-10-20 09:30:43 -0500 | [diff] [blame] | 65 | |
| 66 | 0xc0010131: |
| 67 | Bit[0] 0 = memory encryption is not active |
| 68 | 1 = memory encryption is active |
| 69 | |
Tom Lendacky | c262f3b | 2017-07-17 16:09:58 -0500 | [diff] [blame] | 70 | Linux relies on BIOS to set this bit if BIOS has determined that the reduction |
| 71 | in the physical address space as a result of enabling memory encryption (see |
| 72 | CPUID information above) will not conflict with the address space resource |
| 73 | requirements for the system. If this bit is not set upon Linux startup then |
| 74 | Linux itself will not set it and memory encryption will not be possible. |
| 75 | |
| 76 | The state of SME in the Linux kernel can be documented as follows: |
Changbin Du | 0c7180f | 2019-05-08 23:21:28 +0800 | [diff] [blame] | 77 | |
Tom Lendacky | c262f3b | 2017-07-17 16:09:58 -0500 | [diff] [blame] | 78 | - Supported: |
| 79 | The CPU supports SME (determined through CPUID instruction). |
| 80 | |
| 81 | - Enabled: |
Brijesh Singh | 059e5c3 | 2021-04-27 06:16:36 -0500 | [diff] [blame] | 82 | Supported and bit 23 of MSR_AMD64_SYSCFG is set. |
Tom Lendacky | c262f3b | 2017-07-17 16:09:58 -0500 | [diff] [blame] | 83 | |
| 84 | - Active: |
| 85 | Supported, Enabled and the Linux kernel is actively applying |
| 86 | the encryption bit to page table entries (the SME mask in the |
| 87 | kernel is non-zero). |
| 88 | |
| 89 | SME can also be enabled and activated in the BIOS. If SME is enabled and |
| 90 | activated in the BIOS, then all memory accesses will be encrypted and it will |
| 91 | not be necessary to activate the Linux memory encryption support. If the BIOS |
Brijesh Singh | 059e5c3 | 2021-04-27 06:16:36 -0500 | [diff] [blame] | 92 | merely enables SME (sets bit 23 of the MSR_AMD64_SYSCFG), then Linux can activate |
Tom Lendacky | c262f3b | 2017-07-17 16:09:58 -0500 | [diff] [blame] | 93 | memory encryption by default (CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT=y) or |
| 94 | by supplying mem_encrypt=on on the kernel command line. However, if BIOS does |
| 95 | not enable SME, then Linux will not be able to activate memory encryption, even |
| 96 | if configured to do so by default or the mem_encrypt=on command line parameter |
| 97 | is specified. |