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Kim Phillips9c4a7962008-06-23 19:50:15 +08001/*
2 * Freescale SEC (talitos) device register and descriptor header defines
3 *
Kim Phillipsad42d5f2011-11-21 16:13:27 +08004 * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
Kim Phillips9c4a7962008-06-23 19:50:15 +08005 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 */
30
Horia Geantad1a0eb92012-07-03 19:16:51 +030031#define TALITOS_TIMEOUT 100000
32#define TALITOS_MAX_DATA_LEN 65535
33
34#define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
35#define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
36#define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
37
38/* descriptor pointer entry */
39struct talitos_ptr {
LEROY Christophe90490752015-04-17 16:32:01 +020040 union {
41 struct { /* SEC2 format */
42 __be16 len; /* length */
43 u8 j_extent; /* jump to sg link table and/or extent*/
44 u8 eptr; /* extended address */
45 };
46 struct { /* SEC1 format */
47 __be16 res;
48 __be16 len1; /* length */
49 };
50 };
Horia Geantad1a0eb92012-07-03 19:16:51 +030051 __be32 ptr; /* address */
52};
53
54static const struct talitos_ptr zero_entry = {
55 .len = 0,
56 .j_extent = 0,
57 .eptr = 0,
58 .ptr = 0
59};
60
61/* descriptor */
62struct talitos_desc {
63 __be32 hdr; /* header high bits */
LEROY Christophe90490752015-04-17 16:32:01 +020064 union {
65 __be32 hdr_lo; /* header low bits */
66 __be32 hdr1; /* header for SEC1 */
67 };
Horia Geantad1a0eb92012-07-03 19:16:51 +030068 struct talitos_ptr ptr[7]; /* ptr/len pair array */
LEROY Christophe90490752015-04-17 16:32:01 +020069 __be32 next_desc; /* next descriptor (SEC1) */
Horia Geantad1a0eb92012-07-03 19:16:51 +030070};
71
LEROY Christophe7d607c6a2015-04-17 16:32:09 +020072#define TALITOS_DESC_SIZE (sizeof(struct talitos_desc) - sizeof(__be32))
73
Horia Geantad1a0eb92012-07-03 19:16:51 +030074/**
75 * talitos_request - descriptor submission request
76 * @desc: descriptor pointer (kernel virtual)
77 * @dma_desc: descriptor's physical bus address
78 * @callback: whom to call when descriptor processing is done
79 * @context: caller context (optional)
80 */
81struct talitos_request {
82 struct talitos_desc *desc;
83 dma_addr_t dma_desc;
84 void (*callback) (struct device *dev, struct talitos_desc *desc,
85 void *context, int error);
86 void *context;
87};
88
89/* per-channel fifo management */
90struct talitos_channel {
91 void __iomem *reg;
92
93 /* request fifo */
94 struct talitos_request *fifo;
95
96 /* number of requests pending in channel h/w fifo */
97 atomic_t submit_count ____cacheline_aligned;
98
99 /* request submission (head) lock */
100 spinlock_t head_lock ____cacheline_aligned;
101 /* index to next free descriptor request */
102 int head;
103
104 /* request release (tail) lock */
105 spinlock_t tail_lock ____cacheline_aligned;
106 /* index to next in-progress/done descriptor request */
107 int tail;
108};
109
110struct talitos_private {
111 struct device *dev;
112 struct platform_device *ofdev;
113 void __iomem *reg;
LEROY Christophe5fa7fa12015-04-17 16:32:11 +0200114 void __iomem *reg_deu;
115 void __iomem *reg_aesu;
116 void __iomem *reg_mdeu;
117 void __iomem *reg_afeu;
118 void __iomem *reg_rngu;
119 void __iomem *reg_pkeu;
120 void __iomem *reg_keu;
121 void __iomem *reg_crcu;
Horia Geantad1a0eb92012-07-03 19:16:51 +0300122 int irq[2];
123
124 /* SEC global registers lock */
125 spinlock_t reg_lock ____cacheline_aligned;
126
127 /* SEC version geometry (from device tree node) */
128 unsigned int num_channels;
129 unsigned int chfifo_len;
130 unsigned int exec_units;
131 unsigned int desc_types;
132
133 /* SEC Compatibility info */
134 unsigned long features;
135
136 /*
137 * length of the request fifo
138 * fifo_len is chfifo_len rounded up to next power of 2
139 * so we can use bitwise ops to wrap
140 */
141 unsigned int fifo_len;
142
143 struct talitos_channel *chan;
144
145 /* next channel to be assigned next incoming descriptor */
146 atomic_t last_chan ____cacheline_aligned;
147
148 /* request callback tasklet */
149 struct tasklet_struct done_task[2];
150
151 /* list of registered algorithms */
152 struct list_head alg_list;
153
154 /* hwrng device */
155 struct hwrng rng;
156};
157
Horia Geanta865d5062012-07-03 19:16:52 +0300158extern int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
159 void (*callback)(struct device *dev,
160 struct talitos_desc *desc,
161 void *context, int error),
162 void *context);
163
Horia Geantad1a0eb92012-07-03 19:16:51 +0300164/* .features flag */
165#define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
166#define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
167#define TALITOS_FTR_SHA224_HWINIT 0x00000004
168#define TALITOS_FTR_HMAC_OK 0x00000008
LEROY Christophe21590882015-04-17 16:32:05 +0200169#define TALITOS_FTR_SEC1 0x00000010
170
171/*
172 * If both CONFIG_CRYPTO_DEV_TALITOS1 and CONFIG_CRYPTO_DEV_TALITOS2 are
173 * defined, we check the features which are set according to the device tree.
174 * Otherwise, we answer true or false directly
175 */
176static inline bool has_ftr_sec1(struct talitos_private *priv)
177{
178#if defined(CONFIG_CRYPTO_DEV_TALITOS1) && defined(CONFIG_CRYPTO_DEV_TALITOS2)
179 return priv->features & TALITOS_FTR_SEC1 ? true : false;
180#elif defined(CONFIG_CRYPTO_DEV_TALITOS1)
181 return true;
182#else
183 return false;
184#endif
185}
Horia Geantad1a0eb92012-07-03 19:16:51 +0300186
Kim Phillips9c4a7962008-06-23 19:50:15 +0800187/*
188 * TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register
189 */
190
191/* global register offset addresses */
192#define TALITOS_MCR 0x1030 /* master control register */
Kim Phillipsc3e337f2011-11-21 16:13:27 +0800193#define TALITOS_MCR_RCA0 (1 << 15) /* remap channel 0 */
194#define TALITOS_MCR_RCA1 (1 << 14) /* remap channel 1 */
195#define TALITOS_MCR_RCA2 (1 << 13) /* remap channel 2 */
196#define TALITOS_MCR_RCA3 (1 << 12) /* remap channel 3 */
Kim Phillips9c4a7962008-06-23 19:50:15 +0800197#define TALITOS_MCR_SWR 0x1 /* s/w reset */
Kim Phillipsc3e337f2011-11-21 16:13:27 +0800198#define TALITOS_MCR_LO 0x1034
Kim Phillips9c4a7962008-06-23 19:50:15 +0800199#define TALITOS_IMR 0x1008 /* interrupt mask register */
Lee Nipper1c2e8812008-10-12 20:29:34 +0800200#define TALITOS_IMR_INIT 0x100ff /* enable channel IRQs */
201#define TALITOS_IMR_DONE 0x00055 /* done IRQs */
Kim Phillips9c4a7962008-06-23 19:50:15 +0800202#define TALITOS_IMR_LO 0x100C
203#define TALITOS_IMR_LO_INIT 0x20000 /* allow RNGU error IRQs */
204#define TALITOS_ISR 0x1010 /* interrupt status register */
Kim Phillipsc3e337f2011-11-21 16:13:27 +0800205#define TALITOS_ISR_4CHERR 0xaa /* 4 channel errors mask */
206#define TALITOS_ISR_4CHDONE 0x55 /* 4 channel done mask */
207#define TALITOS_ISR_CH_0_2_ERR 0x22 /* channels 0, 2 errors mask */
208#define TALITOS_ISR_CH_0_2_DONE 0x11 /* channels 0, 2 done mask */
209#define TALITOS_ISR_CH_1_3_ERR 0x88 /* channels 1, 3 errors mask */
210#define TALITOS_ISR_CH_1_3_DONE 0x44 /* channels 1, 3 done mask */
Kim Phillips9c4a7962008-06-23 19:50:15 +0800211#define TALITOS_ISR_LO 0x1014
212#define TALITOS_ICR 0x1018 /* interrupt clear register */
213#define TALITOS_ICR_LO 0x101C
214
215/* channel register address stride */
Kim Phillipsad42d5f2011-11-21 16:13:27 +0800216#define TALITOS_CH_BASE_OFFSET 0x1000 /* default channel map base */
LEROY Christophe5fa7fa12015-04-17 16:32:11 +0200217#define TALITOS1_CH_STRIDE 0x1000
218#define TALITOS2_CH_STRIDE 0x100
Kim Phillips9c4a7962008-06-23 19:50:15 +0800219
220/* channel configuration register */
Kim Phillipsad42d5f2011-11-21 16:13:27 +0800221#define TALITOS_CCCR 0x8
Kim Phillips9c4a7962008-06-23 19:50:15 +0800222#define TALITOS_CCCR_CONT 0x2 /* channel continue */
223#define TALITOS_CCCR_RESET 0x1 /* channel reset */
Kim Phillipsad42d5f2011-11-21 16:13:27 +0800224#define TALITOS_CCCR_LO 0xc
Kim Phillipsfe5720e2008-10-12 20:33:14 +0800225#define TALITOS_CCCR_LO_IWSE 0x80 /* chan. ICCR writeback enab. */
Kim Phillips81eb0242009-08-13 11:51:51 +1000226#define TALITOS_CCCR_LO_EAE 0x20 /* extended address enable */
Kim Phillips9c4a7962008-06-23 19:50:15 +0800227#define TALITOS_CCCR_LO_CDWE 0x10 /* chan. done writeback enab. */
228#define TALITOS_CCCR_LO_NT 0x4 /* notification type */
229#define TALITOS_CCCR_LO_CDIE 0x2 /* channel done IRQ enable */
230
231/* CCPSR: channel pointer status register */
Kim Phillipsad42d5f2011-11-21 16:13:27 +0800232#define TALITOS_CCPSR 0x10
233#define TALITOS_CCPSR_LO 0x14
Kim Phillips9c4a7962008-06-23 19:50:15 +0800234#define TALITOS_CCPSR_LO_DOF 0x8000 /* double FF write oflow error */
235#define TALITOS_CCPSR_LO_SOF 0x4000 /* single FF write oflow error */
236#define TALITOS_CCPSR_LO_MDTE 0x2000 /* master data transfer error */
237#define TALITOS_CCPSR_LO_SGDLZ 0x1000 /* s/g data len zero error */
238#define TALITOS_CCPSR_LO_FPZ 0x0800 /* fetch ptr zero error */
239#define TALITOS_CCPSR_LO_IDH 0x0400 /* illegal desc hdr error */
240#define TALITOS_CCPSR_LO_IEU 0x0200 /* invalid EU error */
241#define TALITOS_CCPSR_LO_EU 0x0100 /* EU error detected */
242#define TALITOS_CCPSR_LO_GB 0x0080 /* gather boundary error */
243#define TALITOS_CCPSR_LO_GRL 0x0040 /* gather return/length error */
244#define TALITOS_CCPSR_LO_SB 0x0020 /* scatter boundary error */
245#define TALITOS_CCPSR_LO_SRL 0x0010 /* scatter return/length error */
246
247/* channel fetch fifo register */
Kim Phillipsad42d5f2011-11-21 16:13:27 +0800248#define TALITOS_FF 0x48
249#define TALITOS_FF_LO 0x4c
Kim Phillips9c4a7962008-06-23 19:50:15 +0800250
251/* current descriptor pointer register */
Kim Phillipsad42d5f2011-11-21 16:13:27 +0800252#define TALITOS_CDPR 0x40
253#define TALITOS_CDPR_LO 0x44
Kim Phillips9c4a7962008-06-23 19:50:15 +0800254
255/* descriptor buffer register */
Kim Phillipsad42d5f2011-11-21 16:13:27 +0800256#define TALITOS_DESCBUF 0x80
257#define TALITOS_DESCBUF_LO 0x84
Kim Phillips9c4a7962008-06-23 19:50:15 +0800258
259/* gather link table */
Kim Phillipsad42d5f2011-11-21 16:13:27 +0800260#define TALITOS_GATHER 0xc0
261#define TALITOS_GATHER_LO 0xc4
Kim Phillips9c4a7962008-06-23 19:50:15 +0800262
263/* scatter link table */
Kim Phillipsad42d5f2011-11-21 16:13:27 +0800264#define TALITOS_SCATTER 0xe0
265#define TALITOS_SCATTER_LO 0xe4
Kim Phillips9c4a7962008-06-23 19:50:15 +0800266
LEROY Christophe5fa7fa12015-04-17 16:32:11 +0200267/* execution unit registers base */
268#define TALITOS2_DEU 0x2000
269#define TALITOS2_AESU 0x4000
270#define TALITOS2_MDEU 0x6000
271#define TALITOS2_AFEU 0x8000
272#define TALITOS2_RNGU 0xa000
273#define TALITOS2_PKEU 0xc000
274#define TALITOS2_KEU 0xe000
275#define TALITOS2_CRCU 0xf000
276
277#define TALITOS12_AESU 0x4000
278#define TALITOS12_DEU 0x5000
279#define TALITOS12_MDEU 0x6000
280
281#define TALITOS10_AFEU 0x8000
282#define TALITOS10_DEU 0xa000
283#define TALITOS10_MDEU 0xc000
284#define TALITOS10_RNGU 0xe000
285#define TALITOS10_PKEU 0x10000
286#define TALITOS10_AESU 0x12000
287
Kim Phillips9c4a7962008-06-23 19:50:15 +0800288/* execution unit interrupt status registers */
LEROY Christophe5fa7fa12015-04-17 16:32:11 +0200289#define TALITOS_EUDSR 0x10 /* data size */
290#define TALITOS_EUDSR_LO 0x14
291#define TALITOS_EURCR 0x18 /* reset control*/
292#define TALITOS_EURCR_LO 0x1c
293#define TALITOS_EUSR 0x28 /* rng status */
294#define TALITOS_EUSR_LO 0x2c
295#define TALITOS_EUISR 0x30
296#define TALITOS_EUISR_LO 0x34
297#define TALITOS_EUICR 0x38 /* int. control */
298#define TALITOS_EUICR_LO 0x3c
299#define TALITOS_EU_FIFO 0x800 /* output FIFO */
300#define TALITOS_EU_FIFO_LO 0x804 /* output FIFO */
301/* message digest unit */
Kim Phillipsfe5720e2008-10-12 20:33:14 +0800302#define TALITOS_MDEUICR_LO_ICE 0x4000 /* integrity check IRQ enable */
LEROY Christophe5fa7fa12015-04-17 16:32:11 +0200303/* random number unit */
Kim Phillips9c4a7962008-06-23 19:50:15 +0800304#define TALITOS_RNGUSR_LO_RD 0x1 /* reset done */
305#define TALITOS_RNGUSR_LO_OFL 0xff0000/* output FIFO length */
Kim Phillips9c4a7962008-06-23 19:50:15 +0800306#define TALITOS_RNGURCR_LO_SR 0x1 /* software reset */
Kim Phillips9c4a7962008-06-23 19:50:15 +0800307
Lee Nipper497f2e62010-05-19 19:20:36 +1000308#define TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256 0x28
309#define TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512 0x48
310
Kim Phillips9c4a7962008-06-23 19:50:15 +0800311/*
312 * talitos descriptor header (hdr) bits
313 */
314
315/* written back when done */
Harvey Harrisondad3df22008-11-28 20:49:19 +0800316#define DESC_HDR_DONE cpu_to_be32(0xff000000)
317#define DESC_HDR_LO_ICCR1_MASK cpu_to_be32(0x00180000)
318#define DESC_HDR_LO_ICCR1_PASS cpu_to_be32(0x00080000)
319#define DESC_HDR_LO_ICCR1_FAIL cpu_to_be32(0x00100000)
Kim Phillips9c4a7962008-06-23 19:50:15 +0800320
321/* primary execution unit select */
Harvey Harrisondad3df22008-11-28 20:49:19 +0800322#define DESC_HDR_SEL0_MASK cpu_to_be32(0xf0000000)
323#define DESC_HDR_SEL0_AFEU cpu_to_be32(0x10000000)
324#define DESC_HDR_SEL0_DEU cpu_to_be32(0x20000000)
325#define DESC_HDR_SEL0_MDEUA cpu_to_be32(0x30000000)
326#define DESC_HDR_SEL0_MDEUB cpu_to_be32(0xb0000000)
327#define DESC_HDR_SEL0_RNG cpu_to_be32(0x40000000)
328#define DESC_HDR_SEL0_PKEU cpu_to_be32(0x50000000)
329#define DESC_HDR_SEL0_AESU cpu_to_be32(0x60000000)
330#define DESC_HDR_SEL0_KEU cpu_to_be32(0x70000000)
331#define DESC_HDR_SEL0_CRCU cpu_to_be32(0x80000000)
Kim Phillips9c4a7962008-06-23 19:50:15 +0800332
333/* primary execution unit mode (MODE0) and derivatives */
Harvey Harrisondad3df22008-11-28 20:49:19 +0800334#define DESC_HDR_MODE0_ENCRYPT cpu_to_be32(0x00100000)
335#define DESC_HDR_MODE0_AESU_CBC cpu_to_be32(0x00200000)
336#define DESC_HDR_MODE0_DEU_CBC cpu_to_be32(0x00400000)
337#define DESC_HDR_MODE0_DEU_3DES cpu_to_be32(0x00200000)
Lee Nipper497f2e62010-05-19 19:20:36 +1000338#define DESC_HDR_MODE0_MDEU_CONT cpu_to_be32(0x08000000)
Harvey Harrisondad3df22008-11-28 20:49:19 +0800339#define DESC_HDR_MODE0_MDEU_INIT cpu_to_be32(0x01000000)
340#define DESC_HDR_MODE0_MDEU_HMAC cpu_to_be32(0x00800000)
341#define DESC_HDR_MODE0_MDEU_PAD cpu_to_be32(0x00400000)
Kim Phillips60f208d72010-05-19 19:21:53 +1000342#define DESC_HDR_MODE0_MDEU_SHA224 cpu_to_be32(0x00300000)
Harvey Harrisondad3df22008-11-28 20:49:19 +0800343#define DESC_HDR_MODE0_MDEU_MD5 cpu_to_be32(0x00200000)
344#define DESC_HDR_MODE0_MDEU_SHA256 cpu_to_be32(0x00100000)
345#define DESC_HDR_MODE0_MDEU_SHA1 cpu_to_be32(0x00000000)
Lee Nipper497f2e62010-05-19 19:20:36 +1000346#define DESC_HDR_MODE0_MDEUB_SHA384 cpu_to_be32(0x00000000)
347#define DESC_HDR_MODE0_MDEUB_SHA512 cpu_to_be32(0x00200000)
Kim Phillips9c4a7962008-06-23 19:50:15 +0800348#define DESC_HDR_MODE0_MDEU_MD5_HMAC (DESC_HDR_MODE0_MDEU_MD5 | \
349 DESC_HDR_MODE0_MDEU_HMAC)
350#define DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 | \
351 DESC_HDR_MODE0_MDEU_HMAC)
352#define DESC_HDR_MODE0_MDEU_SHA1_HMAC (DESC_HDR_MODE0_MDEU_SHA1 | \
353 DESC_HDR_MODE0_MDEU_HMAC)
354
355/* secondary execution unit select (SEL1) */
Harvey Harrisondad3df22008-11-28 20:49:19 +0800356#define DESC_HDR_SEL1_MASK cpu_to_be32(0x000f0000)
357#define DESC_HDR_SEL1_MDEUA cpu_to_be32(0x00030000)
358#define DESC_HDR_SEL1_MDEUB cpu_to_be32(0x000b0000)
359#define DESC_HDR_SEL1_CRCU cpu_to_be32(0x00080000)
Kim Phillips9c4a7962008-06-23 19:50:15 +0800360
361/* secondary execution unit mode (MODE1) and derivatives */
Harvey Harrisondad3df22008-11-28 20:49:19 +0800362#define DESC_HDR_MODE1_MDEU_CICV cpu_to_be32(0x00004000)
363#define DESC_HDR_MODE1_MDEU_INIT cpu_to_be32(0x00001000)
364#define DESC_HDR_MODE1_MDEU_HMAC cpu_to_be32(0x00000800)
365#define DESC_HDR_MODE1_MDEU_PAD cpu_to_be32(0x00000400)
Kim Phillips60f208d72010-05-19 19:21:53 +1000366#define DESC_HDR_MODE1_MDEU_SHA224 cpu_to_be32(0x00000300)
Harvey Harrisondad3df22008-11-28 20:49:19 +0800367#define DESC_HDR_MODE1_MDEU_MD5 cpu_to_be32(0x00000200)
368#define DESC_HDR_MODE1_MDEU_SHA256 cpu_to_be32(0x00000100)
369#define DESC_HDR_MODE1_MDEU_SHA1 cpu_to_be32(0x00000000)
Lee Nipper497f2e62010-05-19 19:20:36 +1000370#define DESC_HDR_MODE1_MDEUB_SHA384 cpu_to_be32(0x00000000)
371#define DESC_HDR_MODE1_MDEUB_SHA512 cpu_to_be32(0x00000200)
Kim Phillips9c4a7962008-06-23 19:50:15 +0800372#define DESC_HDR_MODE1_MDEU_MD5_HMAC (DESC_HDR_MODE1_MDEU_MD5 | \
373 DESC_HDR_MODE1_MDEU_HMAC)
374#define DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 | \
375 DESC_HDR_MODE1_MDEU_HMAC)
376#define DESC_HDR_MODE1_MDEU_SHA1_HMAC (DESC_HDR_MODE1_MDEU_SHA1 | \
377 DESC_HDR_MODE1_MDEU_HMAC)
Horia Geanta357fb602012-07-03 19:16:53 +0300378#define DESC_HDR_MODE1_MDEU_SHA224_HMAC (DESC_HDR_MODE1_MDEU_SHA224 | \
379 DESC_HDR_MODE1_MDEU_HMAC)
380#define DESC_HDR_MODE1_MDEUB_SHA384_HMAC (DESC_HDR_MODE1_MDEUB_SHA384 | \
381 DESC_HDR_MODE1_MDEU_HMAC)
382#define DESC_HDR_MODE1_MDEUB_SHA512_HMAC (DESC_HDR_MODE1_MDEUB_SHA512 | \
383 DESC_HDR_MODE1_MDEU_HMAC)
Kim Phillips9c4a7962008-06-23 19:50:15 +0800384
385/* direction of overall data flow (DIR) */
Harvey Harrisondad3df22008-11-28 20:49:19 +0800386#define DESC_HDR_DIR_INBOUND cpu_to_be32(0x00000002)
Kim Phillips9c4a7962008-06-23 19:50:15 +0800387
388/* request done notification (DN) */
Harvey Harrisondad3df22008-11-28 20:49:19 +0800389#define DESC_HDR_DONE_NOTIFY cpu_to_be32(0x00000001)
Kim Phillips9c4a7962008-06-23 19:50:15 +0800390
391/* descriptor types */
Harvey Harrisondad3df22008-11-28 20:49:19 +0800392#define DESC_HDR_TYPE_AESU_CTR_NONSNOOP cpu_to_be32(0 << 3)
393#define DESC_HDR_TYPE_IPSEC_ESP cpu_to_be32(1 << 3)
394#define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU cpu_to_be32(2 << 3)
395#define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU cpu_to_be32(4 << 3)
Kim Phillips9c4a7962008-06-23 19:50:15 +0800396
397/* link table extent field bits */
398#define DESC_PTR_LNKTBL_JUMP 0x80
399#define DESC_PTR_LNKTBL_RETURN 0x02
400#define DESC_PTR_LNKTBL_NEXT 0x01