blob: 872d141ca1190cb62d013a74e3eedb797fdb140f [file] [log] [blame]
Sonic Zhang22a82622012-05-16 17:24:33 +08001/* mach/dma.h - arch-specific DMA defines
2 *
3 * Copyright 2011 Analog Devices Inc.
4 *
5 * Licensed under the GPL-2 or later.
6 */
7
8#ifndef _MACH_DMA_H_
9#define _MACH_DMA_H_
10
11#define CH_SPORT0_TX 0
12#define CH_SPORT0_RX 1
13#define CH_SPORT1_TX 2
14#define CH_SPORT1_RX 3
15#define CH_SPORT2_TX 4
16#define CH_SPORT2_RX 5
17#define CH_SPI0_TX 6
18#define CH_SPI0_RX 7
19#define CH_SPI1_TX 8
20#define CH_SPI1_RX 9
21#define CH_RSI 10
22#define CH_SDU 11
23#define CH_LP0 13
24#define CH_LP1 14
25#define CH_LP2 15
26#define CH_LP3 16
27#define CH_UART0_TX 17
28#define CH_UART0_RX 18
29#define CH_UART1_TX 19
30#define CH_UART1_RX 20
31#define CH_MEM_STREAM0_SRC_CRC0 21
32#define CH_MEM_STREAM0_SRC CH_MEM_STREAM0_SRC_CRC0
33#define CH_MEM_STREAM0_DEST_CRC0 22
34#define CH_MEM_STREAM0_DEST CH_MEM_STREAM0_DEST_CRC0
35#define CH_MEM_STREAM1_SRC_CRC1 23
36#define CH_MEM_STREAM1_SRC CH_MEM_STREAM1_SRC_CRC1
37#define CH_MEM_STREAM1_DEST_CRC1 24
38#define CH_MEM_STREAM1_DEST CH_MEM_STREAM1_DEST_CRC1
39#define CH_MEM_STREAM2_SRC 25
40#define CH_MEM_STREAM2_DEST 26
41#define CH_MEM_STREAM3_SRC 27
42#define CH_MEM_STREAM3_DEST 28
43#define CH_EPPI0_CH0 29
44#define CH_EPPI0_CH1 30
45#define CH_EPPI1_CH0 31
46#define CH_EPPI1_CH1 32
47#define CH_EPPI2_CH0 33
48#define CH_EPPI2_CH1 34
49#define CH_PIXC_CH0 35
50#define CH_PIXC_CH1 36
51#define CH_PIXC_CH2 37
52#define CH_PVP_CPDOB 38
53#define CH_PVP_CPDOC 39
54#define CH_PVP_CPSTAT 40
55#define CH_PVP_CPCI 41
56#define CH_PVP_MPDO 42
57#define CH_PVP_MPDI 43
58#define CH_PVP_MPSTAT 44
59#define CH_PVP_MPCI 45
60#define CH_PVP_CPDOA 46
61
62#define MAX_DMA_CHANNELS 47
63#define MAX_DMA_SUSPEND_CHANNELS 0
64#define DMA_MMR_SIZE_32
65
66#define bfin_read_MDMA_S0_CONFIG bfin_read_MDMA0_SRC_CRC0_CONFIG
67#define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA0_SRC_CRC0_CONFIG
68#define bfin_read_MDMA_S0_IRQ_STATUS bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS
69#define bfin_write_MDMA_S0_IRQ_STATUS bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS
70#define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA0_SRC_CRC0_START_ADDR
71#define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA0_SRC_CRC0_X_COUNT
72#define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA0_SRC_CRC0_X_MODIFY
73#define bfin_write_MDMA_S0_Y_COUNT bfin_write_MDMA0_SRC_CRC0_Y_COUNT
74#define bfin_write_MDMA_S0_Y_MODIFY bfin_write_MDMA0_SRC_CRC0_Y_MODIFY
75#define bfin_read_MDMA_D0_CONFIG bfin_read_MDMA0_DEST_CRC0_CONFIG
76#define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA0_DEST_CRC0_CONFIG
77#define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS
78#define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS
79#define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA0_DEST_CRC0_START_ADDR
80#define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA0_DEST_CRC0_X_COUNT
81#define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA0_DEST_CRC0_X_MODIFY
82#define bfin_write_MDMA_D0_Y_COUNT bfin_write_MDMA0_DEST_CRC0_Y_COUNT
83#define bfin_write_MDMA_D0_Y_MODIFY bfin_write_MDMA0_DEST_CRC0_Y_MODIFY
84
85#define bfin_read_MDMA_S1_CONFIG bfin_read_MDMA1_SRC_CRC1_CONFIG
86#define bfin_write_MDMA_S1_CONFIG bfin_write_MDMA1_SRC_CRC1_CONFIG
87#define bfin_read_MDMA_D1_CONFIG bfin_read_MDMA1_DEST_CRC1_CONFIG
88#define bfin_write_MDMA_D1_CONFIG bfin_write_MDMA1_DEST_CRC1_CONFIG
89#define bfin_read_MDMA_D1_IRQ_STATUS bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS
90#define bfin_write_MDMA_D1_IRQ_STATUS bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS
91
92#define bfin_read_MDMA_S3_CONFIG bfin_read_MDMA3_SRC_CONFIG
93#define bfin_write_MDMA_S3_CONFIG bfin_write_MDMA3_SRC_CONFIG
94#define bfin_read_MDMA_S3_IRQ_STATUS bfin_read_MDMA3_SRC_IRQ_STATUS
95#define bfin_write_MDMA_S3_IRQ_STATUS bfin_write_MDMA3_SRC_IRQ_STATUS
96#define bfin_write_MDMA_S3_START_ADDR bfin_write_MDMA3_SRC_START_ADDR
97#define bfin_write_MDMA_S3_X_COUNT bfin_write_MDMA3_SRC_X_COUNT
98#define bfin_write_MDMA_S3_X_MODIFY bfin_write_MDMA3_SRC_X_MODIFY
99#define bfin_write_MDMA_S3_Y_COUNT bfin_write_MDMA3_SRC_Y_COUNT
100#define bfin_write_MDMA_S3_Y_MODIFY bfin_write_MDMA3_SRC_Y_MODIFY
101#define bfin_read_MDMA_D3_CONFIG bfin_read_MDMA3_DEST_CONFIG
102#define bfin_write_MDMA_D3_CONFIG bfin_write_MDMA3_DEST_CONFIG
103#define bfin_read_MDMA_D3_IRQ_STATUS bfin_read_MDMA3_DEST_IRQ_STATUS
104#define bfin_write_MDMA_D3_IRQ_STATUS bfin_write_MDMA3_DEST_IRQ_STATUS
105#define bfin_write_MDMA_D3_START_ADDR bfin_write_MDMA3_DEST_START_ADDR
106#define bfin_write_MDMA_D3_X_COUNT bfin_write_MDMA3_DEST_X_COUNT
107#define bfin_write_MDMA_D3_X_MODIFY bfin_write_MDMA3_DEST_X_MODIFY
108#define bfin_write_MDMA_D3_Y_COUNT bfin_write_MDMA3_DEST_Y_COUNT
109#define bfin_write_MDMA_D3_Y_MODIFY bfin_write_MDMA3_DEST_Y_MODIFY
110
111#define MDMA_S0_NEXT_DESC_PTR MDMA0_SRC_CRC0_NEXT_DESC_PTR
112#define MDMA_D0_NEXT_DESC_PTR MDMA0_DEST_CRC0_NEXT_DESC_PTR
113#define MDMA_S1_NEXT_DESC_PTR MDMA1_SRC_CRC1_NEXT_DESC_PTR
114#define MDMA_D1_NEXT_DESC_PTR MDMA1_DEST_CRC1_NEXT_DESC_PTR
115
116#endif