Thomas Gleixner | caab277 | 2019-06-03 07:44:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Low-level exception handling code |
| 4 | * |
| 5 | * Copyright (C) 2012 ARM Ltd. |
| 6 | * Authors: Catalin Marinas <catalin.marinas@arm.com> |
| 7 | * Will Deacon <will.deacon@arm.com> |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
Marc Zyngier | 8e29062 | 2018-05-29 13:11:06 +0100 | [diff] [blame] | 10 | #include <linux/arm-smccc.h> |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 11 | #include <linux/init.h> |
| 12 | #include <linux/linkage.h> |
| 13 | |
Marc Zyngier | 8d883b2 | 2015-06-01 10:47:41 +0100 | [diff] [blame] | 14 | #include <asm/alternative.h> |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 15 | #include <asm/assembler.h> |
| 16 | #include <asm/asm-offsets.h> |
Kristina Martsenko | be12984 | 2020-03-13 14:34:51 +0530 | [diff] [blame] | 17 | #include <asm/asm_pointer_auth.h> |
Will Deacon | 5f1f7f6 | 2020-06-30 13:53:07 +0100 | [diff] [blame] | 18 | #include <asm/bug.h> |
Will Deacon | 905e8c5 | 2015-03-23 19:07:02 +0000 | [diff] [blame] | 19 | #include <asm/cpufeature.h> |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 20 | #include <asm/errno.h> |
Marc Zyngier | 5c1ce6f | 2013-04-08 17:17:03 +0100 | [diff] [blame] | 21 | #include <asm/esr.h> |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 22 | #include <asm/irq.h> |
Will Deacon | c7b9ada | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 23 | #include <asm/memory.h> |
| 24 | #include <asm/mmu.h> |
Yury Norov | eef94a3 | 2017-08-31 11:30:50 +0300 | [diff] [blame] | 25 | #include <asm/processor.h> |
Catalin Marinas | 39bc88e | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 26 | #include <asm/ptrace.h> |
Sami Tolvanen | 5287569 | 2020-04-27 09:00:16 -0700 | [diff] [blame] | 27 | #include <asm/scs.h> |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 28 | #include <asm/thread_info.h> |
Al Viro | b4b8664 | 2016-12-26 04:10:19 -0500 | [diff] [blame] | 29 | #include <asm/asm-uaccess.h> |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 30 | #include <asm/unistd.h> |
| 31 | |
Mark Rutland | baaa723 | 2018-07-11 14:56:48 +0100 | [diff] [blame] | 32 | .macro clear_gp_regs |
| 33 | .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29 |
| 34 | mov x\n, xzr |
| 35 | .endr |
| 36 | .endm |
| 37 | |
Mark Rutland | ec841aa | 2021-06-07 10:46:18 +0100 | [diff] [blame] | 38 | .macro kernel_ventry, el:req, ht:req, regsize:req, label:req |
Mark Rutland | b11e575 | 2017-07-19 17:24:49 +0100 | [diff] [blame] | 39 | .align 7 |
James Morse | 4330e2c | 2021-11-17 15:15:26 +0000 | [diff] [blame] | 40 | .Lventry_start\@: |
Will Deacon | 4bf3286 | 2017-11-14 14:24:29 +0000 | [diff] [blame] | 41 | .if \el == 0 |
James Morse | d739da1 | 2021-11-24 15:36:12 +0000 | [diff] [blame] | 42 | /* |
| 43 | * This must be the first instruction of the EL0 vector entries. It is |
| 44 | * skipped by the trampoline vectors, to trigger the cleanup. |
| 45 | */ |
| 46 | b .Lskip_tramp_vectors_cleanup\@ |
Will Deacon | 4bf3286 | 2017-11-14 14:24:29 +0000 | [diff] [blame] | 47 | .if \regsize == 64 |
| 48 | mrs x30, tpidrro_el0 |
| 49 | msr tpidrro_el0, xzr |
| 50 | .else |
| 51 | mov x30, xzr |
| 52 | .endif |
James Morse | d739da1 | 2021-11-24 15:36:12 +0000 | [diff] [blame] | 53 | .Lskip_tramp_vectors_cleanup\@: |
Julien Thierry | 108eae2 | 2020-01-09 16:02:59 +0000 | [diff] [blame] | 54 | .endif |
Will Deacon | 4bf3286 | 2017-11-14 14:24:29 +0000 | [diff] [blame] | 55 | |
Jianlin Lv | 71e7018 | 2021-01-12 09:58:13 +0800 | [diff] [blame] | 56 | sub sp, sp, #PT_REGS_SIZE |
Mark Rutland | 872d832 | 2017-07-14 20:30:35 +0100 | [diff] [blame] | 57 | #ifdef CONFIG_VMAP_STACK |
| 58 | /* |
| 59 | * Test whether the SP has overflowed, without corrupting a GPR. |
Heyi Guo | de85804 | 2019-12-02 19:37:02 +0800 | [diff] [blame] | 60 | * Task and IRQ stacks are aligned so that SP & (1 << THREAD_SHIFT) |
| 61 | * should always be zero. |
Mark Rutland | 872d832 | 2017-07-14 20:30:35 +0100 | [diff] [blame] | 62 | */ |
| 63 | add sp, sp, x0 // sp' = sp + x0 |
| 64 | sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp |
| 65 | tbnz x0, #THREAD_SHIFT, 0f |
| 66 | sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0 |
| 67 | sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp |
Mark Rutland | ec841aa | 2021-06-07 10:46:18 +0100 | [diff] [blame] | 68 | b el\el\ht\()_\regsize\()_\label |
Mark Rutland | 872d832 | 2017-07-14 20:30:35 +0100 | [diff] [blame] | 69 | |
| 70 | 0: |
| 71 | /* |
| 72 | * Either we've just detected an overflow, or we've taken an exception |
| 73 | * while on the overflow stack. Either way, we won't return to |
| 74 | * userspace, and can clobber EL0 registers to free up GPRs. |
| 75 | */ |
| 76 | |
Jianlin Lv | 71e7018 | 2021-01-12 09:58:13 +0800 | [diff] [blame] | 77 | /* Stash the original SP (minus PT_REGS_SIZE) in tpidr_el0. */ |
Mark Rutland | 872d832 | 2017-07-14 20:30:35 +0100 | [diff] [blame] | 78 | msr tpidr_el0, x0 |
| 79 | |
| 80 | /* Recover the original x0 value and stash it in tpidrro_el0 */ |
| 81 | sub x0, sp, x0 |
| 82 | msr tpidrro_el0, x0 |
| 83 | |
| 84 | /* Switch to the overflow stack */ |
| 85 | adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0 |
| 86 | |
| 87 | /* |
| 88 | * Check whether we were already on the overflow stack. This may happen |
| 89 | * after panic() re-enables interrupts. |
| 90 | */ |
| 91 | mrs x0, tpidr_el0 // sp of interrupted context |
| 92 | sub x0, sp, x0 // delta with top of overflow stack |
| 93 | tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range? |
| 94 | b.ne __bad_stack // no? -> bad stack pointer |
| 95 | |
| 96 | /* We were already on the overflow stack. Restore sp/x0 and carry on. */ |
| 97 | sub sp, sp, x0 |
| 98 | mrs x0, tpidrro_el0 |
| 99 | #endif |
Mark Rutland | ec841aa | 2021-06-07 10:46:18 +0100 | [diff] [blame] | 100 | b el\el\ht\()_\regsize\()_\label |
James Morse | 4330e2c | 2021-11-17 15:15:26 +0000 | [diff] [blame] | 101 | .org .Lventry_start\@ + 128 // Did we overflow the ventry slot? |
Mark Rutland | b11e575 | 2017-07-19 17:24:49 +0100 | [diff] [blame] | 102 | .endm |
| 103 | |
Ard Biesheuvel | 211ceca | 2023-04-18 16:36:04 +0200 | [diff] [blame] | 104 | .macro tramp_alias, dst, sym |
| 105 | .set .Lalias\@, TRAMP_VALIAS + \sym - .entry.tramp.text |
| 106 | movz \dst, :abs_g2_s:.Lalias\@ |
| 107 | movk \dst, :abs_g1_nc:.Lalias\@ |
| 108 | movk \dst, :abs_g0_nc:.Lalias\@ |
Mark Rutland | b11e575 | 2017-07-19 17:24:49 +0100 | [diff] [blame] | 109 | .endm |
| 110 | |
Will Deacon | 8c3001b | 2020-07-08 22:10:01 +0100 | [diff] [blame] | 111 | /* |
| 112 | * This macro corrupts x0-x3. It is the caller's duty to save/restore |
| 113 | * them if required. |
| 114 | */ |
Mark Rutland | 99ed3ed | 2018-07-11 14:56:47 +0100 | [diff] [blame] | 115 | .macro apply_ssbd, state, tmp1, tmp2 |
Mark Rutland | 4c0bd99 | 2022-09-12 17:22:08 +0100 | [diff] [blame] | 116 | alternative_cb ARM64_ALWAYS_SYSTEM, spectre_v4_patch_fw_mitigation_enable |
Will Deacon | c287620 | 2020-09-18 11:54:33 +0100 | [diff] [blame] | 117 | b .L__asm_ssbd_skip\@ // Patched to NOP |
Marc Zyngier | 986372c | 2018-05-29 13:11:11 +0100 | [diff] [blame] | 118 | alternative_cb_end |
Marc Zyngier | 5cf9ce6 | 2018-05-29 13:11:07 +0100 | [diff] [blame] | 119 | ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1 |
Mark Rutland | 99ed3ed | 2018-07-11 14:56:47 +0100 | [diff] [blame] | 120 | cbz \tmp2, .L__asm_ssbd_skip\@ |
Marc Zyngier | 9dd9614 | 2018-05-29 13:11:13 +0100 | [diff] [blame] | 121 | ldr \tmp2, [tsk, #TSK_TI_FLAGS] |
Mark Rutland | 99ed3ed | 2018-07-11 14:56:47 +0100 | [diff] [blame] | 122 | tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@ |
Marc Zyngier | 8e29062 | 2018-05-29 13:11:06 +0100 | [diff] [blame] | 123 | mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2 |
| 124 | mov w1, #\state |
Mark Rutland | 4c0bd99 | 2022-09-12 17:22:08 +0100 | [diff] [blame] | 125 | alternative_cb ARM64_ALWAYS_SYSTEM, smccc_patch_fw_mitigation_conduit |
Marc Zyngier | 8e29062 | 2018-05-29 13:11:06 +0100 | [diff] [blame] | 126 | nop // Patched to SMC/HVC #0 |
| 127 | alternative_cb_end |
Mark Rutland | 99ed3ed | 2018-07-11 14:56:47 +0100 | [diff] [blame] | 128 | .L__asm_ssbd_skip\@: |
Marc Zyngier | 8e29062 | 2018-05-29 13:11:06 +0100 | [diff] [blame] | 129 | .endm |
| 130 | |
Vincenzo Frascino | 637ec83 | 2019-09-16 11:51:17 +0100 | [diff] [blame] | 131 | /* Check for MTE asynchronous tag check faults */ |
Peter Collingbourne | 42b6b10 | 2021-07-08 19:35:32 -0700 | [diff] [blame] | 132 | .macro check_mte_async_tcf, tmp, ti_flags, thread_sctlr |
Vincenzo Frascino | 637ec83 | 2019-09-16 11:51:17 +0100 | [diff] [blame] | 133 | #ifdef CONFIG_ARM64_MTE |
Catalin Marinas | 2decad9 | 2021-04-09 18:37:10 +0100 | [diff] [blame] | 134 | .arch_extension lse |
Vincenzo Frascino | 637ec83 | 2019-09-16 11:51:17 +0100 | [diff] [blame] | 135 | alternative_if_not ARM64_MTE |
| 136 | b 1f |
| 137 | alternative_else_nop_endif |
Peter Collingbourne | 42b6b10 | 2021-07-08 19:35:32 -0700 | [diff] [blame] | 138 | /* |
| 139 | * Asynchronous tag check faults are only possible in ASYNC (2) or |
| 140 | * ASYM (3) modes. In each of these modes bit 1 of SCTLR_EL1.TCF0 is |
| 141 | * set, so skip the check if it is unset. |
| 142 | */ |
| 143 | tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f |
Vincenzo Frascino | 637ec83 | 2019-09-16 11:51:17 +0100 | [diff] [blame] | 144 | mrs_s \tmp, SYS_TFSRE0_EL1 |
| 145 | tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f |
| 146 | /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */ |
Catalin Marinas | 2decad9 | 2021-04-09 18:37:10 +0100 | [diff] [blame] | 147 | mov \tmp, #_TIF_MTE_ASYNC_FAULT |
| 148 | add \ti_flags, tsk, #TSK_TI_FLAGS |
| 149 | stset \tmp, [\ti_flags] |
Vincenzo Frascino | 637ec83 | 2019-09-16 11:51:17 +0100 | [diff] [blame] | 150 | 1: |
| 151 | #endif |
| 152 | .endm |
| 153 | |
| 154 | /* Clear the MTE asynchronous tag check faults */ |
Peter Collingbourne | 42b6b10 | 2021-07-08 19:35:32 -0700 | [diff] [blame] | 155 | .macro clear_mte_async_tcf thread_sctlr |
Vincenzo Frascino | 637ec83 | 2019-09-16 11:51:17 +0100 | [diff] [blame] | 156 | #ifdef CONFIG_ARM64_MTE |
| 157 | alternative_if ARM64_MTE |
Peter Collingbourne | 42b6b10 | 2021-07-08 19:35:32 -0700 | [diff] [blame] | 158 | /* See comment in check_mte_async_tcf above. */ |
| 159 | tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f |
Vincenzo Frascino | 637ec83 | 2019-09-16 11:51:17 +0100 | [diff] [blame] | 160 | dsb ish |
| 161 | msr_s SYS_TFSRE0_EL1, xzr |
Peter Collingbourne | 42b6b10 | 2021-07-08 19:35:32 -0700 | [diff] [blame] | 162 | 1: |
Vincenzo Frascino | 637ec83 | 2019-09-16 11:51:17 +0100 | [diff] [blame] | 163 | alternative_else_nop_endif |
| 164 | #endif |
| 165 | .endm |
| 166 | |
Peter Collingbourne | afdfd93 | 2021-07-13 18:36:38 -0700 | [diff] [blame] | 167 | .macro mte_set_gcr, mte_ctrl, tmp |
Vincenzo Frascino | bad1e1c | 2020-12-22 12:01:45 -0800 | [diff] [blame] | 168 | #ifdef CONFIG_ARM64_MTE |
Peter Collingbourne | afdfd93 | 2021-07-13 18:36:38 -0700 | [diff] [blame] | 169 | ubfx \tmp, \mte_ctrl, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16 |
| 170 | orr \tmp, \tmp, #SYS_GCR_EL1_RRND |
| 171 | msr_s SYS_GCR_EL1, \tmp |
Vincenzo Frascino | bad1e1c | 2020-12-22 12:01:45 -0800 | [diff] [blame] | 172 | #endif |
| 173 | .endm |
| 174 | |
| 175 | .macro mte_set_kernel_gcr, tmp, tmp2 |
| 176 | #ifdef CONFIG_KASAN_HW_TAGS |
Mark Rutland | 4c0bd99 | 2022-09-12 17:22:08 +0100 | [diff] [blame] | 177 | alternative_cb ARM64_ALWAYS_SYSTEM, kasan_hw_tags_enable |
Vincenzo Frascino | bad1e1c | 2020-12-22 12:01:45 -0800 | [diff] [blame] | 178 | b 1f |
Peter Collingbourne | e5af50a | 2021-09-23 18:06:55 -0700 | [diff] [blame] | 179 | alternative_cb_end |
Mark Rutland | 8286824 | 2021-07-14 15:38:42 +0100 | [diff] [blame] | 180 | mov \tmp, KERNEL_GCR_EL1 |
| 181 | msr_s SYS_GCR_EL1, \tmp |
Vincenzo Frascino | bad1e1c | 2020-12-22 12:01:45 -0800 | [diff] [blame] | 182 | 1: |
| 183 | #endif |
| 184 | .endm |
| 185 | |
| 186 | .macro mte_set_user_gcr, tsk, tmp, tmp2 |
Peter Collingbourne | e5af50a | 2021-09-23 18:06:55 -0700 | [diff] [blame] | 187 | #ifdef CONFIG_KASAN_HW_TAGS |
Mark Rutland | 4c0bd99 | 2022-09-12 17:22:08 +0100 | [diff] [blame] | 188 | alternative_cb ARM64_ALWAYS_SYSTEM, kasan_hw_tags_enable |
Vincenzo Frascino | bad1e1c | 2020-12-22 12:01:45 -0800 | [diff] [blame] | 189 | b 1f |
Peter Collingbourne | e5af50a | 2021-09-23 18:06:55 -0700 | [diff] [blame] | 190 | alternative_cb_end |
Peter Collingbourne | 638982a | 2021-07-27 13:52:55 -0700 | [diff] [blame] | 191 | ldr \tmp, [\tsk, #THREAD_MTE_CTRL] |
Vincenzo Frascino | bad1e1c | 2020-12-22 12:01:45 -0800 | [diff] [blame] | 192 | |
| 193 | mte_set_gcr \tmp, \tmp2 |
| 194 | 1: |
| 195 | #endif |
| 196 | .endm |
| 197 | |
Mark Rutland | b11e575 | 2017-07-19 17:24:49 +0100 | [diff] [blame] | 198 | .macro kernel_entry, el, regsize = 64 |
Ard Biesheuvel | 01ab991f | 2022-11-07 18:24:00 +0100 | [diff] [blame] | 199 | .if \el == 0 |
| 200 | alternative_insn nop, SET_PSTATE_DIT(1), ARM64_HAS_DIT |
| 201 | .endif |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 202 | .if \regsize == 32 |
| 203 | mov w0, w0 // zero upper 32 bits of x0 |
| 204 | .endif |
Will Deacon | 63648dd | 2014-09-29 12:26:41 +0100 | [diff] [blame] | 205 | stp x0, x1, [sp, #16 * 0] |
| 206 | stp x2, x3, [sp, #16 * 1] |
| 207 | stp x4, x5, [sp, #16 * 2] |
| 208 | stp x6, x7, [sp, #16 * 3] |
| 209 | stp x8, x9, [sp, #16 * 4] |
| 210 | stp x10, x11, [sp, #16 * 5] |
| 211 | stp x12, x13, [sp, #16 * 6] |
| 212 | stp x14, x15, [sp, #16 * 7] |
| 213 | stp x16, x17, [sp, #16 * 8] |
| 214 | stp x18, x19, [sp, #16 * 9] |
| 215 | stp x20, x21, [sp, #16 * 10] |
| 216 | stp x22, x23, [sp, #16 * 11] |
| 217 | stp x24, x25, [sp, #16 * 12] |
| 218 | stp x26, x27, [sp, #16 * 13] |
| 219 | stp x28, x29, [sp, #16 * 14] |
| 220 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 221 | .if \el == 0 |
Mark Rutland | baaa723 | 2018-07-11 14:56:48 +0100 | [diff] [blame] | 222 | clear_gp_regs |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 223 | mrs x21, sp_el0 |
Mark Rutland | 3e39341 | 2020-01-16 18:35:48 +0000 | [diff] [blame] | 224 | ldr_this_cpu tsk, __entry_task, x20 |
| 225 | msr sp_el0, tsk |
| 226 | |
Will Deacon | 8c3001b | 2020-07-08 22:10:01 +0100 | [diff] [blame] | 227 | /* |
| 228 | * Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions |
| 229 | * when scheduling. |
| 230 | */ |
Mark Rutland | 3e39341 | 2020-01-16 18:35:48 +0000 | [diff] [blame] | 231 | ldr x19, [tsk, #TSK_TI_FLAGS] |
| 232 | disable_step_tsk x19, x20 |
James Morse | 49003a8 | 2015-12-10 10:22:41 +0000 | [diff] [blame] | 233 | |
Vincenzo Frascino | 637ec83 | 2019-09-16 11:51:17 +0100 | [diff] [blame] | 234 | /* Check for asynchronous tag check faults in user space */ |
Peter Collingbourne | 42b6b10 | 2021-07-08 19:35:32 -0700 | [diff] [blame] | 235 | ldr x0, [tsk, THREAD_SCTLR_USER] |
| 236 | check_mte_async_tcf x22, x23, x0 |
Marc Zyngier | 8e29062 | 2018-05-29 13:11:06 +0100 | [diff] [blame] | 237 | |
Peter Collingbourne | 2016986 | 2021-03-18 20:10:53 -0700 | [diff] [blame] | 238 | #ifdef CONFIG_ARM64_PTR_AUTH |
| 239 | alternative_if ARM64_HAS_ADDRESS_AUTH |
| 240 | /* |
| 241 | * Enable IA for in-kernel PAC if the task had it disabled. Although |
| 242 | * this could be implemented with an unconditional MRS which would avoid |
| 243 | * a load, this was measured to be slower on Cortex-A75 and Cortex-A76. |
Peter Collingbourne | b90e483 | 2021-03-18 20:10:54 -0700 | [diff] [blame] | 244 | * |
| 245 | * Install the kernel IA key only if IA was enabled in the task. If IA |
| 246 | * was disabled on kernel exit then we would have left the kernel IA |
| 247 | * installed so there is no need to install it again. |
Peter Collingbourne | 2016986 | 2021-03-18 20:10:53 -0700 | [diff] [blame] | 248 | */ |
Peter Collingbourne | b90e483 | 2021-03-18 20:10:54 -0700 | [diff] [blame] | 249 | tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f |
| 250 | __ptrauth_keys_install_kernel_nosync tsk, x20, x22, x23 |
| 251 | b 2f |
| 252 | 1: |
Peter Collingbourne | 2016986 | 2021-03-18 20:10:53 -0700 | [diff] [blame] | 253 | mrs x0, sctlr_el1 |
| 254 | orr x0, x0, SCTLR_ELx_ENIA |
| 255 | msr sctlr_el1, x0 |
Peter Collingbourne | b90e483 | 2021-03-18 20:10:54 -0700 | [diff] [blame] | 256 | 2: |
Peter Collingbourne | 2016986 | 2021-03-18 20:10:53 -0700 | [diff] [blame] | 257 | alternative_else_nop_endif |
| 258 | #endif |
Sami Tolvanen | 5287569 | 2020-04-27 09:00:16 -0700 | [diff] [blame] | 259 | |
Peter Collingbourne | 42b6b10 | 2021-07-08 19:35:32 -0700 | [diff] [blame] | 260 | apply_ssbd 1, x22, x23 |
| 261 | |
Vincenzo Frascino | bad1e1c | 2020-12-22 12:01:45 -0800 | [diff] [blame] | 262 | mte_set_kernel_gcr x22, x23 |
| 263 | |
Peter Collingbourne | d914b80 | 2021-07-27 13:54:39 -0700 | [diff] [blame] | 264 | /* |
| 265 | * Any non-self-synchronizing system register updates required for |
| 266 | * kernel entry should be placed before this point. |
| 267 | */ |
| 268 | alternative_if ARM64_MTE |
| 269 | isb |
| 270 | b 1f |
| 271 | alternative_else_nop_endif |
| 272 | alternative_if ARM64_HAS_ADDRESS_AUTH |
| 273 | isb |
| 274 | alternative_else_nop_endif |
| 275 | 1: |
| 276 | |
Ard Biesheuvel | 2198d07 | 2023-01-09 18:47:59 +0100 | [diff] [blame] | 277 | scs_load_current |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 278 | .else |
Jianlin Lv | 71e7018 | 2021-01-12 09:58:13 +0800 | [diff] [blame] | 279 | add x21, sp, #PT_REGS_SIZE |
Julien Thierry | 4caf875 | 2019-02-22 09:32:50 +0000 | [diff] [blame] | 280 | get_current_task tsk |
James Morse | e19a6ee | 2016-06-20 18:28:01 +0100 | [diff] [blame] | 281 | .endif /* \el == 0 */ |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 282 | mrs x22, elr_el1 |
| 283 | mrs x23, spsr_el1 |
| 284 | stp lr, x21, [sp, #S_LR] |
Catalin Marinas | 39bc88e | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 285 | |
Ard Biesheuvel | 7326749 | 2017-07-22 18:45:33 +0100 | [diff] [blame] | 286 | /* |
Madhavan T. Venkataraman | 7d7b720 | 2021-05-10 12:00:26 +0100 | [diff] [blame] | 287 | * For exceptions from EL0, create a final frame record. |
Mark Rutland | 6106e11 | 2021-01-13 17:31:55 +0000 | [diff] [blame] | 288 | * For exceptions from EL1, create a synthetic frame record so the |
| 289 | * interrupted code shows up in the backtrace. |
Ard Biesheuvel | 7326749 | 2017-07-22 18:45:33 +0100 | [diff] [blame] | 290 | */ |
| 291 | .if \el == 0 |
Mark Rutland | 8533d5b | 2021-04-29 11:20:04 +0100 | [diff] [blame] | 292 | stp xzr, xzr, [sp, #S_STACKFRAME] |
Ard Biesheuvel | 7326749 | 2017-07-22 18:45:33 +0100 | [diff] [blame] | 293 | .else |
| 294 | stp x29, x22, [sp, #S_STACKFRAME] |
Mark Rutland | 6106e11 | 2021-01-13 17:31:55 +0000 | [diff] [blame] | 295 | .endif |
Mark Rutland | 8533d5b | 2021-04-29 11:20:04 +0100 | [diff] [blame] | 296 | add x29, sp, #S_STACKFRAME |
Ard Biesheuvel | 7326749 | 2017-07-22 18:45:33 +0100 | [diff] [blame] | 297 | |
Catalin Marinas | 39bc88e | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 298 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
Ard Biesheuvel | 0ae3b13 | 2020-07-21 10:33:15 +0200 | [diff] [blame] | 299 | alternative_if_not ARM64_HAS_PAN |
| 300 | bl __swpan_entry_el\el |
Catalin Marinas | 39bc88e | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 301 | alternative_else_nop_endif |
Catalin Marinas | 39bc88e | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 302 | #endif |
| 303 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 304 | stp x22, x23, [sp, #S_PC] |
| 305 | |
Dave Martin | 17c2895 | 2017-08-01 15:35:54 +0100 | [diff] [blame] | 306 | /* Not in a syscall by default (el0_svc overwrites for real syscall) */ |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 307 | .if \el == 0 |
Dave Martin | 17c2895 | 2017-08-01 15:35:54 +0100 | [diff] [blame] | 308 | mov w21, #NO_SYSCALL |
Dave Martin | 35d0e6f | 2017-08-01 15:35:53 +0100 | [diff] [blame] | 309 | str w21, [sp, #S_SYSCALLNO] |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 310 | .endif |
| 311 | |
He Ying | 3352a55 | 2022-01-11 22:24:10 -0500 | [diff] [blame] | 312 | #ifdef CONFIG_ARM64_PSEUDO_NMI |
Mark Rutland | 8bf0a80 | 2023-01-30 14:54:28 +0000 | [diff] [blame] | 313 | alternative_if_not ARM64_HAS_GIC_PRIO_MASKING |
| 314 | b .Lskip_pmr_save\@ |
| 315 | alternative_else_nop_endif |
| 316 | |
Julien Thierry | 133d051 | 2019-01-31 14:58:46 +0000 | [diff] [blame] | 317 | mrs_s x20, SYS_ICC_PMR_EL1 |
| 318 | str x20, [sp, #S_PMR_SAVE] |
Mark Rutland | 4d6a38d | 2021-04-28 12:15:55 +0100 | [diff] [blame] | 319 | mov x20, #GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET |
| 320 | msr_s SYS_ICC_PMR_EL1, x20 |
Mark Rutland | 8bf0a80 | 2023-01-30 14:54:28 +0000 | [diff] [blame] | 321 | |
| 322 | .Lskip_pmr_save\@: |
He Ying | 3352a55 | 2022-01-11 22:24:10 -0500 | [diff] [blame] | 323 | #endif |
Julien Thierry | 133d051 | 2019-01-31 14:58:46 +0000 | [diff] [blame] | 324 | |
Jungseok Lee | 6cdf9c7 | 2015-12-04 11:02:25 +0000 | [diff] [blame] | 325 | /* |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 326 | * Registers that may be useful after this macro is invoked: |
| 327 | * |
Julien Thierry | bd82d4b | 2019-06-11 10:38:10 +0100 | [diff] [blame] | 328 | * x20 - ICC_PMR_EL1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 329 | * x21 - aborted SP |
| 330 | * x22 - aborted PC |
| 331 | * x23 - aborted PSTATE |
| 332 | */ |
| 333 | .endm |
| 334 | |
Will Deacon | 412fcb6 | 2015-08-19 15:57:09 +0100 | [diff] [blame] | 335 | .macro kernel_exit, el |
James Morse | e19a6ee | 2016-06-20 18:28:01 +0100 | [diff] [blame] | 336 | .if \el != 0 |
James Morse | 8d66772 | 2017-11-02 12:12:37 +0000 | [diff] [blame] | 337 | disable_daif |
James Morse | e19a6ee | 2016-06-20 18:28:01 +0100 | [diff] [blame] | 338 | .endif |
| 339 | |
He Ying | 3352a55 | 2022-01-11 22:24:10 -0500 | [diff] [blame] | 340 | #ifdef CONFIG_ARM64_PSEUDO_NMI |
Mark Rutland | 8bf0a80 | 2023-01-30 14:54:28 +0000 | [diff] [blame] | 341 | alternative_if_not ARM64_HAS_GIC_PRIO_MASKING |
| 342 | b .Lskip_pmr_restore\@ |
| 343 | alternative_else_nop_endif |
| 344 | |
Julien Thierry | 133d051 | 2019-01-31 14:58:46 +0000 | [diff] [blame] | 345 | ldr x20, [sp, #S_PMR_SAVE] |
| 346 | msr_s SYS_ICC_PMR_EL1, x20 |
Mark Rutland | 8bf0a80 | 2023-01-30 14:54:28 +0000 | [diff] [blame] | 347 | |
| 348 | /* Ensure priority change is seen by redistributor */ |
| 349 | alternative_if_not ARM64_HAS_GIC_PRIO_RELAXED_SYNC |
| 350 | dsb sy |
Julien Thierry | 133d051 | 2019-01-31 14:58:46 +0000 | [diff] [blame] | 351 | alternative_else_nop_endif |
Mark Rutland | 8bf0a80 | 2023-01-30 14:54:28 +0000 | [diff] [blame] | 352 | |
| 353 | .Lskip_pmr_restore\@: |
He Ying | 3352a55 | 2022-01-11 22:24:10 -0500 | [diff] [blame] | 354 | #endif |
Julien Thierry | 133d051 | 2019-01-31 14:58:46 +0000 | [diff] [blame] | 355 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 356 | ldp x21, x22, [sp, #S_PC] // load ELR, SPSR |
Catalin Marinas | 39bc88e | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 357 | |
| 358 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
Ard Biesheuvel | 0ae3b13 | 2020-07-21 10:33:15 +0200 | [diff] [blame] | 359 | alternative_if_not ARM64_HAS_PAN |
| 360 | bl __swpan_exit_el\el |
Catalin Marinas | 39bc88e | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 361 | alternative_else_nop_endif |
Catalin Marinas | 39bc88e | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 362 | #endif |
| 363 | |
| 364 | .if \el == 0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 365 | ldr x23, [sp, #S_SP] // load return stack pointer |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 366 | msr sp_el0, x23 |
Will Deacon | 4bf3286 | 2017-11-14 14:24:29 +0000 | [diff] [blame] | 367 | tst x22, #PSR_MODE32_BIT // native task? |
| 368 | b.eq 3f |
| 369 | |
Will Deacon | 905e8c5 | 2015-03-23 19:07:02 +0000 | [diff] [blame] | 370 | #ifdef CONFIG_ARM64_ERRATUM_845719 |
Mark Rutland | 6ba3b55 | 2016-09-07 11:07:09 +0100 | [diff] [blame] | 371 | alternative_if ARM64_WORKAROUND_845719 |
Daniel Thompson | e28cabf | 2015-07-22 12:21:03 +0100 | [diff] [blame] | 372 | #ifdef CONFIG_PID_IN_CONTEXTIDR |
| 373 | mrs x29, contextidr_el1 |
| 374 | msr contextidr_el1, x29 |
| 375 | #else |
| 376 | msr contextidr_el1, xzr |
| 377 | #endif |
Mark Rutland | 6ba3b55 | 2016-09-07 11:07:09 +0100 | [diff] [blame] | 378 | alternative_else_nop_endif |
Will Deacon | 905e8c5 | 2015-03-23 19:07:02 +0000 | [diff] [blame] | 379 | #endif |
Will Deacon | 4bf3286 | 2017-11-14 14:24:29 +0000 | [diff] [blame] | 380 | 3: |
Will Deacon | 16c230b | 2021-05-27 11:55:29 +0100 | [diff] [blame] | 381 | scs_save tsk |
Sami Tolvanen | 5287569 | 2020-04-27 09:00:16 -0700 | [diff] [blame] | 382 | |
Peter Collingbourne | 42b6b10 | 2021-07-08 19:35:32 -0700 | [diff] [blame] | 383 | /* Ignore asynchronous tag check faults in the uaccess routines */ |
| 384 | ldr x0, [tsk, THREAD_SCTLR_USER] |
| 385 | clear_mte_async_tcf x0 |
| 386 | |
Peter Collingbourne | 2016986 | 2021-03-18 20:10:53 -0700 | [diff] [blame] | 387 | #ifdef CONFIG_ARM64_PTR_AUTH |
| 388 | alternative_if ARM64_HAS_ADDRESS_AUTH |
| 389 | /* |
Peter Collingbourne | b90e483 | 2021-03-18 20:10:54 -0700 | [diff] [blame] | 390 | * IA was enabled for in-kernel PAC. Disable it now if needed, or |
| 391 | * alternatively install the user's IA. All other per-task keys and |
| 392 | * SCTLR bits were updated on task switch. |
| 393 | * |
| 394 | * No kernel C function calls after this. |
Peter Collingbourne | 2016986 | 2021-03-18 20:10:53 -0700 | [diff] [blame] | 395 | */ |
Peter Collingbourne | b90e483 | 2021-03-18 20:10:54 -0700 | [diff] [blame] | 396 | tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f |
| 397 | __ptrauth_keys_install_user tsk, x0, x1, x2 |
| 398 | b 2f |
| 399 | 1: |
Peter Collingbourne | 2016986 | 2021-03-18 20:10:53 -0700 | [diff] [blame] | 400 | mrs x0, sctlr_el1 |
| 401 | bic x0, x0, SCTLR_ELx_ENIA |
| 402 | msr sctlr_el1, x0 |
Peter Collingbourne | b90e483 | 2021-03-18 20:10:54 -0700 | [diff] [blame] | 403 | 2: |
Peter Collingbourne | 2016986 | 2021-03-18 20:10:53 -0700 | [diff] [blame] | 404 | alternative_else_nop_endif |
| 405 | #endif |
Kristina Martsenko | be12984 | 2020-03-13 14:34:51 +0530 | [diff] [blame] | 406 | |
Vincenzo Frascino | bad1e1c | 2020-12-22 12:01:45 -0800 | [diff] [blame] | 407 | mte_set_user_gcr tsk, x0, x1 |
| 408 | |
Mark Rutland | 99ed3ed | 2018-07-11 14:56:47 +0100 | [diff] [blame] | 409 | apply_ssbd 0, x0, x1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 410 | .endif |
Catalin Marinas | 39bc88e | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 411 | |
Will Deacon | 63648dd | 2014-09-29 12:26:41 +0100 | [diff] [blame] | 412 | msr elr_el1, x21 // set up the return data |
| 413 | msr spsr_el1, x22 |
Will Deacon | 63648dd | 2014-09-29 12:26:41 +0100 | [diff] [blame] | 414 | ldp x0, x1, [sp, #16 * 0] |
Will Deacon | 63648dd | 2014-09-29 12:26:41 +0100 | [diff] [blame] | 415 | ldp x2, x3, [sp, #16 * 1] |
| 416 | ldp x4, x5, [sp, #16 * 2] |
| 417 | ldp x6, x7, [sp, #16 * 3] |
| 418 | ldp x8, x9, [sp, #16 * 4] |
| 419 | ldp x10, x11, [sp, #16 * 5] |
| 420 | ldp x12, x13, [sp, #16 * 6] |
| 421 | ldp x14, x15, [sp, #16 * 7] |
| 422 | ldp x16, x17, [sp, #16 * 8] |
| 423 | ldp x18, x19, [sp, #16 * 9] |
| 424 | ldp x20, x21, [sp, #16 * 10] |
| 425 | ldp x22, x23, [sp, #16 * 11] |
| 426 | ldp x24, x25, [sp, #16 * 12] |
| 427 | ldp x26, x27, [sp, #16 * 13] |
| 428 | ldp x28, x29, [sp, #16 * 14] |
Will Deacon | 4bf3286 | 2017-11-14 14:24:29 +0000 | [diff] [blame] | 429 | |
Will Deacon | 4bf3286 | 2017-11-14 14:24:29 +0000 | [diff] [blame] | 430 | .if \el == 0 |
Will Deacon | ea1e3de | 2017-11-14 14:38:19 +0000 | [diff] [blame] | 431 | #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 |
Mark Rutland | 832dd63 | 2024-01-16 11:02:20 +0000 | [diff] [blame] | 432 | alternative_insn "b .L_skip_tramp_exit_\@", nop, ARM64_UNMAP_KERNEL_AT_EL0 |
| 433 | |
James Morse | 03aff3a | 2021-11-23 18:41:43 +0000 | [diff] [blame] | 434 | msr far_el1, x29 |
Ard Biesheuvel | 211ceca | 2023-04-18 16:36:04 +0200 | [diff] [blame] | 435 | |
| 436 | ldr_this_cpu x30, this_cpu_vector, x29 |
| 437 | tramp_alias x29, tramp_exit |
| 438 | msr vbar_el1, x30 // install vector table |
| 439 | ldr lr, [sp, #S_LR] // restore x30 |
| 440 | add sp, sp, #PT_REGS_SIZE // restore sp |
| 441 | br x29 |
Mark Rutland | 832dd63 | 2024-01-16 11:02:20 +0000 | [diff] [blame] | 442 | |
| 443 | .L_skip_tramp_exit_\@: |
Will Deacon | ea1e3de | 2017-11-14 14:38:19 +0000 | [diff] [blame] | 444 | #endif |
Mark Rutland | da59f1d | 2024-01-16 11:02:21 +0000 | [diff] [blame] | 445 | .endif |
| 446 | |
Mark Rutland | 832dd63 | 2024-01-16 11:02:20 +0000 | [diff] [blame] | 447 | ldr lr, [sp, #S_LR] |
| 448 | add sp, sp, #PT_REGS_SIZE // restore sp |
| 449 | |
Mark Rutland | da59f1d | 2024-01-16 11:02:21 +0000 | [diff] [blame] | 450 | .if \el == 0 |
Mark Rutland | 832dd63 | 2024-01-16 11:02:20 +0000 | [diff] [blame] | 451 | /* This must be after the last explicit memory access */ |
| 452 | alternative_if ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD |
| 453 | tlbi vale1, xzr |
| 454 | dsb nsh |
| 455 | alternative_else_nop_endif |
Will Deacon | 4bf3286 | 2017-11-14 14:24:29 +0000 | [diff] [blame] | 456 | .else |
Rob Herring | 96d389ca | 2020-10-28 13:28:39 -0500 | [diff] [blame] | 457 | /* Ensure any device/NC reads complete */ |
| 458 | alternative_insn nop, "dmb sy", ARM64_WORKAROUND_1508412 |
Mark Rutland | da59f1d | 2024-01-16 11:02:21 +0000 | [diff] [blame] | 459 | .endif |
Rob Herring | 96d389ca | 2020-10-28 13:28:39 -0500 | [diff] [blame] | 460 | |
Will Deacon | 4bf3286 | 2017-11-14 14:24:29 +0000 | [diff] [blame] | 461 | eret |
Will Deacon | 679db70 | 2018-06-14 11:23:38 +0100 | [diff] [blame] | 462 | sb |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 463 | .endm |
| 464 | |
Ard Biesheuvel | 0ae3b13 | 2020-07-21 10:33:15 +0200 | [diff] [blame] | 465 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
| 466 | /* |
| 467 | * Set the TTBR0 PAN bit in SPSR. When the exception is taken from |
| 468 | * EL0, there is no need to check the state of TTBR0_EL1 since |
| 469 | * accesses are always enabled. |
| 470 | * Note that the meaning of this bit differs from the ARMv8.1 PAN |
| 471 | * feature as all TTBR0_EL1 accesses are disabled, not just those to |
| 472 | * user mappings. |
| 473 | */ |
| 474 | SYM_CODE_START_LOCAL(__swpan_entry_el1) |
| 475 | mrs x21, ttbr0_el1 |
| 476 | tst x21, #TTBR_ASID_MASK // Check for the reserved ASID |
| 477 | orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR |
| 478 | b.eq 1f // TTBR0 access already disabled |
| 479 | and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR |
| 480 | SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL) |
| 481 | __uaccess_ttbr0_disable x21 |
| 482 | 1: ret |
| 483 | SYM_CODE_END(__swpan_entry_el1) |
| 484 | |
| 485 | /* |
| 486 | * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR |
| 487 | * PAN bit checking. |
| 488 | */ |
| 489 | SYM_CODE_START_LOCAL(__swpan_exit_el1) |
| 490 | tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set |
| 491 | __uaccess_ttbr0_enable x0, x1 |
| 492 | 1: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit |
| 493 | ret |
| 494 | SYM_CODE_END(__swpan_exit_el1) |
| 495 | |
| 496 | SYM_CODE_START_LOCAL(__swpan_exit_el0) |
| 497 | __uaccess_ttbr0_enable x0, x1 |
| 498 | /* |
| 499 | * Enable errata workarounds only if returning to user. The only |
| 500 | * workaround currently required for TTBR0_EL1 changes are for the |
| 501 | * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache |
| 502 | * corruption). |
| 503 | */ |
| 504 | b post_ttbr_update_workaround |
| 505 | SYM_CODE_END(__swpan_exit_el0) |
| 506 | #endif |
| 507 | |
Mark Rutland | 8c2c596f | 2019-01-03 13:23:10 +0000 | [diff] [blame] | 508 | /* GPRs used by entry code */ |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 509 | tsk .req x28 // current thread_info |
| 510 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 511 | .text |
| 512 | |
| 513 | /* |
| 514 | * Exception vectors. |
| 515 | */ |
Pratyush Anand | 888b3c8 | 2016-07-08 12:35:50 -0400 | [diff] [blame] | 516 | .pushsection ".entry.text", "ax" |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 517 | |
| 518 | .align 11 |
Mark Brown | 0ccbd98 | 2020-02-18 19:58:27 +0000 | [diff] [blame] | 519 | SYM_CODE_START(vectors) |
Mark Rutland | ec841aa | 2021-06-07 10:46:18 +0100 | [diff] [blame] | 520 | kernel_ventry 1, t, 64, sync // Synchronous EL1t |
| 521 | kernel_ventry 1, t, 64, irq // IRQ EL1t |
Kuan-Ying Lee | 729a916 | 2022-07-21 11:05:31 +0800 | [diff] [blame] | 522 | kernel_ventry 1, t, 64, fiq // FIQ EL1t |
Mark Rutland | ec841aa | 2021-06-07 10:46:18 +0100 | [diff] [blame] | 523 | kernel_ventry 1, t, 64, error // Error EL1t |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 524 | |
Mark Rutland | ec841aa | 2021-06-07 10:46:18 +0100 | [diff] [blame] | 525 | kernel_ventry 1, h, 64, sync // Synchronous EL1h |
| 526 | kernel_ventry 1, h, 64, irq // IRQ EL1h |
| 527 | kernel_ventry 1, h, 64, fiq // FIQ EL1h |
| 528 | kernel_ventry 1, h, 64, error // Error EL1h |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 529 | |
Mark Rutland | ec841aa | 2021-06-07 10:46:18 +0100 | [diff] [blame] | 530 | kernel_ventry 0, t, 64, sync // Synchronous 64-bit EL0 |
| 531 | kernel_ventry 0, t, 64, irq // IRQ 64-bit EL0 |
| 532 | kernel_ventry 0, t, 64, fiq // FIQ 64-bit EL0 |
| 533 | kernel_ventry 0, t, 64, error // Error 64-bit EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 534 | |
Mark Rutland | ec841aa | 2021-06-07 10:46:18 +0100 | [diff] [blame] | 535 | kernel_ventry 0, t, 32, sync // Synchronous 32-bit EL0 |
| 536 | kernel_ventry 0, t, 32, irq // IRQ 32-bit EL0 |
| 537 | kernel_ventry 0, t, 32, fiq // FIQ 32-bit EL0 |
| 538 | kernel_ventry 0, t, 32, error // Error 32-bit EL0 |
Mark Brown | 0ccbd98 | 2020-02-18 19:58:27 +0000 | [diff] [blame] | 539 | SYM_CODE_END(vectors) |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 540 | |
Mark Rutland | 872d832 | 2017-07-14 20:30:35 +0100 | [diff] [blame] | 541 | #ifdef CONFIG_VMAP_STACK |
Mark Brown | ede3241 | 2021-08-04 19:17:10 +0100 | [diff] [blame] | 542 | SYM_CODE_START_LOCAL(__bad_stack) |
Mark Rutland | 872d832 | 2017-07-14 20:30:35 +0100 | [diff] [blame] | 543 | /* |
| 544 | * We detected an overflow in kernel_ventry, which switched to the |
| 545 | * overflow stack. Stash the exception regs, and head to our overflow |
| 546 | * handler. |
| 547 | */ |
Mark Brown | ede3241 | 2021-08-04 19:17:10 +0100 | [diff] [blame] | 548 | |
Mark Rutland | 872d832 | 2017-07-14 20:30:35 +0100 | [diff] [blame] | 549 | /* Restore the original x0 value */ |
| 550 | mrs x0, tpidrro_el0 |
| 551 | |
| 552 | /* |
| 553 | * Store the original GPRs to the new stack. The orginal SP (minus |
Jianlin Lv | 71e7018 | 2021-01-12 09:58:13 +0800 | [diff] [blame] | 554 | * PT_REGS_SIZE) was stashed in tpidr_el0 by kernel_ventry. |
Mark Rutland | 872d832 | 2017-07-14 20:30:35 +0100 | [diff] [blame] | 555 | */ |
Jianlin Lv | 71e7018 | 2021-01-12 09:58:13 +0800 | [diff] [blame] | 556 | sub sp, sp, #PT_REGS_SIZE |
Mark Rutland | 872d832 | 2017-07-14 20:30:35 +0100 | [diff] [blame] | 557 | kernel_entry 1 |
| 558 | mrs x0, tpidr_el0 |
Jianlin Lv | 71e7018 | 2021-01-12 09:58:13 +0800 | [diff] [blame] | 559 | add x0, x0, #PT_REGS_SIZE |
Mark Rutland | 872d832 | 2017-07-14 20:30:35 +0100 | [diff] [blame] | 560 | str x0, [sp, #S_SP] |
| 561 | |
| 562 | /* Stash the regs for handle_bad_stack */ |
| 563 | mov x0, sp |
| 564 | |
| 565 | /* Time to die */ |
| 566 | bl handle_bad_stack |
| 567 | ASM_BUG() |
Mark Brown | ede3241 | 2021-08-04 19:17:10 +0100 | [diff] [blame] | 568 | SYM_CODE_END(__bad_stack) |
Mark Rutland | 872d832 | 2017-07-14 20:30:35 +0100 | [diff] [blame] | 569 | #endif /* CONFIG_VMAP_STACK */ |
| 570 | |
Mark Rutland | ec841aa | 2021-06-07 10:46:18 +0100 | [diff] [blame] | 571 | |
| 572 | .macro entry_handler el:req, ht:req, regsize:req, label:req |
| 573 | SYM_CODE_START_LOCAL(el\el\ht\()_\regsize\()_\label) |
Ard Biesheuvel | b660950 | 2016-03-18 10:58:09 +0100 | [diff] [blame] | 574 | kernel_entry \el, \regsize |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 575 | mov x0, sp |
Mark Rutland | ec841aa | 2021-06-07 10:46:18 +0100 | [diff] [blame] | 576 | bl el\el\ht\()_\regsize\()_\label\()_handler |
Mark Rutland | a5b43a8 | 2021-06-07 10:46:17 +0100 | [diff] [blame] | 577 | .if \el == 0 |
| 578 | b ret_to_user |
| 579 | .else |
| 580 | b ret_to_kernel |
| 581 | .endif |
Mark Rutland | ec841aa | 2021-06-07 10:46:18 +0100 | [diff] [blame] | 582 | SYM_CODE_END(el\el\ht\()_\regsize\()_\label) |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 583 | .endm |
| 584 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 585 | /* |
Mark Rutland | a5b43a8 | 2021-06-07 10:46:17 +0100 | [diff] [blame] | 586 | * Early exception handlers |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 587 | */ |
Mark Rutland | ec841aa | 2021-06-07 10:46:18 +0100 | [diff] [blame] | 588 | entry_handler 1, t, 64, sync |
| 589 | entry_handler 1, t, 64, irq |
| 590 | entry_handler 1, t, 64, fiq |
| 591 | entry_handler 1, t, 64, error |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 592 | |
Mark Rutland | ec841aa | 2021-06-07 10:46:18 +0100 | [diff] [blame] | 593 | entry_handler 1, h, 64, sync |
| 594 | entry_handler 1, h, 64, irq |
| 595 | entry_handler 1, h, 64, fiq |
| 596 | entry_handler 1, h, 64, error |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 597 | |
Mark Rutland | ec841aa | 2021-06-07 10:46:18 +0100 | [diff] [blame] | 598 | entry_handler 0, t, 64, sync |
| 599 | entry_handler 0, t, 64, irq |
| 600 | entry_handler 0, t, 64, fiq |
| 601 | entry_handler 0, t, 64, error |
| 602 | |
| 603 | entry_handler 0, t, 32, sync |
| 604 | entry_handler 0, t, 32, irq |
| 605 | entry_handler 0, t, 32, fiq |
| 606 | entry_handler 0, t, 32, error |
Xie XiuQi | a92d4d1 | 2017-11-02 12:12:42 +0000 | [diff] [blame] | 607 | |
Mark Rutland | af541cb | 2021-06-07 10:46:14 +0100 | [diff] [blame] | 608 | SYM_CODE_START_LOCAL(ret_to_kernel) |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 609 | kernel_exit 1 |
Mark Rutland | af541cb | 2021-06-07 10:46:14 +0100 | [diff] [blame] | 610 | SYM_CODE_END(ret_to_kernel) |
Xie XiuQi | a92d4d1 | 2017-11-02 12:12:42 +0000 | [diff] [blame] | 611 | |
Mark Brown | 06607c7 | 2020-05-01 12:54:28 +0100 | [diff] [blame] | 612 | SYM_CODE_START_LOCAL(ret_to_user) |
Mark Rutland | 4d1c2ee | 2021-08-02 15:07:32 +0100 | [diff] [blame] | 613 | ldr x19, [tsk, #TSK_TI_FLAGS] // re-check for single-step |
Mark Rutland | 3cb5ed4 | 2020-11-30 11:59:44 +0000 | [diff] [blame] | 614 | enable_step_tsk x19, x2 |
Laura Abbott | 0b3e336 | 2018-07-20 14:41:54 -0700 | [diff] [blame] | 615 | #ifdef CONFIG_GCC_PLUGIN_STACKLEAK |
Mark Rutland | 88959a3 | 2022-04-27 18:31:28 +0100 | [diff] [blame] | 616 | bl stackleak_erase_on_task_stack |
Laura Abbott | 0b3e336 | 2018-07-20 14:41:54 -0700 | [diff] [blame] | 617 | #endif |
Will Deacon | 412fcb6 | 2015-08-19 15:57:09 +0100 | [diff] [blame] | 618 | kernel_exit 0 |
Mark Brown | 06607c7 | 2020-05-01 12:54:28 +0100 | [diff] [blame] | 619 | SYM_CODE_END(ret_to_user) |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 620 | |
Pratyush Anand | 888b3c8 | 2016-07-08 12:35:50 -0400 | [diff] [blame] | 621 | .popsection // .entry.text |
| 622 | |
Mark Rutland | 833be85 | 2020-11-03 10:22:29 +0000 | [diff] [blame] | 623 | // Move from tramp_pg_dir to swapper_pg_dir |
Will Deacon | c7b9ada | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 624 | .macro tramp_map_kernel, tmp |
| 625 | mrs \tmp, ttbr1_el1 |
Joey Gouly | 0188a89 | 2021-02-02 12:36:58 +0000 | [diff] [blame] | 626 | add \tmp, \tmp, #TRAMP_SWAPPER_OFFSET |
Will Deacon | c7b9ada | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 627 | bic \tmp, \tmp, #USER_ASID_FLAG |
| 628 | msr ttbr1_el1, \tmp |
Will Deacon | d1777e6 | 2017-11-14 14:29:19 +0000 | [diff] [blame] | 629 | #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 |
| 630 | alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003 |
| 631 | /* ASID already in \tmp[63:48] */ |
| 632 | movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12) |
| 633 | movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12) |
| 634 | /* 2MB boundary containing the vectors, so we nobble the walk cache */ |
| 635 | movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12) |
| 636 | isb |
| 637 | tlbi vae1, \tmp |
| 638 | dsb nsh |
| 639 | alternative_else_nop_endif |
| 640 | #endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */ |
Will Deacon | c7b9ada | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 641 | .endm |
| 642 | |
Mark Rutland | 833be85 | 2020-11-03 10:22:29 +0000 | [diff] [blame] | 643 | // Move from swapper_pg_dir to tramp_pg_dir |
Will Deacon | c7b9ada | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 644 | .macro tramp_unmap_kernel, tmp |
| 645 | mrs \tmp, ttbr1_el1 |
Joey Gouly | 0188a89 | 2021-02-02 12:36:58 +0000 | [diff] [blame] | 646 | sub \tmp, \tmp, #TRAMP_SWAPPER_OFFSET |
Will Deacon | c7b9ada | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 647 | orr \tmp, \tmp, #USER_ASID_FLAG |
| 648 | msr ttbr1_el1, \tmp |
| 649 | /* |
Will Deacon | f167211 | 2018-01-29 11:59:58 +0000 | [diff] [blame] | 650 | * We avoid running the post_ttbr_update_workaround here because |
| 651 | * it's only needed by Cavium ThunderX, which requires KPTI to be |
| 652 | * disabled. |
Will Deacon | c7b9ada | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 653 | */ |
| 654 | .endm |
| 655 | |
Ard Biesheuvel | 1c9a8e87 | 2022-06-22 18:10:10 +0200 | [diff] [blame] | 656 | .macro tramp_data_read_var dst, var |
| 657 | #ifdef CONFIG_RELOCATABLE |
| 658 | ldr \dst, .L__tramp_data_\var |
| 659 | .ifndef .L__tramp_data_\var |
| 660 | .pushsection ".entry.tramp.rodata", "a", %progbits |
| 661 | .align 3 |
| 662 | .L__tramp_data_\var: |
| 663 | .quad \var |
| 664 | .popsection |
| 665 | .endif |
James Morse | b28a8ee | 2021-11-25 14:25:34 +0000 | [diff] [blame] | 666 | #else |
Ard Biesheuvel | 1c9a8e87 | 2022-06-22 18:10:10 +0200 | [diff] [blame] | 667 | /* |
| 668 | * As !RELOCATABLE implies !RANDOMIZE_BASE the address is always a |
| 669 | * compile time constant (and hence not secret and not worth hiding). |
| 670 | * |
| 671 | * As statically allocated kernel code and data always live in the top |
| 672 | * 47 bits of the address space we can sign-extend bit 47 and avoid an |
| 673 | * instruction to load the upper 16 bits (which must be 0xFFFF). |
| 674 | */ |
| 675 | movz \dst, :abs_g2_s:\var |
| 676 | movk \dst, :abs_g1_nc:\var |
| 677 | movk \dst, :abs_g0_nc:\var |
James Morse | b28a8ee | 2021-11-25 14:25:34 +0000 | [diff] [blame] | 678 | #endif |
| 679 | .endm |
James Morse | ba26892 | 2021-11-18 13:59:46 +0000 | [diff] [blame] | 680 | |
| 681 | #define BHB_MITIGATION_NONE 0 |
| 682 | #define BHB_MITIGATION_LOOP 1 |
| 683 | #define BHB_MITIGATION_FW 2 |
James Morse | 228a26b | 2021-12-10 14:32:56 +0000 | [diff] [blame] | 684 | #define BHB_MITIGATION_INSN 3 |
James Morse | ba26892 | 2021-11-18 13:59:46 +0000 | [diff] [blame] | 685 | |
| 686 | .macro tramp_ventry, vector_start, regsize, kpti, bhb |
Will Deacon | c7b9ada | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 687 | .align 7 |
| 688 | 1: |
| 689 | .if \regsize == 64 |
| 690 | msr tpidrro_el0, x30 // Restored in kernel_ventry |
| 691 | .endif |
James Morse | aff6539 | 2021-11-24 15:03:15 +0000 | [diff] [blame] | 692 | |
James Morse | ba26892 | 2021-11-18 13:59:46 +0000 | [diff] [blame] | 693 | .if \bhb == BHB_MITIGATION_LOOP |
| 694 | /* |
| 695 | * This sequence must appear before the first indirect branch. i.e. the |
| 696 | * ret out of tramp_ventry. It appears here because x30 is free. |
| 697 | */ |
| 698 | __mitigate_spectre_bhb_loop x30 |
| 699 | .endif // \bhb == BHB_MITIGATION_LOOP |
| 700 | |
James Morse | 228a26b | 2021-12-10 14:32:56 +0000 | [diff] [blame] | 701 | .if \bhb == BHB_MITIGATION_INSN |
| 702 | clearbhb |
| 703 | isb |
| 704 | .endif // \bhb == BHB_MITIGATION_INSN |
| 705 | |
James Morse | aff6539 | 2021-11-24 15:03:15 +0000 | [diff] [blame] | 706 | .if \kpti == 1 |
Will Deacon | be04a6d | 2017-11-14 16:15:59 +0000 | [diff] [blame] | 707 | /* |
| 708 | * Defend against branch aliasing attacks by pushing a dummy |
| 709 | * entry onto the return stack and using a RET instruction to |
| 710 | * enter the full-fat kernel vectors. |
| 711 | */ |
| 712 | bl 2f |
| 713 | b . |
| 714 | 2: |
Will Deacon | c7b9ada | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 715 | tramp_map_kernel x30 |
Will Deacon | 6c27c40 | 2017-12-06 11:24:02 +0000 | [diff] [blame] | 716 | alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003 |
James Morse | b28a8ee | 2021-11-25 14:25:34 +0000 | [diff] [blame] | 717 | tramp_data_read_var x30, vectors |
Marc Zyngier | 9405447 | 2019-04-09 16:22:24 +0100 | [diff] [blame] | 718 | alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM |
James Morse | ed50da7 | 2021-11-24 13:40:09 +0000 | [diff] [blame] | 719 | prfm plil1strm, [x30, #(1b - \vector_start)] |
Marc Zyngier | 9405447 | 2019-04-09 16:22:24 +0100 | [diff] [blame] | 720 | alternative_else_nop_endif |
James Morse | c47e4d0 | 2021-11-18 13:16:23 +0000 | [diff] [blame] | 721 | |
Will Deacon | c7b9ada | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 722 | msr vbar_el1, x30 |
Will Deacon | c7b9ada | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 723 | isb |
James Morse | c47e4d0 | 2021-11-18 13:16:23 +0000 | [diff] [blame] | 724 | .else |
Ard Biesheuvel | 1c9a8e87 | 2022-06-22 18:10:10 +0200 | [diff] [blame] | 725 | adr_l x30, vectors |
James Morse | c47e4d0 | 2021-11-18 13:16:23 +0000 | [diff] [blame] | 726 | .endif // \kpti == 1 |
| 727 | |
James Morse | ba26892 | 2021-11-18 13:59:46 +0000 | [diff] [blame] | 728 | .if \bhb == BHB_MITIGATION_FW |
| 729 | /* |
| 730 | * The firmware sequence must appear before the first indirect branch. |
| 731 | * i.e. the ret out of tramp_ventry. But it also needs the stack to be |
| 732 | * mapped to save/restore the registers the SMC clobbers. |
| 733 | */ |
| 734 | __mitigate_spectre_bhb_fw |
| 735 | .endif // \bhb == BHB_MITIGATION_FW |
| 736 | |
James Morse | c47e4d0 | 2021-11-18 13:16:23 +0000 | [diff] [blame] | 737 | add x30, x30, #(1b - \vector_start + 4) |
Will Deacon | be04a6d | 2017-11-14 16:15:59 +0000 | [diff] [blame] | 738 | ret |
James Morse | 4330e2c | 2021-11-17 15:15:26 +0000 | [diff] [blame] | 739 | .org 1b + 128 // Did we overflow the ventry slot? |
Will Deacon | c7b9ada | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 740 | .endm |
| 741 | |
James Morse | ba26892 | 2021-11-18 13:59:46 +0000 | [diff] [blame] | 742 | .macro generate_tramp_vector, kpti, bhb |
James Morse | ed50da7 | 2021-11-24 13:40:09 +0000 | [diff] [blame] | 743 | .Lvector_start\@: |
Will Deacon | c7b9ada | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 744 | .space 0x400 |
| 745 | |
James Morse | ed50da7 | 2021-11-24 13:40:09 +0000 | [diff] [blame] | 746 | .rept 4 |
James Morse | ba26892 | 2021-11-18 13:59:46 +0000 | [diff] [blame] | 747 | tramp_ventry .Lvector_start\@, 64, \kpti, \bhb |
James Morse | ed50da7 | 2021-11-24 13:40:09 +0000 | [diff] [blame] | 748 | .endr |
| 749 | .rept 4 |
James Morse | ba26892 | 2021-11-18 13:59:46 +0000 | [diff] [blame] | 750 | tramp_ventry .Lvector_start\@, 32, \kpti, \bhb |
James Morse | ed50da7 | 2021-11-24 13:40:09 +0000 | [diff] [blame] | 751 | .endr |
| 752 | .endm |
Will Deacon | c7b9ada | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 753 | |
James Morse | 13d7a08 | 2021-11-18 14:02:30 +0000 | [diff] [blame] | 754 | #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 |
| 755 | /* |
| 756 | * Exception vectors trampoline. |
James Morse | ba26892 | 2021-11-18 13:59:46 +0000 | [diff] [blame] | 757 | * The order must match __bp_harden_el1_vectors and the |
| 758 | * arm64_bp_harden_el1_vectors enum. |
James Morse | 13d7a08 | 2021-11-18 14:02:30 +0000 | [diff] [blame] | 759 | */ |
| 760 | .pushsection ".entry.tramp.text", "ax" |
James Morse | ed50da7 | 2021-11-24 13:40:09 +0000 | [diff] [blame] | 761 | .align 11 |
Ard Biesheuvel | 211ceca | 2023-04-18 16:36:04 +0200 | [diff] [blame] | 762 | SYM_CODE_START_LOCAL_NOALIGN(tramp_vectors) |
James Morse | ba26892 | 2021-11-18 13:59:46 +0000 | [diff] [blame] | 763 | #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY |
| 764 | generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_LOOP |
| 765 | generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_FW |
James Morse | 228a26b | 2021-12-10 14:32:56 +0000 | [diff] [blame] | 766 | generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_INSN |
James Morse | ba26892 | 2021-11-18 13:59:46 +0000 | [diff] [blame] | 767 | #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ |
| 768 | generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_NONE |
Mark Brown | e7bf697 | 2020-02-18 19:58:29 +0000 | [diff] [blame] | 769 | SYM_CODE_END(tramp_vectors) |
Will Deacon | c7b9ada | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 770 | |
Ard Biesheuvel | 211ceca | 2023-04-18 16:36:04 +0200 | [diff] [blame] | 771 | SYM_CODE_START_LOCAL(tramp_exit) |
| 772 | tramp_unmap_kernel x29 |
| 773 | mrs x29, far_el1 // restore x29 |
| 774 | eret |
| 775 | sb |
| 776 | SYM_CODE_END(tramp_exit) |
Will Deacon | c7b9ada | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 777 | .popsection // .entry.tramp.text |
| 778 | #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ |
| 779 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 780 | /* |
James Morse | aff6539 | 2021-11-24 15:03:15 +0000 | [diff] [blame] | 781 | * Exception vectors for spectre mitigations on entry from EL1 when |
| 782 | * kpti is not in use. |
| 783 | */ |
James Morse | ba26892 | 2021-11-18 13:59:46 +0000 | [diff] [blame] | 784 | .macro generate_el1_vector, bhb |
James Morse | aff6539 | 2021-11-24 15:03:15 +0000 | [diff] [blame] | 785 | .Lvector_start\@: |
| 786 | kernel_ventry 1, t, 64, sync // Synchronous EL1t |
| 787 | kernel_ventry 1, t, 64, irq // IRQ EL1t |
| 788 | kernel_ventry 1, t, 64, fiq // FIQ EL1h |
| 789 | kernel_ventry 1, t, 64, error // Error EL1t |
| 790 | |
| 791 | kernel_ventry 1, h, 64, sync // Synchronous EL1h |
| 792 | kernel_ventry 1, h, 64, irq // IRQ EL1h |
| 793 | kernel_ventry 1, h, 64, fiq // FIQ EL1h |
| 794 | kernel_ventry 1, h, 64, error // Error EL1h |
| 795 | |
| 796 | .rept 4 |
James Morse | ba26892 | 2021-11-18 13:59:46 +0000 | [diff] [blame] | 797 | tramp_ventry .Lvector_start\@, 64, 0, \bhb |
James Morse | aff6539 | 2021-11-24 15:03:15 +0000 | [diff] [blame] | 798 | .endr |
| 799 | .rept 4 |
James Morse | ba26892 | 2021-11-18 13:59:46 +0000 | [diff] [blame] | 800 | tramp_ventry .Lvector_start\@, 32, 0, \bhb |
James Morse | aff6539 | 2021-11-24 15:03:15 +0000 | [diff] [blame] | 801 | .endr |
| 802 | .endm |
| 803 | |
James Morse | ba26892 | 2021-11-18 13:59:46 +0000 | [diff] [blame] | 804 | /* The order must match tramp_vecs and the arm64_bp_harden_el1_vectors enum. */ |
James Morse | aff6539 | 2021-11-24 15:03:15 +0000 | [diff] [blame] | 805 | .pushsection ".entry.text", "ax" |
| 806 | .align 11 |
| 807 | SYM_CODE_START(__bp_harden_el1_vectors) |
James Morse | ba26892 | 2021-11-18 13:59:46 +0000 | [diff] [blame] | 808 | #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY |
| 809 | generate_el1_vector bhb=BHB_MITIGATION_LOOP |
| 810 | generate_el1_vector bhb=BHB_MITIGATION_FW |
James Morse | 228a26b | 2021-12-10 14:32:56 +0000 | [diff] [blame] | 811 | generate_el1_vector bhb=BHB_MITIGATION_INSN |
James Morse | ba26892 | 2021-11-18 13:59:46 +0000 | [diff] [blame] | 812 | #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ |
James Morse | aff6539 | 2021-11-24 15:03:15 +0000 | [diff] [blame] | 813 | SYM_CODE_END(__bp_harden_el1_vectors) |
| 814 | .popsection |
| 815 | |
| 816 | |
| 817 | /* |
Mark Rutland | ed84b4e | 2017-07-26 16:05:20 +0100 | [diff] [blame] | 818 | * Register switch for AArch64. The callee-saved registers need to be saved |
| 819 | * and restored. On entry: |
| 820 | * x0 = previous task_struct (must be preserved across the switch) |
| 821 | * x1 = next task_struct |
| 822 | * Previous and next are guaranteed not to be the same. |
| 823 | * |
| 824 | */ |
Mark Brown | e7bf697 | 2020-02-18 19:58:29 +0000 | [diff] [blame] | 825 | SYM_FUNC_START(cpu_switch_to) |
Mark Rutland | ed84b4e | 2017-07-26 16:05:20 +0100 | [diff] [blame] | 826 | mov x10, #THREAD_CPU_CONTEXT |
| 827 | add x8, x0, x10 |
| 828 | mov x9, sp |
| 829 | stp x19, x20, [x8], #16 // store callee-saved registers |
| 830 | stp x21, x22, [x8], #16 |
| 831 | stp x23, x24, [x8], #16 |
| 832 | stp x25, x26, [x8], #16 |
| 833 | stp x27, x28, [x8], #16 |
| 834 | stp x29, x9, [x8], #16 |
| 835 | str lr, [x8] |
| 836 | add x8, x1, x10 |
| 837 | ldp x19, x20, [x8], #16 // restore callee-saved registers |
| 838 | ldp x21, x22, [x8], #16 |
| 839 | ldp x23, x24, [x8], #16 |
| 840 | ldp x25, x26, [x8], #16 |
| 841 | ldp x27, x28, [x8], #16 |
| 842 | ldp x29, x9, [x8], #16 |
| 843 | ldr lr, [x8] |
| 844 | mov sp, x9 |
| 845 | msr sp_el0, x1 |
Mark Rutland | d0055da5 | 2020-04-23 11:16:05 +0100 | [diff] [blame] | 846 | ptrauth_keys_install_kernel x1, x8, x9, x10 |
Will Deacon | 16c230b | 2021-05-27 11:55:29 +0100 | [diff] [blame] | 847 | scs_save x0 |
Ard Biesheuvel | 2198d07 | 2023-01-09 18:47:59 +0100 | [diff] [blame] | 848 | scs_load_current |
Mark Rutland | ed84b4e | 2017-07-26 16:05:20 +0100 | [diff] [blame] | 849 | ret |
Mark Brown | e7bf697 | 2020-02-18 19:58:29 +0000 | [diff] [blame] | 850 | SYM_FUNC_END(cpu_switch_to) |
Mark Rutland | ed84b4e | 2017-07-26 16:05:20 +0100 | [diff] [blame] | 851 | NOKPROBE(cpu_switch_to) |
| 852 | |
| 853 | /* |
| 854 | * This is how we return from a fork. |
| 855 | */ |
Mark Brown | c3357fc | 2020-02-18 19:58:28 +0000 | [diff] [blame] | 856 | SYM_CODE_START(ret_from_fork) |
Mark Rutland | ed84b4e | 2017-07-26 16:05:20 +0100 | [diff] [blame] | 857 | bl schedule_tail |
| 858 | cbz x19, 1f // not a kernel thread |
| 859 | mov x0, x20 |
| 860 | blr x19 |
Julien Thierry | 4caf875 | 2019-02-22 09:32:50 +0000 | [diff] [blame] | 861 | 1: get_current_task tsk |
Mark Rutland | e130338 | 2021-08-02 15:07:33 +0100 | [diff] [blame] | 862 | mov x0, sp |
| 863 | bl asm_exit_to_user_mode |
Mark Rutland | ed84b4e | 2017-07-26 16:05:20 +0100 | [diff] [blame] | 864 | b ret_to_user |
Mark Brown | c3357fc | 2020-02-18 19:58:28 +0000 | [diff] [blame] | 865 | SYM_CODE_END(ret_from_fork) |
Mark Rutland | ed84b4e | 2017-07-26 16:05:20 +0100 | [diff] [blame] | 866 | NOKPROBE(ret_from_fork) |
James Morse | f5df269 | 2018-01-08 15:38:12 +0000 | [diff] [blame] | 867 | |
Mark Rutland | f804948 | 2021-06-07 10:46:10 +0100 | [diff] [blame] | 868 | /* |
| 869 | * void call_on_irq_stack(struct pt_regs *regs, |
| 870 | * void (*func)(struct pt_regs *)); |
| 871 | * |
| 872 | * Calls func(regs) using this CPU's irq stack and shadow irq stack. |
| 873 | */ |
| 874 | SYM_FUNC_START(call_on_irq_stack) |
| 875 | #ifdef CONFIG_SHADOW_CALL_STACK |
Ard Biesheuvel | 59b37fe | 2023-01-09 18:48:00 +0100 | [diff] [blame] | 876 | get_current_task x16 |
| 877 | scs_save x16 |
Mark Rutland | f804948 | 2021-06-07 10:46:10 +0100 | [diff] [blame] | 878 | ldr_this_cpu scs_sp, irq_shadow_call_stack_ptr, x17 |
| 879 | #endif |
Ard Biesheuvel | 59b37fe | 2023-01-09 18:48:00 +0100 | [diff] [blame] | 880 | |
Mark Rutland | f804948 | 2021-06-07 10:46:10 +0100 | [diff] [blame] | 881 | /* Create a frame record to save our LR and SP (implicit in FP) */ |
| 882 | stp x29, x30, [sp, #-16]! |
| 883 | mov x29, sp |
| 884 | |
| 885 | ldr_this_cpu x16, irq_stack_ptr, x17 |
Mark Rutland | f804948 | 2021-06-07 10:46:10 +0100 | [diff] [blame] | 886 | |
| 887 | /* Move to the new stack and call the function there */ |
Ard Biesheuvel | 59b37fe | 2023-01-09 18:48:00 +0100 | [diff] [blame] | 888 | add sp, x16, #IRQ_STACK_SIZE |
Mark Rutland | f804948 | 2021-06-07 10:46:10 +0100 | [diff] [blame] | 889 | blr x1 |
| 890 | |
| 891 | /* |
| 892 | * Restore the SP from the FP, and restore the FP and LR from the frame |
| 893 | * record. |
| 894 | */ |
| 895 | mov sp, x29 |
| 896 | ldp x29, x30, [sp], #16 |
Ard Biesheuvel | 59b37fe | 2023-01-09 18:48:00 +0100 | [diff] [blame] | 897 | scs_load_current |
Mark Rutland | f804948 | 2021-06-07 10:46:10 +0100 | [diff] [blame] | 898 | ret |
| 899 | SYM_FUNC_END(call_on_irq_stack) |
| 900 | NOKPROBE(call_on_irq_stack) |
| 901 | |
James Morse | f5df269 | 2018-01-08 15:38:12 +0000 | [diff] [blame] | 902 | #ifdef CONFIG_ARM_SDE_INTERFACE |
| 903 | |
| 904 | #include <asm/sdei.h> |
| 905 | #include <uapi/linux/arm_sdei.h> |
| 906 | |
James Morse | 79e9aa5 | 2018-01-08 15:38:18 +0000 | [diff] [blame] | 907 | .macro sdei_handler_exit exit_mode |
| 908 | /* On success, this call never returns... */ |
| 909 | cmp \exit_mode, #SDEI_EXIT_SMC |
| 910 | b.ne 99f |
| 911 | smc #0 |
| 912 | b . |
| 913 | 99: hvc #0 |
| 914 | b . |
| 915 | .endm |
| 916 | |
| 917 | #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 |
| 918 | /* |
| 919 | * The regular SDEI entry point may have been unmapped along with the rest of |
| 920 | * the kernel. This trampoline restores the kernel mapping to make the x1 memory |
| 921 | * argument accessible. |
| 922 | * |
| 923 | * This clobbers x4, __sdei_handler() will restore this from firmware's |
| 924 | * copy. |
| 925 | */ |
James Morse | 79e9aa5 | 2018-01-08 15:38:18 +0000 | [diff] [blame] | 926 | .pushsection ".entry.tramp.text", "ax" |
Mark Brown | 1242b9b | 2020-02-18 19:58:40 +0000 | [diff] [blame] | 927 | SYM_CODE_START(__sdei_asm_entry_trampoline) |
James Morse | 79e9aa5 | 2018-01-08 15:38:18 +0000 | [diff] [blame] | 928 | mrs x4, ttbr1_el1 |
| 929 | tbz x4, #USER_ASID_BIT, 1f |
| 930 | |
| 931 | tramp_map_kernel tmp=x4 |
| 932 | isb |
| 933 | mov x4, xzr |
| 934 | |
| 935 | /* |
Mark Rutland | 3d2403f | 2020-12-02 13:15:55 +0000 | [diff] [blame] | 936 | * Remember whether to unmap the kernel on exit. |
James Morse | 79e9aa5 | 2018-01-08 15:38:18 +0000 | [diff] [blame] | 937 | */ |
Mark Rutland | 3d2403f | 2020-12-02 13:15:55 +0000 | [diff] [blame] | 938 | 1: str x4, [x1, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)] |
James Morse | b28a8ee | 2021-11-25 14:25:34 +0000 | [diff] [blame] | 939 | tramp_data_read_var x4, __sdei_asm_handler |
James Morse | 79e9aa5 | 2018-01-08 15:38:18 +0000 | [diff] [blame] | 940 | br x4 |
Mark Brown | 1242b9b | 2020-02-18 19:58:40 +0000 | [diff] [blame] | 941 | SYM_CODE_END(__sdei_asm_entry_trampoline) |
James Morse | 79e9aa5 | 2018-01-08 15:38:18 +0000 | [diff] [blame] | 942 | NOKPROBE(__sdei_asm_entry_trampoline) |
| 943 | |
| 944 | /* |
| 945 | * Make the exit call and restore the original ttbr1_el1 |
| 946 | * |
| 947 | * x0 & x1: setup for the exit API call |
| 948 | * x2: exit_mode |
| 949 | * x4: struct sdei_registered_event argument from registration time. |
| 950 | */ |
Mark Brown | 1242b9b | 2020-02-18 19:58:40 +0000 | [diff] [blame] | 951 | SYM_CODE_START(__sdei_asm_exit_trampoline) |
Mark Rutland | 3d2403f | 2020-12-02 13:15:55 +0000 | [diff] [blame] | 952 | ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)] |
James Morse | 79e9aa5 | 2018-01-08 15:38:18 +0000 | [diff] [blame] | 953 | cbnz x4, 1f |
| 954 | |
| 955 | tramp_unmap_kernel tmp=x4 |
| 956 | |
| 957 | 1: sdei_handler_exit exit_mode=x2 |
Mark Brown | 1242b9b | 2020-02-18 19:58:40 +0000 | [diff] [blame] | 958 | SYM_CODE_END(__sdei_asm_exit_trampoline) |
James Morse | 79e9aa5 | 2018-01-08 15:38:18 +0000 | [diff] [blame] | 959 | NOKPROBE(__sdei_asm_exit_trampoline) |
James Morse | 79e9aa5 | 2018-01-08 15:38:18 +0000 | [diff] [blame] | 960 | .popsection // .entry.tramp.text |
James Morse | 79e9aa5 | 2018-01-08 15:38:18 +0000 | [diff] [blame] | 961 | #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ |
| 962 | |
James Morse | f5df269 | 2018-01-08 15:38:12 +0000 | [diff] [blame] | 963 | /* |
| 964 | * Software Delegated Exception entry point. |
| 965 | * |
| 966 | * x0: Event number |
| 967 | * x1: struct sdei_registered_event argument from registration time. |
| 968 | * x2: interrupted PC |
| 969 | * x3: interrupted PSTATE |
James Morse | 79e9aa5 | 2018-01-08 15:38:18 +0000 | [diff] [blame] | 970 | * x4: maybe clobbered by the trampoline |
James Morse | f5df269 | 2018-01-08 15:38:12 +0000 | [diff] [blame] | 971 | * |
| 972 | * Firmware has preserved x0->x17 for us, we must save/restore the rest to |
| 973 | * follow SMC-CC. We save (or retrieve) all the registers as the handler may |
| 974 | * want them. |
| 975 | */ |
Mark Brown | 1242b9b | 2020-02-18 19:58:40 +0000 | [diff] [blame] | 976 | SYM_CODE_START(__sdei_asm_handler) |
James Morse | f5df269 | 2018-01-08 15:38:12 +0000 | [diff] [blame] | 977 | stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC] |
| 978 | stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2] |
| 979 | stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3] |
| 980 | stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4] |
| 981 | stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5] |
| 982 | stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6] |
| 983 | stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7] |
| 984 | stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8] |
| 985 | stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9] |
| 986 | stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10] |
| 987 | stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11] |
| 988 | stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12] |
| 989 | stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13] |
| 990 | stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14] |
| 991 | mov x4, sp |
| 992 | stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR] |
| 993 | |
| 994 | mov x19, x1 |
| 995 | |
D Scott Phillips | 5cd474e | 2023-06-26 17:29:39 -0700 | [diff] [blame] | 996 | /* Store the registered-event for crash_smp_send_stop() */ |
Sami Tolvanen | 439dc2a | 2020-04-27 09:00:17 -0700 | [diff] [blame] | 997 | ldrb w4, [x19, #SDEI_EVENT_PRIORITY] |
D Scott Phillips | 5cd474e | 2023-06-26 17:29:39 -0700 | [diff] [blame] | 998 | cbnz w4, 1f |
| 999 | adr_this_cpu dst=x5, sym=sdei_active_normal_event, tmp=x6 |
| 1000 | b 2f |
| 1001 | 1: adr_this_cpu dst=x5, sym=sdei_active_critical_event, tmp=x6 |
| 1002 | 2: str x19, [x5] |
Sami Tolvanen | 439dc2a | 2020-04-27 09:00:17 -0700 | [diff] [blame] | 1003 | |
James Morse | f5df269 | 2018-01-08 15:38:12 +0000 | [diff] [blame] | 1004 | #ifdef CONFIG_VMAP_STACK |
| 1005 | /* |
| 1006 | * entry.S may have been using sp as a scratch register, find whether |
| 1007 | * this is a normal or critical event and switch to the appropriate |
| 1008 | * stack for this CPU. |
| 1009 | */ |
James Morse | f5df269 | 2018-01-08 15:38:12 +0000 | [diff] [blame] | 1010 | cbnz w4, 1f |
| 1011 | ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6 |
| 1012 | b 2f |
| 1013 | 1: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6 |
| 1014 | 2: mov x6, #SDEI_STACK_SIZE |
| 1015 | add x5, x5, x6 |
| 1016 | mov sp, x5 |
| 1017 | #endif |
| 1018 | |
Sami Tolvanen | 439dc2a | 2020-04-27 09:00:17 -0700 | [diff] [blame] | 1019 | #ifdef CONFIG_SHADOW_CALL_STACK |
| 1020 | /* Use a separate shadow call stack for normal and critical events */ |
| 1021 | cbnz w4, 3f |
Sami Tolvanen | ac20ffb | 2020-11-30 15:34:42 -0800 | [diff] [blame] | 1022 | ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_normal_ptr, tmp=x6 |
Sami Tolvanen | 439dc2a | 2020-04-27 09:00:17 -0700 | [diff] [blame] | 1023 | b 4f |
Sami Tolvanen | ac20ffb | 2020-11-30 15:34:42 -0800 | [diff] [blame] | 1024 | 3: ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_critical_ptr, tmp=x6 |
Sami Tolvanen | 439dc2a | 2020-04-27 09:00:17 -0700 | [diff] [blame] | 1025 | 4: |
| 1026 | #endif |
| 1027 | |
James Morse | f5df269 | 2018-01-08 15:38:12 +0000 | [diff] [blame] | 1028 | /* |
| 1029 | * We may have interrupted userspace, or a guest, or exit-from or |
| 1030 | * return-to either of these. We can't trust sp_el0, restore it. |
| 1031 | */ |
| 1032 | mrs x28, sp_el0 |
| 1033 | ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1 |
| 1034 | msr sp_el0, x0 |
| 1035 | |
| 1036 | /* If we interrupted the kernel point to the previous stack/frame. */ |
| 1037 | and x0, x3, #0xc |
| 1038 | mrs x1, CurrentEL |
| 1039 | cmp x0, x1 |
| 1040 | csel x29, x29, xzr, eq // fp, or zero |
| 1041 | csel x4, x2, xzr, eq // elr, or zero |
| 1042 | |
| 1043 | stp x29, x4, [sp, #-16]! |
| 1044 | mov x29, sp |
| 1045 | |
| 1046 | add x0, x19, #SDEI_EVENT_INTREGS |
| 1047 | mov x1, x19 |
| 1048 | bl __sdei_handler |
| 1049 | |
| 1050 | msr sp_el0, x28 |
| 1051 | /* restore regs >x17 that we clobbered */ |
James Morse | 79e9aa5 | 2018-01-08 15:38:18 +0000 | [diff] [blame] | 1052 | mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline |
| 1053 | ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14] |
| 1054 | ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9] |
| 1055 | ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR] |
| 1056 | mov sp, x1 |
James Morse | f5df269 | 2018-01-08 15:38:12 +0000 | [diff] [blame] | 1057 | |
| 1058 | mov x1, x0 // address to complete_and_resume |
Florian Fainelli | c9f5ea0 | 2021-11-18 12:18:10 -0800 | [diff] [blame] | 1059 | /* x0 = (x0 <= SDEI_EV_FAILED) ? |
| 1060 | * EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME |
| 1061 | */ |
| 1062 | cmp x0, #SDEI_EV_FAILED |
James Morse | f5df269 | 2018-01-08 15:38:12 +0000 | [diff] [blame] | 1063 | mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE |
| 1064 | mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME |
| 1065 | csel x0, x2, x3, ls |
| 1066 | |
James Morse | f5df269 | 2018-01-08 15:38:12 +0000 | [diff] [blame] | 1067 | ldr_l x2, sdei_exit_mode |
James Morse | 79e9aa5 | 2018-01-08 15:38:18 +0000 | [diff] [blame] | 1068 | |
D Scott Phillips | 5cd474e | 2023-06-26 17:29:39 -0700 | [diff] [blame] | 1069 | /* Clear the registered-event seen by crash_smp_send_stop() */ |
| 1070 | ldrb w3, [x4, #SDEI_EVENT_PRIORITY] |
| 1071 | cbnz w3, 1f |
| 1072 | adr_this_cpu dst=x5, sym=sdei_active_normal_event, tmp=x6 |
| 1073 | b 2f |
| 1074 | 1: adr_this_cpu dst=x5, sym=sdei_active_critical_event, tmp=x6 |
| 1075 | 2: str xzr, [x5] |
| 1076 | |
James Morse | 79e9aa5 | 2018-01-08 15:38:18 +0000 | [diff] [blame] | 1077 | alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 |
| 1078 | sdei_handler_exit exit_mode=x2 |
| 1079 | alternative_else_nop_endif |
| 1080 | |
| 1081 | #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 |
Ard Biesheuvel | 211ceca | 2023-04-18 16:36:04 +0200 | [diff] [blame] | 1082 | tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline |
James Morse | 79e9aa5 | 2018-01-08 15:38:18 +0000 | [diff] [blame] | 1083 | br x5 |
| 1084 | #endif |
Mark Brown | 1242b9b | 2020-02-18 19:58:40 +0000 | [diff] [blame] | 1085 | SYM_CODE_END(__sdei_asm_handler) |
James Morse | f5df269 | 2018-01-08 15:38:12 +0000 | [diff] [blame] | 1086 | NOKPROBE(__sdei_asm_handler) |
D Scott Phillips | 5cd474e | 2023-06-26 17:29:39 -0700 | [diff] [blame] | 1087 | |
| 1088 | SYM_CODE_START(__sdei_handler_abort) |
| 1089 | mov_q x0, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME |
| 1090 | adr x1, 1f |
| 1091 | ldr_l x2, sdei_exit_mode |
| 1092 | sdei_handler_exit exit_mode=x2 |
| 1093 | // exit the handler and jump to the next instruction. |
| 1094 | // Exit will stomp x0-x17, PSTATE, ELR_ELx, and SPSR_ELx. |
| 1095 | 1: ret |
| 1096 | SYM_CODE_END(__sdei_handler_abort) |
| 1097 | NOKPROBE(__sdei_handler_abort) |
James Morse | f5df269 | 2018-01-08 15:38:12 +0000 | [diff] [blame] | 1098 | #endif /* CONFIG_ARM_SDE_INTERFACE */ |