blob: 7847dd34f86fc5ba8152ebda4cf7d4310a217d27 [file] [log] [blame]
Andreas Larssonddb27f32013-04-17 14:36:50 +02001/*
2 * Driver for Aeroflex Gaisler GRGPIO General Purpose I/O cores.
3 *
4 * 2013 (c) Aeroflex Gaisler AB
5 *
6 * This driver supports the GRGPIO GPIO core available in the GRLIB VHDL
7 * IP core library.
8 *
9 * Full documentation of the GRGPIO core can be found here:
10 * http://www.gaisler.com/products/grlib/grip.pdf
11 *
12 * See "Documentation/devicetree/bindings/gpio/gpio-grgpio.txt" for
13 * information on open firmware properties.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Contributors: Andreas Larsson <andreas@gaisler.com>
21 */
22
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/spinlock.h>
27#include <linux/io.h>
28#include <linux/of.h>
29#include <linux/of_gpio.h>
30#include <linux/of_platform.h>
31#include <linux/gpio.h>
32#include <linux/slab.h>
33#include <linux/err.h>
Linus Walleij0f4630f2015-12-04 14:02:58 +010034#include <linux/gpio/driver.h>
Andreas Larsson08ffb222013-04-17 14:36:51 +020035#include <linux/interrupt.h>
36#include <linux/irq.h>
37#include <linux/irqdomain.h>
Andreas Larssonddb27f32013-04-17 14:36:50 +020038
39#define GRGPIO_MAX_NGPIO 32
40
41#define GRGPIO_DATA 0x00
42#define GRGPIO_OUTPUT 0x04
43#define GRGPIO_DIR 0x08
44#define GRGPIO_IMASK 0x0c
45#define GRGPIO_IPOL 0x10
46#define GRGPIO_IEDGE 0x14
47#define GRGPIO_BYPASS 0x18
48#define GRGPIO_IMAP_BASE 0x20
49
Andreas Larsson08ffb222013-04-17 14:36:51 +020050/* Structure for an irq of the core - called an underlying irq */
51struct grgpio_uirq {
52 u8 refcnt; /* Reference counter to manage requesting/freeing of uirq */
53 u8 uirq; /* Underlying irq of the gpio driver */
54};
55
56/*
57 * Structure for an irq of a gpio line handed out by this driver. The index is
58 * used to map to the corresponding underlying irq.
59 */
60struct grgpio_lirq {
61 s8 index; /* Index into struct grgpio_priv's uirqs, or -1 */
62 u8 irq; /* irq for the gpio line */
63};
64
Andreas Larssonddb27f32013-04-17 14:36:50 +020065struct grgpio_priv {
Linus Walleij0f4630f2015-12-04 14:02:58 +010066 struct gpio_chip gc;
Andreas Larssonddb27f32013-04-17 14:36:50 +020067 void __iomem *regs;
68 struct device *dev;
Andreas Larsson08ffb222013-04-17 14:36:51 +020069
70 u32 imask; /* irq mask shadow register */
71
72 /*
73 * The grgpio core can have multiple "underlying" irqs. The gpio lines
74 * can be mapped to any one or none of these underlying irqs
75 * independently of each other. This driver sets up an irq domain and
76 * hands out separate irqs to each gpio line
77 */
78 struct irq_domain *domain;
79
80 /*
81 * This array contains information on each underlying irq, each
82 * irq of the grgpio core itself.
83 */
84 struct grgpio_uirq uirqs[GRGPIO_MAX_NGPIO];
85
86 /*
87 * This array contains information for each gpio line on the irqs
88 * obtains from this driver. An index value of -1 for a certain gpio
89 * line indicates that the line has no irq. Otherwise the index connects
90 * the irq to the underlying irq by pointing into the uirqs array.
91 */
92 struct grgpio_lirq lirqs[GRGPIO_MAX_NGPIO];
Andreas Larssonddb27f32013-04-17 14:36:50 +020093};
94
Andreas Larsson08ffb222013-04-17 14:36:51 +020095static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
96 int val)
97{
Linus Walleij0f4630f2015-12-04 14:02:58 +010098 struct gpio_chip *gc = &priv->gc;
99 unsigned long mask = gc->pin2mask(gc, offset);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200100
101 if (val)
102 priv->imask |= mask;
103 else
104 priv->imask &= ~mask;
Linus Walleij0f4630f2015-12-04 14:02:58 +0100105 gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200106}
107
108static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset)
109{
Linus Walleij0f4630f2015-12-04 14:02:58 +0100110 struct grgpio_priv *priv = gpiochip_get_data(gc);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200111
Dan Carpenterd3c21552014-12-17 02:53:59 +0300112 if (offset >= gc->ngpio)
Andreas Larsson08ffb222013-04-17 14:36:51 +0200113 return -ENXIO;
114
115 if (priv->lirqs[offset].index < 0)
116 return -ENXIO;
117
118 return irq_create_mapping(priv->domain, offset);
119}
120
121/* -------------------- IRQ chip functions -------------------- */
122
123static int grgpio_irq_set_type(struct irq_data *d, unsigned int type)
124{
125 struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
126 unsigned long flags;
127 u32 mask = BIT(d->hwirq);
128 u32 ipol;
129 u32 iedge;
130 u32 pol;
131 u32 edge;
132
133 switch (type) {
134 case IRQ_TYPE_LEVEL_LOW:
135 pol = 0;
136 edge = 0;
137 break;
138 case IRQ_TYPE_LEVEL_HIGH:
139 pol = mask;
140 edge = 0;
141 break;
142 case IRQ_TYPE_EDGE_FALLING:
143 pol = 0;
144 edge = mask;
145 break;
146 case IRQ_TYPE_EDGE_RISING:
147 pol = mask;
148 edge = mask;
149 break;
150 default:
151 return -EINVAL;
152 }
153
Linus Walleij0f4630f2015-12-04 14:02:58 +0100154 spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200155
Linus Walleij0f4630f2015-12-04 14:02:58 +0100156 ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
157 iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
Andreas Larsson08ffb222013-04-17 14:36:51 +0200158
Linus Walleij0f4630f2015-12-04 14:02:58 +0100159 priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);
160 priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200161
Linus Walleij0f4630f2015-12-04 14:02:58 +0100162 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200163
164 return 0;
165}
166
167static void grgpio_irq_mask(struct irq_data *d)
168{
169 struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
170 int offset = d->hwirq;
Alexandre Courbot7fa25932015-08-17 17:23:52 +0900171 unsigned long flags;
172
Linus Walleij0f4630f2015-12-04 14:02:58 +0100173 spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200174
175 grgpio_set_imask(priv, offset, 0);
Alexandre Courbot7fa25932015-08-17 17:23:52 +0900176
Linus Walleij0f4630f2015-12-04 14:02:58 +0100177 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200178}
179
180static void grgpio_irq_unmask(struct irq_data *d)
181{
182 struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
183 int offset = d->hwirq;
Alexandre Courbot7fa25932015-08-17 17:23:52 +0900184 unsigned long flags;
185
Linus Walleij0f4630f2015-12-04 14:02:58 +0100186 spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200187
188 grgpio_set_imask(priv, offset, 1);
Alexandre Courbot7fa25932015-08-17 17:23:52 +0900189
Linus Walleij0f4630f2015-12-04 14:02:58 +0100190 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200191}
192
193static struct irq_chip grgpio_irq_chip = {
194 .name = "grgpio",
195 .irq_mask = grgpio_irq_mask,
196 .irq_unmask = grgpio_irq_unmask,
197 .irq_set_type = grgpio_irq_set_type,
198};
199
200static irqreturn_t grgpio_irq_handler(int irq, void *dev)
201{
202 struct grgpio_priv *priv = dev;
Linus Walleij0f4630f2015-12-04 14:02:58 +0100203 int ngpio = priv->gc.ngpio;
Andreas Larsson08ffb222013-04-17 14:36:51 +0200204 unsigned long flags;
205 int i;
206 int match = 0;
207
Linus Walleij0f4630f2015-12-04 14:02:58 +0100208 spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200209
210 /*
211 * For each gpio line, call its interrupt handler if it its underlying
212 * irq matches the current irq that is handled.
213 */
214 for (i = 0; i < ngpio; i++) {
215 struct grgpio_lirq *lirq = &priv->lirqs[i];
216
217 if (priv->imask & BIT(i) && lirq->index >= 0 &&
218 priv->uirqs[lirq->index].uirq == irq) {
219 generic_handle_irq(lirq->irq);
220 match = 1;
221 }
222 }
223
Linus Walleij0f4630f2015-12-04 14:02:58 +0100224 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200225
226 if (!match)
227 dev_warn(priv->dev, "No gpio line matched irq %d\n", irq);
228
229 return IRQ_HANDLED;
230}
231
232/*
233 * This function will be called as a consequence of the call to
234 * irq_create_mapping in grgpio_to_irq
235 */
Sachin Kamat61e38842013-06-18 17:07:03 +0530236static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
237 irq_hw_number_t hwirq)
Andreas Larsson08ffb222013-04-17 14:36:51 +0200238{
239 struct grgpio_priv *priv = d->host_data;
240 struct grgpio_lirq *lirq;
241 struct grgpio_uirq *uirq;
242 unsigned long flags;
243 int offset = hwirq;
244 int ret = 0;
245
246 if (!priv)
247 return -EINVAL;
248
249 lirq = &priv->lirqs[offset];
250 if (lirq->index < 0)
251 return -EINVAL;
252
253 dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n",
254 irq, offset);
255
Linus Walleij0f4630f2015-12-04 14:02:58 +0100256 spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200257
258 /* Request underlying irq if not already requested */
259 lirq->irq = irq;
260 uirq = &priv->uirqs[lirq->index];
261 if (uirq->refcnt == 0) {
262 ret = request_irq(uirq->uirq, grgpio_irq_handler, 0,
263 dev_name(priv->dev), priv);
264 if (ret) {
265 dev_err(priv->dev,
266 "Could not request underlying irq %d\n",
267 uirq->uirq);
268
Linus Walleij0f4630f2015-12-04 14:02:58 +0100269 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200270
271 return ret;
272 }
273 }
274 uirq->refcnt++;
275
Linus Walleij0f4630f2015-12-04 14:02:58 +0100276 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200277
278 /* Setup irq */
279 irq_set_chip_data(irq, priv);
280 irq_set_chip_and_handler(irq, &grgpio_irq_chip,
281 handle_simple_irq);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200282 irq_set_noprobe(irq);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200283
284 return ret;
285}
286
Sachin Kamat61e38842013-06-18 17:07:03 +0530287static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
Andreas Larsson08ffb222013-04-17 14:36:51 +0200288{
289 struct grgpio_priv *priv = d->host_data;
290 int index;
291 struct grgpio_lirq *lirq;
292 struct grgpio_uirq *uirq;
293 unsigned long flags;
Linus Walleij0f4630f2015-12-04 14:02:58 +0100294 int ngpio = priv->gc.ngpio;
Andreas Larsson08ffb222013-04-17 14:36:51 +0200295 int i;
296
Andreas Larsson08ffb222013-04-17 14:36:51 +0200297 irq_set_chip_and_handler(irq, NULL, NULL);
298 irq_set_chip_data(irq, NULL);
299
Linus Walleij0f4630f2015-12-04 14:02:58 +0100300 spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200301
302 /* Free underlying irq if last user unmapped */
303 index = -1;
304 for (i = 0; i < ngpio; i++) {
305 lirq = &priv->lirqs[i];
306 if (lirq->irq == irq) {
307 grgpio_set_imask(priv, i, 0);
308 lirq->irq = 0;
309 index = lirq->index;
310 break;
311 }
312 }
313 WARN_ON(index < 0);
314
315 if (index >= 0) {
316 uirq = &priv->uirqs[lirq->index];
317 uirq->refcnt--;
318 if (uirq->refcnt == 0)
319 free_irq(uirq->uirq, priv);
320 }
321
Linus Walleij0f4630f2015-12-04 14:02:58 +0100322 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200323}
324
Krzysztof Kozlowski0b354dc2015-04-27 21:54:07 +0900325static const struct irq_domain_ops grgpio_irq_domain_ops = {
Andreas Larsson08ffb222013-04-17 14:36:51 +0200326 .map = grgpio_irq_map,
327 .unmap = grgpio_irq_unmap,
328};
329
330/* ------------------------------------------------------------ */
331
Andreas Larssonddb27f32013-04-17 14:36:50 +0200332static int grgpio_probe(struct platform_device *ofdev)
333{
334 struct device_node *np = ofdev->dev.of_node;
335 void __iomem *regs;
336 struct gpio_chip *gc;
Andreas Larssonddb27f32013-04-17 14:36:50 +0200337 struct grgpio_priv *priv;
338 struct resource *res;
339 int err;
340 u32 prop;
Andreas Larsson08ffb222013-04-17 14:36:51 +0200341 s32 *irqmap;
342 int size;
343 int i;
Andreas Larssonddb27f32013-04-17 14:36:50 +0200344
345 priv = devm_kzalloc(&ofdev->dev, sizeof(*priv), GFP_KERNEL);
346 if (!priv)
347 return -ENOMEM;
348
349 res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
350 regs = devm_ioremap_resource(&ofdev->dev, res);
351 if (IS_ERR(regs))
352 return PTR_ERR(regs);
353
Linus Walleij0f4630f2015-12-04 14:02:58 +0100354 gc = &priv->gc;
355 err = bgpio_init(gc, &ofdev->dev, 4, regs + GRGPIO_DATA,
Andreas Larssonddb27f32013-04-17 14:36:50 +0200356 regs + GRGPIO_OUTPUT, NULL, regs + GRGPIO_DIR, NULL,
357 BGPIOF_BIG_ENDIAN_BYTE_ORDER);
358 if (err) {
359 dev_err(&ofdev->dev, "bgpio_init() failed\n");
360 return err;
361 }
362
363 priv->regs = regs;
Linus Walleij0f4630f2015-12-04 14:02:58 +0100364 priv->imask = gc->read_reg(regs + GRGPIO_IMASK);
Andreas Larssonddb27f32013-04-17 14:36:50 +0200365 priv->dev = &ofdev->dev;
366
Andreas Larssonddb27f32013-04-17 14:36:50 +0200367 gc->of_node = np;
368 gc->owner = THIS_MODULE;
Andreas Larsson08ffb222013-04-17 14:36:51 +0200369 gc->to_irq = grgpio_to_irq;
Andreas Larssonddb27f32013-04-17 14:36:50 +0200370 gc->label = np->full_name;
371 gc->base = -1;
372
373 err = of_property_read_u32(np, "nbits", &prop);
374 if (err || prop <= 0 || prop > GRGPIO_MAX_NGPIO) {
375 gc->ngpio = GRGPIO_MAX_NGPIO;
376 dev_dbg(&ofdev->dev,
377 "No or invalid nbits property: assume %d\n", gc->ngpio);
378 } else {
379 gc->ngpio = prop;
380 }
381
Andreas Larsson08ffb222013-04-17 14:36:51 +0200382 /*
383 * The irqmap contains the index values indicating which underlying irq,
384 * if anyone, is connected to that line
385 */
386 irqmap = (s32 *)of_get_property(np, "irqmap", &size);
387 if (irqmap) {
388 if (size < gc->ngpio) {
389 dev_err(&ofdev->dev,
390 "irqmap shorter than ngpio (%d < %d)\n",
391 size, gc->ngpio);
392 return -EINVAL;
393 }
394
395 priv->domain = irq_domain_add_linear(np, gc->ngpio,
396 &grgpio_irq_domain_ops,
397 priv);
398 if (!priv->domain) {
399 dev_err(&ofdev->dev, "Could not add irq domain\n");
400 return -EINVAL;
401 }
402
403 for (i = 0; i < gc->ngpio; i++) {
404 struct grgpio_lirq *lirq;
405 int ret;
406
407 lirq = &priv->lirqs[i];
408 lirq->index = irqmap[i];
409
410 if (lirq->index < 0)
411 continue;
412
413 ret = platform_get_irq(ofdev, lirq->index);
414 if (ret <= 0) {
415 /*
416 * Continue without irq functionality for that
417 * gpio line
418 */
419 dev_err(priv->dev,
420 "Failed to get irq for offset %d\n", i);
421 continue;
422 }
423 priv->uirqs[lirq->index].uirq = ret;
424 }
425 }
426
Andreas Larssonddb27f32013-04-17 14:36:50 +0200427 platform_set_drvdata(ofdev, priv);
428
Linus Walleij0f4630f2015-12-04 14:02:58 +0100429 err = gpiochip_add_data(gc, priv);
Andreas Larssonddb27f32013-04-17 14:36:50 +0200430 if (err) {
431 dev_err(&ofdev->dev, "Could not add gpiochip\n");
Axel Lin879828c2014-12-20 22:47:07 +0800432 if (priv->domain)
433 irq_domain_remove(priv->domain);
Andreas Larssonddb27f32013-04-17 14:36:50 +0200434 return err;
435 }
436
Andreas Larsson08ffb222013-04-17 14:36:51 +0200437 dev_info(&ofdev->dev, "regs=0x%p, base=%d, ngpio=%d, irqs=%s\n",
438 priv->regs, gc->base, gc->ngpio, priv->domain ? "on" : "off");
Andreas Larssonddb27f32013-04-17 14:36:50 +0200439
440 return 0;
441}
442
443static int grgpio_remove(struct platform_device *ofdev)
444{
445 struct grgpio_priv *priv = platform_get_drvdata(ofdev);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200446 unsigned long flags;
447 int i;
448 int ret = 0;
Andreas Larssonddb27f32013-04-17 14:36:50 +0200449
Linus Walleij0f4630f2015-12-04 14:02:58 +0100450 spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200451
452 if (priv->domain) {
453 for (i = 0; i < GRGPIO_MAX_NGPIO; i++) {
454 if (priv->uirqs[i].refcnt != 0) {
455 ret = -EBUSY;
456 goto out;
457 }
458 }
459 }
460
Linus Walleij0f4630f2015-12-04 14:02:58 +0100461 gpiochip_remove(&priv->gc);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200462
463 if (priv->domain)
464 irq_domain_remove(priv->domain);
465
466out:
Linus Walleij0f4630f2015-12-04 14:02:58 +0100467 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
Andreas Larsson08ffb222013-04-17 14:36:51 +0200468
469 return ret;
Andreas Larssonddb27f32013-04-17 14:36:50 +0200470}
471
Jingoo Hanf77b6442014-05-07 18:03:30 +0900472static const struct of_device_id grgpio_match[] = {
Andreas Larssonddb27f32013-04-17 14:36:50 +0200473 {.name = "GAISLER_GPIO"},
474 {.name = "01_01a"},
475 {},
476};
477
478MODULE_DEVICE_TABLE(of, grgpio_match);
479
480static struct platform_driver grgpio_driver = {
481 .driver = {
482 .name = "grgpio",
Andreas Larssonddb27f32013-04-17 14:36:50 +0200483 .of_match_table = grgpio_match,
484 },
485 .probe = grgpio_probe,
486 .remove = grgpio_remove,
487};
488module_platform_driver(grgpio_driver);
489
490MODULE_AUTHOR("Aeroflex Gaisler AB.");
491MODULE_DESCRIPTION("Driver for Aeroflex Gaisler GRGPIO");
492MODULE_LICENSE("GPL");