Kevin Cernekee | 5f7f031 | 2014-12-25 09:49:06 -0800 | [diff] [blame] | 1 | Broadcom BCM7038-style Level 1 interrupt controller |
| 2 | |
| 3 | This block is a first level interrupt controller that is typically connected |
| 4 | directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip |
| 5 | since BCM7038 has contained this hardware. |
| 6 | |
| 7 | Key elements of the hardware design include: |
| 8 | |
| 9 | - 64, 96, 128, or 160 incoming level IRQ lines |
| 10 | |
| 11 | - Most onchip peripherals are wired directly to an L1 input |
| 12 | |
| 13 | - A separate instance of the register set for each CPU, allowing individual |
| 14 | peripheral IRQs to be routed to any CPU |
| 15 | |
| 16 | - Atomic mask/unmask operations |
| 17 | |
| 18 | - No polarity/level/edge settings |
| 19 | |
| 20 | - No FIFO or priority encoder logic; software is expected to read all |
| 21 | 2-5 status words to determine which IRQs are pending |
| 22 | |
| 23 | Required properties: |
| 24 | |
| 25 | - compatible: should be "brcm,bcm7038-l1-intc" |
| 26 | - reg: specifies the base physical address and size of the registers; |
| 27 | the number of supported IRQs is inferred from the size argument |
| 28 | - interrupt-controller: identifies the node as an interrupt controller |
| 29 | - #interrupt-cells: specifies the number of cells needed to encode an interrupt |
| 30 | source, should be 1. |
| 31 | - interrupt-parent: specifies the phandle to the parent interrupt controller(s) |
| 32 | this one is cascaded from |
| 33 | - interrupts: specifies the interrupt line(s) in the interrupt-parent controller |
| 34 | node; valid values depend on the type of parent interrupt controller |
| 35 | |
| 36 | If multiple reg ranges and interrupt-parent entries are present on an SMP |
| 37 | system, the driver will allow IRQ SMP affinity to be set up through the |
| 38 | /proc/irq/ interface. In the simplest possible configuration, only one |
| 39 | reg range and one interrupt-parent is needed. |
| 40 | |
| 41 | Example: |
| 42 | |
| 43 | periph_intc: periph_intc@1041a400 { |
| 44 | compatible = "brcm,bcm7038-l1-intc"; |
| 45 | reg = <0x1041a400 0x30 0x1041a600 0x30>; |
| 46 | |
| 47 | interrupt-controller; |
| 48 | #interrupt-cells = <1>; |
| 49 | |
| 50 | interrupt-parent = <&cpu_intc>; |
| 51 | interrupts = <2>, <3>; |
| 52 | }; |