blob: f30718d7e61af0457b719732ebf6b4117e1cdc0a [file] [log] [blame]
Ben Skeggsba6e34e2014-09-23 15:42:45 +10001/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
Ben Skeggsa8c43622015-01-14 14:48:16 +100024#include "nv50.h"
Ben Skeggsba6e34e2014-09-23 15:42:45 +100025
26#include <subdev/bios.h>
27#include <subdev/bios/bit.h>
28#include <subdev/bios/pmu.h>
Ben Skeggsb7f44ef2022-06-01 20:47:48 +100029#include <subdev/pmu.h>
Ben Skeggs920c58a2016-11-08 11:54:24 +100030#include <subdev/timer.h>
Ben Skeggsba6e34e2014-09-23 15:42:45 +100031
Ben Skeggsba6e34e2014-09-23 15:42:45 +100032static void
Ben Skeggs266f8b52015-08-20 14:54:06 +100033pmu_code(struct nv50_devinit *init, u32 pmu, u32 img, u32 len, bool sec)
Ben Skeggsba6e34e2014-09-23 15:42:45 +100034{
Ben Skeggs8ac3f642015-08-20 14:54:09 +100035 struct nvkm_device *device = init->base.subdev.device;
36 struct nvkm_bios *bios = device->bios;
Ben Skeggsba6e34e2014-09-23 15:42:45 +100037 int i;
38
Ben Skeggs8ac3f642015-08-20 14:54:09 +100039 nvkm_wr32(device, 0x10a180, 0x01000000 | (sec ? 0x10000000 : 0) | pmu);
Ben Skeggsba6e34e2014-09-23 15:42:45 +100040 for (i = 0; i < len; i += 4) {
41 if ((i & 0xff) == 0)
Ben Skeggs8ac3f642015-08-20 14:54:09 +100042 nvkm_wr32(device, 0x10a188, (pmu + i) >> 8);
Ben Skeggs7f5f5182015-08-20 14:54:13 +100043 nvkm_wr32(device, 0x10a184, nvbios_rd32(bios, img + i));
Ben Skeggsba6e34e2014-09-23 15:42:45 +100044 }
45
46 while (i & 0xff) {
Ben Skeggs8ac3f642015-08-20 14:54:09 +100047 nvkm_wr32(device, 0x10a184, 0x00000000);
Ben Skeggsba6e34e2014-09-23 15:42:45 +100048 i += 4;
49 }
50}
51
52static void
Ben Skeggs266f8b52015-08-20 14:54:06 +100053pmu_data(struct nv50_devinit *init, u32 pmu, u32 img, u32 len)
Ben Skeggsba6e34e2014-09-23 15:42:45 +100054{
Ben Skeggs8ac3f642015-08-20 14:54:09 +100055 struct nvkm_device *device = init->base.subdev.device;
56 struct nvkm_bios *bios = device->bios;
Ben Skeggsba6e34e2014-09-23 15:42:45 +100057 int i;
58
Ben Skeggs8ac3f642015-08-20 14:54:09 +100059 nvkm_wr32(device, 0x10a1c0, 0x01000000 | pmu);
Ben Skeggsba6e34e2014-09-23 15:42:45 +100060 for (i = 0; i < len; i += 4)
Ben Skeggs7f5f5182015-08-20 14:54:13 +100061 nvkm_wr32(device, 0x10a1c4, nvbios_rd32(bios, img + i));
Ben Skeggsba6e34e2014-09-23 15:42:45 +100062}
63
64static u32
Ben Skeggs266f8b52015-08-20 14:54:06 +100065pmu_args(struct nv50_devinit *init, u32 argp, u32 argi)
Ben Skeggsba6e34e2014-09-23 15:42:45 +100066{
Ben Skeggs8ac3f642015-08-20 14:54:09 +100067 struct nvkm_device *device = init->base.subdev.device;
68 nvkm_wr32(device, 0x10a1c0, argp);
69 nvkm_wr32(device, 0x10a1c0, nvkm_rd32(device, 0x10a1c4) + argi);
70 return nvkm_rd32(device, 0x10a1c4);
Ben Skeggsba6e34e2014-09-23 15:42:45 +100071}
72
73static void
Ben Skeggs266f8b52015-08-20 14:54:06 +100074pmu_exec(struct nv50_devinit *init, u32 init_addr)
Ben Skeggsba6e34e2014-09-23 15:42:45 +100075{
Ben Skeggs8ac3f642015-08-20 14:54:09 +100076 struct nvkm_device *device = init->base.subdev.device;
77 nvkm_wr32(device, 0x10a104, init_addr);
78 nvkm_wr32(device, 0x10a10c, 0x00000000);
79 nvkm_wr32(device, 0x10a100, 0x00000002);
Ben Skeggsba6e34e2014-09-23 15:42:45 +100080}
81
82static int
Ben Skeggs266f8b52015-08-20 14:54:06 +100083pmu_load(struct nv50_devinit *init, u8 type, bool post,
Ben Skeggsba6e34e2014-09-23 15:42:45 +100084 u32 *init_addr_pmu, u32 *args_addr_pmu)
85{
Ben Skeggsaa860e42015-08-20 14:54:12 +100086 struct nvkm_subdev *subdev = &init->base.subdev;
87 struct nvkm_bios *bios = subdev->device->bios;
Ben Skeggsba6e34e2014-09-23 15:42:45 +100088 struct nvbios_pmuR pmu;
Ben Skeggsb7f44ef2022-06-01 20:47:48 +100089 int ret;
Ben Skeggsba6e34e2014-09-23 15:42:45 +100090
Ben Skeggs3483f0812018-09-13 10:56:38 +100091 if (!nvbios_pmuRm(bios, type, &pmu))
Ben Skeggsba6e34e2014-09-23 15:42:45 +100092 return -EINVAL;
Ben Skeggsba6e34e2014-09-23 15:42:45 +100093
Ben Skeggsb7f44ef2022-06-01 20:47:48 +100094 if (!post || !subdev->device->pmu)
Ben Skeggsba6e34e2014-09-23 15:42:45 +100095 return 0;
96
Ben Skeggsb7f44ef2022-06-01 20:47:48 +100097 ret = nvkm_falcon_reset(&subdev->device->pmu->falcon);
98 if (ret)
99 return ret;
100
Ben Skeggs266f8b52015-08-20 14:54:06 +1000101 pmu_code(init, pmu.boot_addr_pmu, pmu.boot_addr, pmu.boot_size, false);
102 pmu_code(init, pmu.code_addr_pmu, pmu.code_addr, pmu.code_size, true);
103 pmu_data(init, pmu.data_addr_pmu, pmu.data_addr, pmu.data_size);
Ben Skeggsba6e34e2014-09-23 15:42:45 +1000104
105 if (init_addr_pmu) {
106 *init_addr_pmu = pmu.init_addr_pmu;
107 *args_addr_pmu = pmu.args_addr_pmu;
108 return 0;
109 }
110
Ben Skeggs266f8b52015-08-20 14:54:06 +1000111 return pmu_exec(init, pmu.init_addr_pmu), 0;
Ben Skeggsba6e34e2014-09-23 15:42:45 +1000112}
113
Ben Skeggsa31e24a2018-12-11 14:50:02 +1000114void
115gm200_devinit_preos(struct nv50_devinit *init, bool post)
116{
117 /* Optional: Execute PRE_OS application on PMU, which should at
118 * least take care of fans until a full PMU has been loaded.
119 */
120 pmu_load(init, 0x01, post, NULL, NULL);
121}
122
Ben Skeggs8769dc982018-05-08 20:39:47 +1000123int
Ben Skeggsdb1eb522016-02-11 08:35:32 +1000124gm200_devinit_post(struct nvkm_devinit *base, bool post)
Ben Skeggsba6e34e2014-09-23 15:42:45 +1000125{
Ben Skeggs151abd42015-08-20 14:54:20 +1000126 struct nv50_devinit *init = nv50_devinit(base);
127 struct nvkm_subdev *subdev = &init->base.subdev;
Ben Skeggsaa860e42015-08-20 14:54:12 +1000128 struct nvkm_device *device = subdev->device;
Ben Skeggs8ac3f642015-08-20 14:54:09 +1000129 struct nvkm_bios *bios = device->bios;
Ben Skeggsba6e34e2014-09-23 15:42:45 +1000130 struct bit_entry bit_I;
Ben Skeggs266f8b52015-08-20 14:54:06 +1000131 u32 exec, args;
Ben Skeggsba6e34e2014-09-23 15:42:45 +1000132 int ret;
133
134 if (bit_entry(bios, 'I', &bit_I) || bit_I.version != 1 ||
135 bit_I.length < 0x1c) {
Ben Skeggsaa860e42015-08-20 14:54:12 +1000136 nvkm_error(subdev, "VBIOS PMU init data not found\n");
Ben Skeggsba6e34e2014-09-23 15:42:45 +1000137 return -EINVAL;
138 }
139
Ben Skeggs3483f0812018-09-13 10:56:38 +1000140 /* Upload DEVINIT application from VBIOS onto PMU. */
Ben Skeggs266f8b52015-08-20 14:54:06 +1000141 ret = pmu_load(init, 0x04, post, &exec, &args);
Ben Skeggs3483f0812018-09-13 10:56:38 +1000142 if (ret) {
143 nvkm_error(subdev, "VBIOS PMU/DEVINIT not found\n");
Ben Skeggsba6e34e2014-09-23 15:42:45 +1000144 return ret;
Ben Skeggs3483f0812018-09-13 10:56:38 +1000145 }
Ben Skeggsba6e34e2014-09-23 15:42:45 +1000146
Ben Skeggs3483f0812018-09-13 10:56:38 +1000147 /* Upload tables required by opcodes in boot scripts. */
Ben Skeggsba6e34e2014-09-23 15:42:45 +1000148 if (post) {
Ben Skeggs266f8b52015-08-20 14:54:06 +1000149 u32 pmu = pmu_args(init, args + 0x08, 0x08);
Ben Skeggs7f5f5182015-08-20 14:54:13 +1000150 u32 img = nvbios_rd16(bios, bit_I.offset + 0x14);
151 u32 len = nvbios_rd16(bios, bit_I.offset + 0x16);
Ben Skeggs266f8b52015-08-20 14:54:06 +1000152 pmu_data(init, pmu, img, len);
Ben Skeggsba6e34e2014-09-23 15:42:45 +1000153 }
154
Ben Skeggs3483f0812018-09-13 10:56:38 +1000155 /* Upload boot scripts. */
Ben Skeggsba6e34e2014-09-23 15:42:45 +1000156 if (post) {
Ben Skeggs266f8b52015-08-20 14:54:06 +1000157 u32 pmu = pmu_args(init, args + 0x08, 0x10);
Ben Skeggs7f5f5182015-08-20 14:54:13 +1000158 u32 img = nvbios_rd16(bios, bit_I.offset + 0x18);
159 u32 len = nvbios_rd16(bios, bit_I.offset + 0x1a);
Ben Skeggs266f8b52015-08-20 14:54:06 +1000160 pmu_data(init, pmu, img, len);
Ben Skeggsba6e34e2014-09-23 15:42:45 +1000161 }
162
Ben Skeggs3483f0812018-09-13 10:56:38 +1000163 /* Execute DEVINIT. */
Ben Skeggsba6e34e2014-09-23 15:42:45 +1000164 if (post) {
Ben Skeggs8ac3f642015-08-20 14:54:09 +1000165 nvkm_wr32(device, 0x10a040, 0x00005000);
Ben Skeggs266f8b52015-08-20 14:54:06 +1000166 pmu_exec(init, exec);
Ben Skeggs920c58a2016-11-08 11:54:24 +1000167 if (nvkm_msec(device, 2000,
168 if (nvkm_rd32(device, 0x10a040) & 0x00002000)
169 break;
170 ) < 0)
171 return -ETIMEDOUT;
Ben Skeggsba6e34e2014-09-23 15:42:45 +1000172 }
173
Ben Skeggsa31e24a2018-12-11 14:50:02 +1000174 gm200_devinit_preos(init, post);
Ben Skeggs0a6986c2018-09-04 15:56:57 +1000175 return 0;
Ben Skeggsba6e34e2014-09-23 15:42:45 +1000176}
177
Ben Skeggs151abd42015-08-20 14:54:20 +1000178static const struct nvkm_devinit_func
Ben Skeggsdb1eb522016-02-11 08:35:32 +1000179gm200_devinit = {
Alexandre Courbota6a0f672016-02-11 11:10:04 +0900180 .preinit = gf100_devinit_preinit,
Ben Skeggs151abd42015-08-20 14:54:20 +1000181 .init = nv50_devinit_init,
Ben Skeggsdb1eb522016-02-11 08:35:32 +1000182 .post = gm200_devinit_post,
Ben Skeggsa8c43622015-01-14 14:48:16 +1000183 .pll_set = gf100_devinit_pll_set,
Ben Skeggsba6e34e2014-09-23 15:42:45 +1000184 .disable = gm107_devinit_disable,
Ben Skeggs151abd42015-08-20 14:54:20 +1000185};
186
187int
Ben Skeggs4a34fd02020-12-04 11:04:41 +1000188gm200_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
189 struct nvkm_devinit **pinit)
Ben Skeggs151abd42015-08-20 14:54:20 +1000190{
Ben Skeggs4a34fd02020-12-04 11:04:41 +1000191 return nv50_devinit_new_(&gm200_devinit, device, type, inst, pinit);
Ben Skeggs151abd42015-08-20 14:54:20 +1000192}