Thomas Gleixner | 2025cf9 | 2019-05-29 07:18:02 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Tony Luck | 5c71ad1 | 2017-03-09 01:45:39 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Register bitfield descriptions for Pondicherry2 memory controller. |
| 4 | * |
| 5 | * Copyright (c) 2016, Intel Corporation. |
Tony Luck | 5c71ad1 | 2017-03-09 01:45:39 +0800 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef _PND2_REGS_H |
| 9 | #define _PND2_REGS_H |
| 10 | |
| 11 | struct b_cr_touud_lo_pci { |
| 12 | u32 lock : 1; |
| 13 | u32 reserved_1 : 19; |
| 14 | u32 touud : 12; |
| 15 | }; |
| 16 | |
| 17 | #define b_cr_touud_lo_pci_port 0x4c |
| 18 | #define b_cr_touud_lo_pci_offset 0xa8 |
| 19 | #define b_cr_touud_lo_pci_r_opcode 0x04 |
| 20 | |
| 21 | struct b_cr_touud_hi_pci { |
| 22 | u32 touud : 7; |
| 23 | u32 reserved_0 : 25; |
| 24 | }; |
| 25 | |
| 26 | #define b_cr_touud_hi_pci_port 0x4c |
| 27 | #define b_cr_touud_hi_pci_offset 0xac |
| 28 | #define b_cr_touud_hi_pci_r_opcode 0x04 |
| 29 | |
| 30 | struct b_cr_tolud_pci { |
| 31 | u32 lock : 1; |
| 32 | u32 reserved_0 : 19; |
| 33 | u32 tolud : 12; |
| 34 | }; |
| 35 | |
| 36 | #define b_cr_tolud_pci_port 0x4c |
| 37 | #define b_cr_tolud_pci_offset 0xbc |
| 38 | #define b_cr_tolud_pci_r_opcode 0x04 |
| 39 | |
| 40 | struct b_cr_mchbar_lo_pci { |
| 41 | u32 enable : 1; |
| 42 | u32 pad_3_1 : 3; |
| 43 | u32 pad_14_4: 11; |
| 44 | u32 base: 17; |
| 45 | }; |
| 46 | |
| 47 | struct b_cr_mchbar_hi_pci { |
| 48 | u32 base : 7; |
| 49 | u32 pad_31_7 : 25; |
| 50 | }; |
| 51 | |
| 52 | /* Symmetric region */ |
| 53 | struct b_cr_slice_channel_hash { |
| 54 | u64 slice_1_disabled : 1; |
| 55 | u64 hvm_mode : 1; |
| 56 | u64 interleave_mode : 2; |
| 57 | u64 slice_0_mem_disabled : 1; |
| 58 | u64 reserved_0 : 1; |
| 59 | u64 slice_hash_mask : 14; |
| 60 | u64 reserved_1 : 11; |
| 61 | u64 enable_pmi_dual_data_mode : 1; |
| 62 | u64 ch_1_disabled : 1; |
| 63 | u64 reserved_2 : 1; |
| 64 | u64 sym_slice0_channel_enabled : 2; |
| 65 | u64 sym_slice1_channel_enabled : 2; |
| 66 | u64 ch_hash_mask : 14; |
| 67 | u64 reserved_3 : 11; |
| 68 | u64 lock : 1; |
| 69 | }; |
| 70 | |
| 71 | #define b_cr_slice_channel_hash_port 0x4c |
| 72 | #define b_cr_slice_channel_hash_offset 0x4c58 |
| 73 | #define b_cr_slice_channel_hash_r_opcode 0x06 |
| 74 | |
| 75 | struct b_cr_mot_out_base_mchbar { |
| 76 | u32 reserved_0 : 14; |
| 77 | u32 mot_out_base : 15; |
| 78 | u32 reserved_1 : 1; |
| 79 | u32 tr_en : 1; |
| 80 | u32 imr_en : 1; |
| 81 | }; |
| 82 | |
| 83 | #define b_cr_mot_out_base_mchbar_port 0x4c |
| 84 | #define b_cr_mot_out_base_mchbar_offset 0x6af0 |
| 85 | #define b_cr_mot_out_base_mchbar_r_opcode 0x00 |
| 86 | |
| 87 | struct b_cr_mot_out_mask_mchbar { |
| 88 | u32 reserved_0 : 14; |
| 89 | u32 mot_out_mask : 15; |
| 90 | u32 reserved_1 : 1; |
| 91 | u32 ia_iwb_en : 1; |
| 92 | u32 gt_iwb_en : 1; |
| 93 | }; |
| 94 | |
| 95 | #define b_cr_mot_out_mask_mchbar_port 0x4c |
| 96 | #define b_cr_mot_out_mask_mchbar_offset 0x6af4 |
| 97 | #define b_cr_mot_out_mask_mchbar_r_opcode 0x00 |
| 98 | |
| 99 | struct b_cr_asym_mem_region0_mchbar { |
| 100 | u32 pad : 4; |
| 101 | u32 slice0_asym_base : 11; |
| 102 | u32 pad_18_15 : 4; |
| 103 | u32 slice0_asym_limit : 11; |
| 104 | u32 slice0_asym_channel_select : 1; |
| 105 | u32 slice0_asym_enable : 1; |
| 106 | }; |
| 107 | |
| 108 | #define b_cr_asym_mem_region0_mchbar_port 0x4c |
| 109 | #define b_cr_asym_mem_region0_mchbar_offset 0x6e40 |
| 110 | #define b_cr_asym_mem_region0_mchbar_r_opcode 0x00 |
| 111 | |
| 112 | struct b_cr_asym_mem_region1_mchbar { |
| 113 | u32 pad : 4; |
| 114 | u32 slice1_asym_base : 11; |
| 115 | u32 pad_18_15 : 4; |
| 116 | u32 slice1_asym_limit : 11; |
| 117 | u32 slice1_asym_channel_select : 1; |
| 118 | u32 slice1_asym_enable : 1; |
| 119 | }; |
| 120 | |
| 121 | #define b_cr_asym_mem_region1_mchbar_port 0x4c |
| 122 | #define b_cr_asym_mem_region1_mchbar_offset 0x6e44 |
| 123 | #define b_cr_asym_mem_region1_mchbar_r_opcode 0x00 |
| 124 | |
| 125 | /* Some bit fields moved in above two structs on Denverton */ |
| 126 | struct b_cr_asym_mem_region_denverton { |
| 127 | u32 pad : 4; |
| 128 | u32 slice_asym_base : 8; |
| 129 | u32 pad_19_12 : 8; |
| 130 | u32 slice_asym_limit : 8; |
| 131 | u32 pad_28_30 : 3; |
| 132 | u32 slice_asym_enable : 1; |
| 133 | }; |
| 134 | |
| 135 | struct b_cr_asym_2way_mem_region_mchbar { |
| 136 | u32 pad : 2; |
| 137 | u32 asym_2way_intlv_mode : 2; |
| 138 | u32 asym_2way_base : 11; |
| 139 | u32 pad_16_15 : 2; |
| 140 | u32 asym_2way_limit : 11; |
| 141 | u32 pad_30_28 : 3; |
| 142 | u32 asym_2way_interleave_enable : 1; |
| 143 | }; |
| 144 | |
| 145 | #define b_cr_asym_2way_mem_region_mchbar_port 0x4c |
| 146 | #define b_cr_asym_2way_mem_region_mchbar_offset 0x6e50 |
| 147 | #define b_cr_asym_2way_mem_region_mchbar_r_opcode 0x00 |
| 148 | |
| 149 | /* Apollo Lake d-unit */ |
| 150 | |
| 151 | struct d_cr_drp0 { |
| 152 | u32 rken0 : 1; |
| 153 | u32 rken1 : 1; |
| 154 | u32 ddmen : 1; |
| 155 | u32 rsvd3 : 1; |
| 156 | u32 dwid : 2; |
| 157 | u32 dden : 3; |
| 158 | u32 rsvd13_9 : 5; |
| 159 | u32 rsien : 1; |
| 160 | u32 bahen : 1; |
| 161 | u32 rsvd18_16 : 3; |
| 162 | u32 caswizzle : 2; |
| 163 | u32 eccen : 1; |
| 164 | u32 dramtype : 3; |
| 165 | u32 blmode : 3; |
| 166 | u32 addrdec : 2; |
| 167 | u32 dramdevice_pr : 2; |
| 168 | }; |
| 169 | |
| 170 | #define d_cr_drp0_offset 0x1400 |
| 171 | #define d_cr_drp0_r_opcode 0x00 |
| 172 | |
| 173 | /* Denverton d-unit */ |
| 174 | |
| 175 | struct d_cr_dsch { |
| 176 | u32 ch0en : 1; |
| 177 | u32 ch1en : 1; |
| 178 | u32 ddr4en : 1; |
| 179 | u32 coldwake : 1; |
| 180 | u32 newbypdis : 1; |
| 181 | u32 chan_width : 1; |
| 182 | u32 rsvd6_6 : 1; |
| 183 | u32 ooodis : 1; |
| 184 | u32 rsvd18_8 : 11; |
| 185 | u32 ic : 1; |
| 186 | u32 rsvd31_20 : 12; |
| 187 | }; |
| 188 | |
| 189 | #define d_cr_dsch_port 0x16 |
| 190 | #define d_cr_dsch_offset 0x0 |
| 191 | #define d_cr_dsch_r_opcode 0x0 |
| 192 | |
| 193 | struct d_cr_ecc_ctrl { |
| 194 | u32 eccen : 1; |
| 195 | u32 rsvd31_1 : 31; |
| 196 | }; |
| 197 | |
| 198 | #define d_cr_ecc_ctrl_offset 0x180 |
| 199 | #define d_cr_ecc_ctrl_r_opcode 0x0 |
| 200 | |
| 201 | struct d_cr_drp { |
| 202 | u32 rken0 : 1; |
| 203 | u32 rken1 : 1; |
| 204 | u32 rken2 : 1; |
| 205 | u32 rken3 : 1; |
| 206 | u32 dimmdwid0 : 2; |
| 207 | u32 dimmdden0 : 2; |
| 208 | u32 dimmdwid1 : 2; |
| 209 | u32 dimmdden1 : 2; |
| 210 | u32 rsvd15_12 : 4; |
| 211 | u32 dimmflip : 1; |
| 212 | u32 rsvd31_17 : 15; |
| 213 | }; |
| 214 | |
| 215 | #define d_cr_drp_offset 0x158 |
| 216 | #define d_cr_drp_r_opcode 0x0 |
| 217 | |
| 218 | struct d_cr_dmap { |
| 219 | u32 ba0 : 5; |
| 220 | u32 ba1 : 5; |
| 221 | u32 bg0 : 5; /* if ddr3, ba2 = bg0 */ |
| 222 | u32 bg1 : 5; /* if ddr3, ba3 = bg1 */ |
| 223 | u32 rs0 : 5; |
| 224 | u32 rs1 : 5; |
| 225 | u32 rsvd : 2; |
| 226 | }; |
| 227 | |
| 228 | #define d_cr_dmap_offset 0x174 |
| 229 | #define d_cr_dmap_r_opcode 0x0 |
| 230 | |
| 231 | struct d_cr_dmap1 { |
| 232 | u32 ca11 : 6; |
| 233 | u32 bxor : 1; |
| 234 | u32 rsvd : 25; |
| 235 | }; |
| 236 | |
| 237 | #define d_cr_dmap1_offset 0xb4 |
| 238 | #define d_cr_dmap1_r_opcode 0x0 |
| 239 | |
| 240 | struct d_cr_dmap2 { |
| 241 | u32 row0 : 5; |
| 242 | u32 row1 : 5; |
| 243 | u32 row2 : 5; |
| 244 | u32 row3 : 5; |
| 245 | u32 row4 : 5; |
| 246 | u32 row5 : 5; |
| 247 | u32 rsvd : 2; |
| 248 | }; |
| 249 | |
| 250 | #define d_cr_dmap2_offset 0x148 |
| 251 | #define d_cr_dmap2_r_opcode 0x0 |
| 252 | |
| 253 | struct d_cr_dmap3 { |
| 254 | u32 row6 : 5; |
| 255 | u32 row7 : 5; |
| 256 | u32 row8 : 5; |
| 257 | u32 row9 : 5; |
| 258 | u32 row10 : 5; |
| 259 | u32 row11 : 5; |
| 260 | u32 rsvd : 2; |
| 261 | }; |
| 262 | |
| 263 | #define d_cr_dmap3_offset 0x14c |
| 264 | #define d_cr_dmap3_r_opcode 0x0 |
| 265 | |
| 266 | struct d_cr_dmap4 { |
| 267 | u32 row12 : 5; |
| 268 | u32 row13 : 5; |
| 269 | u32 row14 : 5; |
| 270 | u32 row15 : 5; |
| 271 | u32 row16 : 5; |
| 272 | u32 row17 : 5; |
| 273 | u32 rsvd : 2; |
| 274 | }; |
| 275 | |
| 276 | #define d_cr_dmap4_offset 0x150 |
| 277 | #define d_cr_dmap4_r_opcode 0x0 |
| 278 | |
| 279 | struct d_cr_dmap5 { |
| 280 | u32 ca3 : 4; |
| 281 | u32 ca4 : 4; |
| 282 | u32 ca5 : 4; |
| 283 | u32 ca6 : 4; |
| 284 | u32 ca7 : 4; |
| 285 | u32 ca8 : 4; |
| 286 | u32 ca9 : 4; |
| 287 | u32 rsvd : 4; |
| 288 | }; |
| 289 | |
| 290 | #define d_cr_dmap5_offset 0x154 |
| 291 | #define d_cr_dmap5_r_opcode 0x0 |
| 292 | |
| 293 | #endif /* _PND2_REGS_H */ |