blob: a03a3291de84074f361725fffbd61935f0797e6d [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Dmitry Baryshkov9c636342008-09-10 05:01:17 +04002/*
3 * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
4 * which contain:
5 *
6 * Author: Nicolas Pitre
7 * Created: Dec 02, 2004
8 * Copyright: MontaVista Software Inc.
Dmitry Baryshkov9c636342008-09-10 05:01:17 +04009 */
10
11#include <linux/kernel.h>
12#include <linux/platform_device.h>
13#include <linux/interrupt.h>
14#include <linux/clk.h>
15#include <linux/delay.h>
Paul Gortmakerda155d52011-07-15 12:38:28 -040016#include <linux/module.h>
Rob Herring23019a72012-03-20 14:33:19 -050017#include <linux/io.h>
Mike Dunn3b4bc7b2013-01-07 13:55:13 -080018#include <linux/gpio.h>
Robert Jarzmika4519522018-06-17 12:50:01 +020019#include <linux/of_gpio.h>
Arnd Bergmann08d3df82019-09-01 22:26:10 +020020#include <linux/soc/pxa/cpu.h>
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040021
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040022#include <sound/pxa2xx-lib.h>
23
Arnd Bergmann22f08662019-09-02 00:02:08 +020024#include <linux/platform_data/asoc-pxa.h>
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040025
Arnd Bergmann8ff06452019-09-18 10:52:31 +020026#include "pxa2xx-ac97-regs.h"
27
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040028static DEFINE_MUTEX(car_mutex);
29static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
30static volatile long gsr_bits;
31static struct clk *ac97_clk;
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040032static struct clk *ac97conf_clk;
Robert Jarzmik26ade892009-03-15 14:10:54 +010033static int reset_gpio;
Arnd Bergmann8ff06452019-09-18 10:52:31 +020034static void __iomem *ac97_reg_base;
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040035
36/*
37 * Beware PXA27x bugs:
38 *
39 * o Slot 12 read from modem space will hang controller.
40 * o CDONE, SDONE interrupt fails after any slot 12 IO.
41 *
42 * We therefore have an hybrid approach for waiting on SDONE (interrupt or
43 * 1 jiffy timeout if interrupt never comes).
44 */
45
Robert Jarzmik6f8acad2017-09-02 21:54:06 +020046int pxa2xx_ac97_read(int slot, unsigned short reg)
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040047{
Robert Jarzmik6f8acad2017-09-02 21:54:06 +020048 int val = -ENODEV;
Arnd Bergmann8ff06452019-09-18 10:52:31 +020049 u32 __iomem *reg_addr;
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040050
Robert Jarzmik6f8acad2017-09-02 21:54:06 +020051 if (slot > 0)
52 return -ENODEV;
53
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040054 mutex_lock(&car_mutex);
55
56 /* set up primary or secondary codec space */
Marc Zyngier8825e8e2008-10-14 09:57:05 +010057 if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
Arnd Bergmann8ff06452019-09-18 10:52:31 +020058 reg_addr = ac97_reg_base +
59 (slot ? SMC_REG_BASE : PMC_REG_BASE);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040060 else
Arnd Bergmann8ff06452019-09-18 10:52:31 +020061 reg_addr = ac97_reg_base +
62 (slot ? SAC_REG_BASE : PAC_REG_BASE);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040063 reg_addr += (reg >> 1);
64
65 /* start read access across the ac97 link */
Arnd Bergmann8ff06452019-09-18 10:52:31 +020066 writel(GSR_CDONE | GSR_SDONE, ac97_reg_base + GSR);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040067 gsr_bits = 0;
Arnd Bergmann8ff06452019-09-18 10:52:31 +020068 val = (readl(reg_addr) & 0xffff);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040069 if (reg == AC97_GPIO_STATUS)
70 goto out;
Arnd Bergmann8ff06452019-09-18 10:52:31 +020071 if (wait_event_timeout(gsr_wq, (readl(ac97_reg_base + GSR) | gsr_bits) & GSR_SDONE, 1) <= 0 &&
72 !((readl(ac97_reg_base + GSR) | gsr_bits) & GSR_SDONE)) {
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040073 printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
Arnd Bergmann8ff06452019-09-18 10:52:31 +020074 __func__, reg, readl(ac97_reg_base + GSR) | gsr_bits);
Robert Jarzmik6f8acad2017-09-02 21:54:06 +020075 val = -ETIMEDOUT;
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040076 goto out;
77 }
78
79 /* valid data now */
Arnd Bergmann8ff06452019-09-18 10:52:31 +020080 writel(GSR_CDONE | GSR_SDONE, ac97_reg_base + GSR);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040081 gsr_bits = 0;
Arnd Bergmann8ff06452019-09-18 10:52:31 +020082 val = (readl(reg_addr) & 0xffff);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040083 /* but we've just started another cycle... */
Arnd Bergmann8ff06452019-09-18 10:52:31 +020084 wait_event_timeout(gsr_wq, (readl(ac97_reg_base + GSR) | gsr_bits) & GSR_SDONE, 1);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040085
86out: mutex_unlock(&car_mutex);
87 return val;
88}
89EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);
90
Robert Jarzmik6f8acad2017-09-02 21:54:06 +020091int pxa2xx_ac97_write(int slot, unsigned short reg, unsigned short val)
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040092{
Arnd Bergmann8ff06452019-09-18 10:52:31 +020093 u32 __iomem *reg_addr;
Robert Jarzmik6f8acad2017-09-02 21:54:06 +020094 int ret = 0;
Dmitry Baryshkov9c636342008-09-10 05:01:17 +040095
96 mutex_lock(&car_mutex);
97
98 /* set up primary or secondary codec space */
Marc Zyngier8825e8e2008-10-14 09:57:05 +010099 if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200100 reg_addr = ac97_reg_base +
101 (slot ? SMC_REG_BASE : PMC_REG_BASE);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400102 else
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200103 reg_addr = ac97_reg_base +
104 (slot ? SAC_REG_BASE : PAC_REG_BASE);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400105 reg_addr += (reg >> 1);
106
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200107 writel(GSR_CDONE | GSR_SDONE, ac97_reg_base + GSR);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400108 gsr_bits = 0;
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200109 writel(val, reg_addr);
110 if (wait_event_timeout(gsr_wq, (readl(ac97_reg_base + GSR) | gsr_bits) & GSR_CDONE, 1) <= 0 &&
111 !((readl(ac97_reg_base + GSR) | gsr_bits) & GSR_CDONE)) {
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400112 printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200113 __func__, reg, readl(ac97_reg_base + GSR) | gsr_bits);
Robert Jarzmik6f8acad2017-09-02 21:54:06 +0200114 ret = -EIO;
115 }
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400116
117 mutex_unlock(&car_mutex);
Robert Jarzmik6f8acad2017-09-02 21:54:06 +0200118 return ret;
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400119}
120EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);
121
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400122#ifdef CONFIG_PXA25x
123static inline void pxa_ac97_warm_pxa25x(void)
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400124{
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400125 gsr_bits = 0;
126
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200127 writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR);
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400128}
129
130static inline void pxa_ac97_cold_pxa25x(void)
131{
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200132 writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR); /* clear everything but nCRST */
133 writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR); /* then assert nCRST */
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400134
135 gsr_bits = 0;
136
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200137 writel(GCR_COLD_RST, ac97_reg_base + GCR);
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400138}
139#endif
140
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400141#ifdef CONFIG_PXA27x
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400142static inline void pxa_ac97_warm_pxa27x(void)
143{
144 gsr_bits = 0;
145
Eric Miaofb1bf8c2010-01-04 16:30:58 +0800146 /* warm reset broken on Bulverde, so manually keep AC97 reset high */
Mike Dunn053fe0f2013-01-07 13:55:14 -0800147 pxa27x_configure_ac97reset(reset_gpio, true);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400148 udelay(10);
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200149 writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR);
Mike Dunn053fe0f2013-01-07 13:55:14 -0800150 pxa27x_configure_ac97reset(reset_gpio, false);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400151 udelay(500);
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400152}
153
154static inline void pxa_ac97_cold_pxa27x(void)
155{
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200156 writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR); /* clear everything but nCRST */
157 writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR); /* then assert nCRST */
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400158
159 gsr_bits = 0;
160
161 /* PXA27x Developers Manual section 13.5.2.2.1 */
Robert Jarzmik4091d342014-06-09 21:59:12 +0200162 clk_prepare_enable(ac97conf_clk);
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400163 udelay(5);
Robert Jarzmik4091d342014-06-09 21:59:12 +0200164 clk_disable_unprepare(ac97conf_clk);
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200165 writel(GCR_COLD_RST | GCR_WARM_RST, ac97_reg_base + GCR);
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400166}
167#endif
168
169#ifdef CONFIG_PXA3xx
170static inline void pxa_ac97_warm_pxa3xx(void)
171{
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400172 gsr_bits = 0;
173
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400174 /* Can't use interrupts */
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200175 writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR);
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400176}
177
178static inline void pxa_ac97_cold_pxa3xx(void)
179{
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400180 /* Hold CLKBPB for 100us */
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200181 writel(0, ac97_reg_base + GCR);
182 writel(GCR_CLKBPB, ac97_reg_base + GCR);
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400183 udelay(100);
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200184 writel(0, ac97_reg_base + GCR);
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400185
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200186 writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR); /* clear everything but nCRST */
187 writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR); /* then assert nCRST */
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400188
189 gsr_bits = 0;
190
191 /* Can't use interrupts on PXA3xx */
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200192 writel(readl(ac97_reg_base + GCR) & (~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN)), ac97_reg_base + GCR);
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400193
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200194 writel(GCR_WARM_RST | GCR_COLD_RST, ac97_reg_base + GCR);
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400195}
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400196#endif
197
Robert Jarzmik6f8acad2017-09-02 21:54:06 +0200198bool pxa2xx_ac97_try_warm_reset(void)
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400199{
Luotao Fu057de502009-03-26 13:18:03 +0100200 unsigned long gsr;
Dmitry Eremin-Solenikovbeb02cd2013-10-17 14:01:35 +0400201 unsigned int timeout = 100;
Luotao Fu057de502009-03-26 13:18:03 +0100202
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400203#ifdef CONFIG_PXA25x
Marc Zyngier8825e8e2008-10-14 09:57:05 +0100204 if (cpu_is_pxa25x())
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400205 pxa_ac97_warm_pxa25x();
206 else
207#endif
208#ifdef CONFIG_PXA27x
209 if (cpu_is_pxa27x())
210 pxa_ac97_warm_pxa27x();
211 else
212#endif
213#ifdef CONFIG_PXA3xx
214 if (cpu_is_pxa3xx())
215 pxa_ac97_warm_pxa3xx();
216 else
217#endif
Takashi Iwai88ec7ae2013-11-05 15:33:40 +0100218 snd_BUG();
Dmitry Eremin-Solenikovbeb02cd2013-10-17 14:01:35 +0400219
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200220 while (!((readl(ac97_reg_base + GSR) | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
Dmitry Eremin-Solenikovbeb02cd2013-10-17 14:01:35 +0400221 mdelay(1);
222
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200223 gsr = readl(ac97_reg_base + GSR) | gsr_bits;
Luotao Fu057de502009-03-26 13:18:03 +0100224 if (!(gsr & (GSR_PCR | GSR_SCR))) {
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400225 printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
Luotao Fu057de502009-03-26 13:18:03 +0100226 __func__, gsr);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400227
228 return false;
229 }
230
231 return true;
232}
233EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);
234
Robert Jarzmik6f8acad2017-09-02 21:54:06 +0200235bool pxa2xx_ac97_try_cold_reset(void)
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400236{
Luotao Fu057de502009-03-26 13:18:03 +0100237 unsigned long gsr;
Dmitry Eremin-Solenikovbeb02cd2013-10-17 14:01:35 +0400238 unsigned int timeout = 1000;
Luotao Fu057de502009-03-26 13:18:03 +0100239
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400240#ifdef CONFIG_PXA25x
Marc Zyngier8825e8e2008-10-14 09:57:05 +0100241 if (cpu_is_pxa25x())
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400242 pxa_ac97_cold_pxa25x();
243 else
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400244#endif
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400245#ifdef CONFIG_PXA27x
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400246 if (cpu_is_pxa27x())
247 pxa_ac97_cold_pxa27x();
248 else
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400249#endif
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400250#ifdef CONFIG_PXA3xx
251 if (cpu_is_pxa3xx())
252 pxa_ac97_cold_pxa3xx();
253 else
254#endif
Takashi Iwai88ec7ae2013-11-05 15:33:40 +0100255 snd_BUG();
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400256
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200257 while (!((readl(ac97_reg_base + GSR) | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
Dmitry Eremin-Solenikovbeb02cd2013-10-17 14:01:35 +0400258 mdelay(1);
259
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200260 gsr = readl(ac97_reg_base + GSR) | gsr_bits;
Luotao Fu057de502009-03-26 13:18:03 +0100261 if (!(gsr & (GSR_PCR | GSR_SCR))) {
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400262 printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
Luotao Fu057de502009-03-26 13:18:03 +0100263 __func__, gsr);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400264
265 return false;
266 }
267
268 return true;
269}
270EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);
271
272
Robert Jarzmik6f8acad2017-09-02 21:54:06 +0200273void pxa2xx_ac97_finish_reset(void)
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400274{
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200275 u32 gcr = readl(ac97_reg_base + GCR);
276 gcr &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
277 gcr |= GCR_SDONE_IE|GCR_CDONE_IE;
278 writel(gcr, ac97_reg_base + GCR);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400279}
280EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);
281
282static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
283{
284 long status;
285
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200286 status = readl(ac97_reg_base + GSR);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400287 if (status) {
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200288 writel(status, ac97_reg_base + GSR);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400289 gsr_bits |= status;
290 wake_up(&gsr_wq);
291
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400292 /* Although we don't use those we still need to clear them
293 since they tend to spuriously trigger when MMC is used
294 (hardware bug? go figure)... */
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400295 if (cpu_is_pxa27x()) {
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200296 writel(MISR_EOC, ac97_reg_base + MISR);
297 writel(PISR_EOC, ac97_reg_base + PISR);
298 writel(MCSR_EOC, ac97_reg_base + MCSR);
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400299 }
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400300
301 return IRQ_HANDLED;
302 }
303
304 return IRQ_NONE;
305}
306
307#ifdef CONFIG_PM
308int pxa2xx_ac97_hw_suspend(void)
309{
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200310 writel(readl(ac97_reg_base + GCR) | (GCR_ACLINK_OFF), ac97_reg_base + GCR);
Robert Jarzmik4091d342014-06-09 21:59:12 +0200311 clk_disable_unprepare(ac97_clk);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400312 return 0;
313}
314EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);
315
316int pxa2xx_ac97_hw_resume(void)
317{
Robert Jarzmik4091d342014-06-09 21:59:12 +0200318 clk_prepare_enable(ac97_clk);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400319 return 0;
320}
321EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
322#endif
323
Bill Pembertone21596b2012-12-06 12:35:12 -0500324int pxa2xx_ac97_hw_probe(struct platform_device *dev)
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400325{
326 int ret;
Arnd Bergmann2548e6c2019-09-10 15:23:52 +0200327 int irq;
Mark Browneae17752009-04-13 11:48:03 +0100328 pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;
Robert Jarzmik26ade892009-03-15 14:10:54 +0100329
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200330 ac97_reg_base = devm_platform_ioremap_resource(dev, 0);
331 if (IS_ERR(ac97_reg_base)) {
332 dev_err(&dev->dev, "Missing MMIO resource\n");
333 return PTR_ERR(ac97_reg_base);
334 }
335
Robert Jarzmik26ade892009-03-15 14:10:54 +0100336 if (pdata) {
337 switch (pdata->reset_gpio) {
338 case 95:
339 case 113:
340 reset_gpio = pdata->reset_gpio;
341 break;
342 case 0:
343 reset_gpio = 113;
344 break;
345 case -1:
346 break;
347 default:
Takashi Iwai1f2186952009-03-19 14:08:58 +0100348 dev_err(&dev->dev, "Invalid reset GPIO %d\n",
Robert Jarzmik26ade892009-03-15 14:10:54 +0100349 pdata->reset_gpio);
350 }
Robert Jarzmika4519522018-06-17 12:50:01 +0200351 } else if (!pdata && dev->dev.of_node) {
352 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
353 if (!pdata)
354 return -ENOMEM;
355 pdata->reset_gpio = of_get_named_gpio(dev->dev.of_node,
356 "reset-gpios", 0);
357 if (pdata->reset_gpio == -ENOENT)
358 pdata->reset_gpio = -1;
359 else if (pdata->reset_gpio < 0)
360 return pdata->reset_gpio;
361 reset_gpio = pdata->reset_gpio;
Robert Jarzmik26ade892009-03-15 14:10:54 +0100362 } else {
363 if (cpu_is_pxa27x())
364 reset_gpio = 113;
365 }
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400366
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400367 if (cpu_is_pxa27x()) {
Mike Dunn3b4bc7b2013-01-07 13:55:13 -0800368 /*
369 * This gpio is needed for a work-around to a bug in the ac97
370 * controller during warm reset. The direction and level is set
371 * here so that it is an output driven high when switching from
372 * AC97_nRESET alt function to generic gpio.
373 */
374 ret = gpio_request_one(reset_gpio, GPIOF_OUT_INIT_HIGH,
375 "pxa27x ac97 reset");
376 if (ret < 0) {
377 pr_err("%s: gpio_request_one() failed: %d\n",
378 __func__, ret);
379 goto err_conf;
380 }
Mike Dunn053fe0f2013-01-07 13:55:14 -0800381 pxa27x_configure_ac97reset(reset_gpio, false);
Mike Dunn3b4bc7b2013-01-07 13:55:13 -0800382
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400383 ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
384 if (IS_ERR(ac97conf_clk)) {
385 ret = PTR_ERR(ac97conf_clk);
386 ac97conf_clk = NULL;
Dmitry Baryshkov79612332009-01-05 12:58:06 +0300387 goto err_conf;
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400388 }
389 }
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400390
391 ac97_clk = clk_get(&dev->dev, "AC97CLK");
392 if (IS_ERR(ac97_clk)) {
393 ret = PTR_ERR(ac97_clk);
394 ac97_clk = NULL;
Dmitry Baryshkov79612332009-01-05 12:58:06 +0300395 goto err_clk;
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400396 }
397
Robert Jarzmik4091d342014-06-09 21:59:12 +0200398 ret = clk_prepare_enable(ac97_clk);
Dmitry Baryshkov79612332009-01-05 12:58:06 +0300399 if (ret)
400 goto err_clk2;
401
Arnd Bergmann2548e6c2019-09-10 15:23:52 +0200402 irq = platform_get_irq(dev, 0);
Yang Yingliang46cf1952022-10-29 16:20:01 +0800403 if (irq < 0) {
404 ret = irq;
Arnd Bergmann2548e6c2019-09-10 15:23:52 +0200405 goto err_irq;
Yang Yingliang46cf1952022-10-29 16:20:01 +0800406 }
Arnd Bergmann2548e6c2019-09-10 15:23:52 +0200407
408 ret = request_irq(irq, pxa2xx_ac97_irq, 0, "AC97", NULL);
Dmitry Baryshkov79612332009-01-05 12:58:06 +0300409 if (ret < 0)
410 goto err_irq;
411
412 return 0;
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400413
414err_irq:
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200415 writel(readl(ac97_reg_base + GCR) | (GCR_ACLINK_OFF), ac97_reg_base + GCR);
Dmitry Baryshkov79612332009-01-05 12:58:06 +0300416err_clk2:
417 clk_put(ac97_clk);
418 ac97_clk = NULL;
419err_clk:
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400420 if (ac97conf_clk) {
421 clk_put(ac97conf_clk);
422 ac97conf_clk = NULL;
423 }
Dmitry Baryshkov79612332009-01-05 12:58:06 +0300424err_conf:
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400425 return ret;
426}
427EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);
428
429void pxa2xx_ac97_hw_remove(struct platform_device *dev)
430{
Mike Dunn3b4bc7b2013-01-07 13:55:13 -0800431 if (cpu_is_pxa27x())
432 gpio_free(reset_gpio);
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200433 writel(readl(ac97_reg_base + GCR) | (GCR_ACLINK_OFF), ac97_reg_base + GCR);
Arnd Bergmann2548e6c2019-09-10 15:23:52 +0200434 free_irq(platform_get_irq(dev, 0), NULL);
Dmitry Baryshkov9d1cf392008-09-10 05:01:18 +0400435 if (ac97conf_clk) {
436 clk_put(ac97conf_clk);
437 ac97conf_clk = NULL;
438 }
Robert Jarzmik4091d342014-06-09 21:59:12 +0200439 clk_disable_unprepare(ac97_clk);
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400440 clk_put(ac97_clk);
441 ac97_clk = NULL;
442}
443EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);
444
Arnd Bergmanne217b082019-09-18 09:55:23 +0200445u32 pxa2xx_ac97_read_modr(void)
446{
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200447 if (!ac97_reg_base)
448 return 0;
449
450 return readl(ac97_reg_base + MODR);
Arnd Bergmanne217b082019-09-18 09:55:23 +0200451}
452EXPORT_SYMBOL_GPL(pxa2xx_ac97_read_modr);
453
454u32 pxa2xx_ac97_read_misr(void)
455{
Arnd Bergmann8ff06452019-09-18 10:52:31 +0200456 if (!ac97_reg_base)
457 return 0;
458
459 return readl(ac97_reg_base + MISR);
Arnd Bergmanne217b082019-09-18 09:55:23 +0200460}
461EXPORT_SYMBOL_GPL(pxa2xx_ac97_read_misr);
462
Dmitry Baryshkov9c636342008-09-10 05:01:17 +0400463MODULE_AUTHOR("Nicolas Pitre");
464MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
465MODULE_LICENSE("GPL");
466