Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * offload engine driver for the Marvell XOR engine |
| 3 | * Copyright (C) 2007, 2008, Marvell International Ltd. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms and conditions of the GNU General Public License, |
| 7 | * version 2, as published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along with |
| 15 | * this program; if not, write to the Free Software Foundation, Inc., |
| 16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 17 | */ |
| 18 | |
| 19 | #include <linux/init.h> |
| 20 | #include <linux/module.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 21 | #include <linux/slab.h> |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 22 | #include <linux/delay.h> |
| 23 | #include <linux/dma-mapping.h> |
| 24 | #include <linux/spinlock.h> |
| 25 | #include <linux/interrupt.h> |
| 26 | #include <linux/platform_device.h> |
| 27 | #include <linux/memory.h> |
Andrew Lunn | c510182 | 2012-02-19 13:30:26 +0100 | [diff] [blame] | 28 | #include <linux/clk.h> |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 29 | #include <linux/of.h> |
| 30 | #include <linux/of_irq.h> |
| 31 | #include <linux/irqdomain.h> |
Arnd Bergmann | c02cecb | 2012-08-24 15:21:54 +0200 | [diff] [blame] | 32 | #include <linux/platform_data/dma-mv_xor.h> |
Russell King - ARM Linux | d2ebfb3 | 2012-03-06 22:34:26 +0000 | [diff] [blame] | 33 | |
| 34 | #include "dmaengine.h" |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 35 | #include "mv_xor.h" |
| 36 | |
| 37 | static void mv_xor_issue_pending(struct dma_chan *chan); |
| 38 | |
| 39 | #define to_mv_xor_chan(chan) \ |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 40 | container_of(chan, struct mv_xor_chan, dmachan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 41 | |
| 42 | #define to_mv_xor_slot(tx) \ |
| 43 | container_of(tx, struct mv_xor_desc_slot, async_tx) |
| 44 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 45 | #define mv_chan_to_devp(chan) \ |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 46 | ((chan)->dmadev.dev) |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 47 | |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 48 | static void mv_desc_init(struct mv_xor_desc_slot *desc, |
Lior Amsalem | ba87d13 | 2014-08-27 10:52:53 -0300 | [diff] [blame] | 49 | dma_addr_t addr, u32 byte_count, |
| 50 | enum dma_ctrl_flags flags) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 51 | { |
| 52 | struct mv_xor_desc *hw_desc = desc->hw_desc; |
| 53 | |
Ezequiel Garcia | 0e7488e | 2014-08-27 10:52:52 -0300 | [diff] [blame] | 54 | hw_desc->status = XOR_DESC_DMA_OWNED; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 55 | hw_desc->phy_next_desc = 0; |
Lior Amsalem | ba87d13 | 2014-08-27 10:52:53 -0300 | [diff] [blame] | 56 | /* Enable end-of-descriptor interrupts only for DMA_PREP_INTERRUPT */ |
| 57 | hw_desc->desc_command = (flags & DMA_PREP_INTERRUPT) ? |
| 58 | XOR_DESC_EOD_INT_EN : 0; |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 59 | hw_desc->phy_dest_addr = addr; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 60 | hw_desc->byte_count = byte_count; |
| 61 | } |
| 62 | |
| 63 | static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc, |
| 64 | u32 next_desc_addr) |
| 65 | { |
| 66 | struct mv_xor_desc *hw_desc = desc->hw_desc; |
| 67 | BUG_ON(hw_desc->phy_next_desc); |
| 68 | hw_desc->phy_next_desc = next_desc_addr; |
| 69 | } |
| 70 | |
| 71 | static void mv_desc_clear_next_desc(struct mv_xor_desc_slot *desc) |
| 72 | { |
| 73 | struct mv_xor_desc *hw_desc = desc->hw_desc; |
| 74 | hw_desc->phy_next_desc = 0; |
| 75 | } |
| 76 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 77 | static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc, |
| 78 | int index, dma_addr_t addr) |
| 79 | { |
| 80 | struct mv_xor_desc *hw_desc = desc->hw_desc; |
Thomas Petazzoni | e03bc65 | 2013-07-29 17:42:14 +0200 | [diff] [blame] | 81 | hw_desc->phy_src_addr[mv_phy_src_idx(index)] = addr; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 82 | if (desc->type == DMA_XOR) |
| 83 | hw_desc->desc_command |= (1 << index); |
| 84 | } |
| 85 | |
| 86 | static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan) |
| 87 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 88 | return readl_relaxed(XOR_CURR_DESC(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 89 | } |
| 90 | |
| 91 | static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan, |
| 92 | u32 next_desc_addr) |
| 93 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 94 | writel_relaxed(next_desc_addr, XOR_NEXT_DESC(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 95 | } |
| 96 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 97 | static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan) |
| 98 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 99 | u32 val = readl_relaxed(XOR_INTR_MASK(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 100 | val |= XOR_INTR_MASK_VALUE << (chan->idx * 16); |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 101 | writel_relaxed(val, XOR_INTR_MASK(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 102 | } |
| 103 | |
| 104 | static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan) |
| 105 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 106 | u32 intr_cause = readl_relaxed(XOR_INTR_CAUSE(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 107 | intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF; |
| 108 | return intr_cause; |
| 109 | } |
| 110 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 111 | static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan) |
| 112 | { |
Lior Amsalem | ba87d13 | 2014-08-27 10:52:53 -0300 | [diff] [blame] | 113 | u32 val; |
| 114 | |
| 115 | val = XOR_INT_END_OF_DESC | XOR_INT_END_OF_CHAIN | XOR_INT_STOPPED; |
| 116 | val = ~(val << (chan->idx * 16)); |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 117 | dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val); |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 118 | writel_relaxed(val, XOR_INTR_CAUSE(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 119 | } |
| 120 | |
| 121 | static void mv_xor_device_clear_err_status(struct mv_xor_chan *chan) |
| 122 | { |
| 123 | u32 val = 0xFFFF0000 >> (chan->idx * 16); |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 124 | writel_relaxed(val, XOR_INTR_CAUSE(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 125 | } |
| 126 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 127 | static void mv_set_mode(struct mv_xor_chan *chan, |
| 128 | enum dma_transaction_type type) |
| 129 | { |
| 130 | u32 op_mode; |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 131 | u32 config = readl_relaxed(XOR_CONFIG(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 132 | |
| 133 | switch (type) { |
| 134 | case DMA_XOR: |
| 135 | op_mode = XOR_OPERATION_MODE_XOR; |
| 136 | break; |
| 137 | case DMA_MEMCPY: |
| 138 | op_mode = XOR_OPERATION_MODE_MEMCPY; |
| 139 | break; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 140 | default: |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 141 | dev_err(mv_chan_to_devp(chan), |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 142 | "error: unsupported operation %d\n", |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 143 | type); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 144 | BUG(); |
| 145 | return; |
| 146 | } |
| 147 | |
| 148 | config &= ~0x7; |
| 149 | config |= op_mode; |
Thomas Petazzoni | e03bc65 | 2013-07-29 17:42:14 +0200 | [diff] [blame] | 150 | |
| 151 | #if defined(__BIG_ENDIAN) |
| 152 | config |= XOR_DESCRIPTOR_SWAP; |
| 153 | #else |
| 154 | config &= ~XOR_DESCRIPTOR_SWAP; |
| 155 | #endif |
| 156 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 157 | writel_relaxed(config, XOR_CONFIG(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 158 | chan->current_type = type; |
| 159 | } |
| 160 | |
| 161 | static void mv_chan_activate(struct mv_xor_chan *chan) |
| 162 | { |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 163 | dev_dbg(mv_chan_to_devp(chan), " activate chan.\n"); |
Ezequiel Garcia | 5a9a55b | 2014-05-21 14:02:35 -0700 | [diff] [blame] | 164 | |
| 165 | /* writel ensures all descriptors are flushed before activation */ |
| 166 | writel(BIT(0), XOR_ACTIVATION(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 167 | } |
| 168 | |
| 169 | static char mv_chan_is_busy(struct mv_xor_chan *chan) |
| 170 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 171 | u32 state = readl_relaxed(XOR_ACTIVATION(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 172 | |
| 173 | state = (state >> 4) & 0x3; |
| 174 | |
| 175 | return (state == 1) ? 1 : 0; |
| 176 | } |
| 177 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 178 | /** |
| 179 | * mv_xor_free_slots - flags descriptor slots for reuse |
| 180 | * @slot: Slot to free |
| 181 | * Caller must hold &mv_chan->lock while calling this function |
| 182 | */ |
| 183 | static void mv_xor_free_slots(struct mv_xor_chan *mv_chan, |
| 184 | struct mv_xor_desc_slot *slot) |
| 185 | { |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 186 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d slot %p\n", |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 187 | __func__, __LINE__, slot); |
| 188 | |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 189 | slot->slot_used = 0; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 190 | |
| 191 | } |
| 192 | |
| 193 | /* |
| 194 | * mv_xor_start_new_chain - program the engine to operate on new chain headed by |
| 195 | * sw_desc |
| 196 | * Caller must hold &mv_chan->lock while calling this function |
| 197 | */ |
| 198 | static void mv_xor_start_new_chain(struct mv_xor_chan *mv_chan, |
| 199 | struct mv_xor_desc_slot *sw_desc) |
| 200 | { |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 201 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n", |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 202 | __func__, __LINE__, sw_desc); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 203 | |
Bartlomiej Zolnierkiewicz | 48a9db4 | 2013-07-03 15:05:06 -0700 | [diff] [blame] | 204 | /* set the hardware chain */ |
| 205 | mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys); |
| 206 | |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 207 | mv_chan->pending++; |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 208 | mv_xor_issue_pending(&mv_chan->dmachan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 209 | } |
| 210 | |
| 211 | static dma_cookie_t |
| 212 | mv_xor_run_tx_complete_actions(struct mv_xor_desc_slot *desc, |
| 213 | struct mv_xor_chan *mv_chan, dma_cookie_t cookie) |
| 214 | { |
| 215 | BUG_ON(desc->async_tx.cookie < 0); |
| 216 | |
| 217 | if (desc->async_tx.cookie > 0) { |
| 218 | cookie = desc->async_tx.cookie; |
| 219 | |
| 220 | /* call the callback (must not sleep or submit new |
| 221 | * operations to this channel) |
| 222 | */ |
| 223 | if (desc->async_tx.callback) |
| 224 | desc->async_tx.callback( |
| 225 | desc->async_tx.callback_param); |
| 226 | |
Dan Williams | d38a8c6 | 2013-10-18 19:35:23 +0200 | [diff] [blame] | 227 | dma_descriptor_unmap(&desc->async_tx); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 228 | } |
| 229 | |
| 230 | /* run dependent operations */ |
Dan Williams | 07f2211 | 2009-01-05 17:14:31 -0700 | [diff] [blame] | 231 | dma_run_dependencies(&desc->async_tx); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 232 | |
| 233 | return cookie; |
| 234 | } |
| 235 | |
| 236 | static int |
| 237 | mv_xor_clean_completed_slots(struct mv_xor_chan *mv_chan) |
| 238 | { |
| 239 | struct mv_xor_desc_slot *iter, *_iter; |
| 240 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 241 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 242 | list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots, |
| 243 | completed_node) { |
| 244 | |
| 245 | if (async_tx_test_ack(&iter->async_tx)) { |
| 246 | list_del(&iter->completed_node); |
| 247 | mv_xor_free_slots(mv_chan, iter); |
| 248 | } |
| 249 | } |
| 250 | return 0; |
| 251 | } |
| 252 | |
| 253 | static int |
| 254 | mv_xor_clean_slot(struct mv_xor_desc_slot *desc, |
| 255 | struct mv_xor_chan *mv_chan) |
| 256 | { |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 257 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: desc %p flags %d\n", |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 258 | __func__, __LINE__, desc, desc->async_tx.flags); |
| 259 | list_del(&desc->chain_node); |
| 260 | /* the client is allowed to attach dependent operations |
| 261 | * until 'ack' is set |
| 262 | */ |
| 263 | if (!async_tx_test_ack(&desc->async_tx)) { |
| 264 | /* move this slot to the completed_slots */ |
| 265 | list_add_tail(&desc->completed_node, &mv_chan->completed_slots); |
| 266 | return 0; |
| 267 | } |
| 268 | |
| 269 | mv_xor_free_slots(mv_chan, desc); |
| 270 | return 0; |
| 271 | } |
| 272 | |
Ezequiel Garcia | fbeec99 | 2014-03-07 16:46:47 -0300 | [diff] [blame] | 273 | /* This function must be called with the mv_xor_chan spinlock held */ |
| 274 | static void mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 275 | { |
| 276 | struct mv_xor_desc_slot *iter, *_iter; |
| 277 | dma_cookie_t cookie = 0; |
| 278 | int busy = mv_chan_is_busy(mv_chan); |
| 279 | u32 current_desc = mv_chan_get_current_desc(mv_chan); |
| 280 | int seen_current = 0; |
| 281 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 282 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__); |
| 283 | dev_dbg(mv_chan_to_devp(mv_chan), "current_desc %x\n", current_desc); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 284 | mv_xor_clean_completed_slots(mv_chan); |
| 285 | |
| 286 | /* free completed slots from the chain starting with |
| 287 | * the oldest descriptor |
| 288 | */ |
| 289 | |
| 290 | list_for_each_entry_safe(iter, _iter, &mv_chan->chain, |
| 291 | chain_node) { |
| 292 | prefetch(_iter); |
| 293 | prefetch(&_iter->async_tx); |
| 294 | |
| 295 | /* do not advance past the current descriptor loaded into the |
| 296 | * hardware channel, subsequent descriptors are either in |
| 297 | * process or have not been submitted |
| 298 | */ |
| 299 | if (seen_current) |
| 300 | break; |
| 301 | |
| 302 | /* stop the search if we reach the current descriptor and the |
| 303 | * channel is busy |
| 304 | */ |
| 305 | if (iter->async_tx.phys == current_desc) { |
| 306 | seen_current = 1; |
| 307 | if (busy) |
| 308 | break; |
| 309 | } |
| 310 | |
| 311 | cookie = mv_xor_run_tx_complete_actions(iter, mv_chan, cookie); |
| 312 | |
| 313 | if (mv_xor_clean_slot(iter, mv_chan)) |
| 314 | break; |
| 315 | } |
| 316 | |
| 317 | if ((busy == 0) && !list_empty(&mv_chan->chain)) { |
| 318 | struct mv_xor_desc_slot *chain_head; |
| 319 | chain_head = list_entry(mv_chan->chain.next, |
| 320 | struct mv_xor_desc_slot, |
| 321 | chain_node); |
| 322 | |
| 323 | mv_xor_start_new_chain(mv_chan, chain_head); |
| 324 | } |
| 325 | |
| 326 | if (cookie > 0) |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 327 | mv_chan->dmachan.completed_cookie = cookie; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 328 | } |
| 329 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 330 | static void mv_xor_tasklet(unsigned long data) |
| 331 | { |
| 332 | struct mv_xor_chan *chan = (struct mv_xor_chan *) data; |
Ezequiel Garcia | e43147a | 2014-03-07 16:46:46 -0300 | [diff] [blame] | 333 | |
| 334 | spin_lock_bh(&chan->lock); |
Saeed Bishara | 8333f65 | 2010-12-21 16:53:39 +0200 | [diff] [blame] | 335 | mv_xor_slot_cleanup(chan); |
Ezequiel Garcia | e43147a | 2014-03-07 16:46:46 -0300 | [diff] [blame] | 336 | spin_unlock_bh(&chan->lock); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 337 | } |
| 338 | |
| 339 | static struct mv_xor_desc_slot * |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 340 | mv_xor_alloc_slot(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 341 | { |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 342 | struct mv_xor_desc_slot *iter, *_iter; |
| 343 | int retry = 0; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 344 | |
| 345 | /* start search from the last allocated descrtiptor |
| 346 | * if a contiguous allocation can not be found start searching |
| 347 | * from the beginning of the list |
| 348 | */ |
| 349 | retry: |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 350 | if (retry == 0) |
| 351 | iter = mv_chan->last_used; |
| 352 | else |
| 353 | iter = list_entry(&mv_chan->all_slots, |
| 354 | struct mv_xor_desc_slot, |
| 355 | slot_node); |
| 356 | |
| 357 | list_for_each_entry_safe_continue( |
| 358 | iter, _iter, &mv_chan->all_slots, slot_node) { |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 359 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 360 | prefetch(_iter); |
| 361 | prefetch(&_iter->async_tx); |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 362 | if (iter->slot_used) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 363 | /* give up after finding the first busy slot |
| 364 | * on the second pass through the list |
| 365 | */ |
| 366 | if (retry) |
| 367 | break; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 368 | continue; |
| 369 | } |
| 370 | |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 371 | /* pre-ack descriptor */ |
| 372 | async_tx_ack(&iter->async_tx); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 373 | |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 374 | iter->slot_used = 1; |
| 375 | INIT_LIST_HEAD(&iter->chain_node); |
| 376 | iter->async_tx.cookie = -EBUSY; |
| 377 | mv_chan->last_used = iter; |
| 378 | mv_desc_clear_next_desc(iter); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 379 | |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 380 | return iter; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 381 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 382 | } |
| 383 | if (!retry++) |
| 384 | goto retry; |
| 385 | |
| 386 | /* try to free some slots if the allocation fails */ |
| 387 | tasklet_schedule(&mv_chan->irq_tasklet); |
| 388 | |
| 389 | return NULL; |
| 390 | } |
| 391 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 392 | /************************ DMA engine API functions ****************************/ |
| 393 | static dma_cookie_t |
| 394 | mv_xor_tx_submit(struct dma_async_tx_descriptor *tx) |
| 395 | { |
| 396 | struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx); |
| 397 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan); |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 398 | struct mv_xor_desc_slot *old_chain_tail; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 399 | dma_cookie_t cookie; |
| 400 | int new_hw_chain = 1; |
| 401 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 402 | dev_dbg(mv_chan_to_devp(mv_chan), |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 403 | "%s sw_desc %p: async_tx %p\n", |
| 404 | __func__, sw_desc, &sw_desc->async_tx); |
| 405 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 406 | spin_lock_bh(&mv_chan->lock); |
Russell King - ARM Linux | 884485e | 2012-03-06 22:34:46 +0000 | [diff] [blame] | 407 | cookie = dma_cookie_assign(tx); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 408 | |
| 409 | if (list_empty(&mv_chan->chain)) |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 410 | list_add_tail(&sw_desc->chain_node, &mv_chan->chain); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 411 | else { |
| 412 | new_hw_chain = 0; |
| 413 | |
| 414 | old_chain_tail = list_entry(mv_chan->chain.prev, |
| 415 | struct mv_xor_desc_slot, |
| 416 | chain_node); |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 417 | list_add_tail(&sw_desc->chain_node, &mv_chan->chain); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 418 | |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 419 | dev_dbg(mv_chan_to_devp(mv_chan), "Append to last desc %pa\n", |
| 420 | &old_chain_tail->async_tx.phys); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 421 | |
| 422 | /* fix up the hardware chain */ |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 423 | mv_desc_set_next_desc(old_chain_tail, sw_desc->async_tx.phys); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 424 | |
| 425 | /* if the channel is not busy */ |
| 426 | if (!mv_chan_is_busy(mv_chan)) { |
| 427 | u32 current_desc = mv_chan_get_current_desc(mv_chan); |
| 428 | /* |
| 429 | * and the curren desc is the end of the chain before |
| 430 | * the append, then we need to start the channel |
| 431 | */ |
| 432 | if (current_desc == old_chain_tail->async_tx.phys) |
| 433 | new_hw_chain = 1; |
| 434 | } |
| 435 | } |
| 436 | |
| 437 | if (new_hw_chain) |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 438 | mv_xor_start_new_chain(mv_chan, sw_desc); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 439 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 440 | spin_unlock_bh(&mv_chan->lock); |
| 441 | |
| 442 | return cookie; |
| 443 | } |
| 444 | |
| 445 | /* returns the number of allocated descriptors */ |
Dan Williams | aa1e6f1 | 2009-01-06 11:38:17 -0700 | [diff] [blame] | 446 | static int mv_xor_alloc_chan_resources(struct dma_chan *chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 447 | { |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 448 | void *virt_desc; |
| 449 | dma_addr_t dma_desc; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 450 | int idx; |
| 451 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
| 452 | struct mv_xor_desc_slot *slot = NULL; |
Thomas Petazzoni | b503fa0 | 2012-11-15 15:55:30 +0100 | [diff] [blame] | 453 | int num_descs_in_pool = MV_XOR_POOL_SIZE/MV_XOR_SLOT_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 454 | |
| 455 | /* Allocate descriptor slots */ |
| 456 | idx = mv_chan->slots_allocated; |
| 457 | while (idx < num_descs_in_pool) { |
| 458 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); |
| 459 | if (!slot) { |
Ezequiel Garcia | b8291dd | 2014-08-27 10:52:49 -0300 | [diff] [blame] | 460 | dev_info(mv_chan_to_devp(mv_chan), |
| 461 | "channel only initialized %d descriptor slots", |
| 462 | idx); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 463 | break; |
| 464 | } |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 465 | virt_desc = mv_chan->dma_desc_pool_virt; |
| 466 | slot->hw_desc = virt_desc + idx * MV_XOR_SLOT_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 467 | |
| 468 | dma_async_tx_descriptor_init(&slot->async_tx, chan); |
| 469 | slot->async_tx.tx_submit = mv_xor_tx_submit; |
| 470 | INIT_LIST_HEAD(&slot->chain_node); |
| 471 | INIT_LIST_HEAD(&slot->slot_node); |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 472 | dma_desc = mv_chan->dma_desc_pool; |
| 473 | slot->async_tx.phys = dma_desc + idx * MV_XOR_SLOT_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 474 | slot->idx = idx++; |
| 475 | |
| 476 | spin_lock_bh(&mv_chan->lock); |
| 477 | mv_chan->slots_allocated = idx; |
| 478 | list_add_tail(&slot->slot_node, &mv_chan->all_slots); |
| 479 | spin_unlock_bh(&mv_chan->lock); |
| 480 | } |
| 481 | |
| 482 | if (mv_chan->slots_allocated && !mv_chan->last_used) |
| 483 | mv_chan->last_used = list_entry(mv_chan->all_slots.next, |
| 484 | struct mv_xor_desc_slot, |
| 485 | slot_node); |
| 486 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 487 | dev_dbg(mv_chan_to_devp(mv_chan), |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 488 | "allocated %d descriptor slots last_used: %p\n", |
| 489 | mv_chan->slots_allocated, mv_chan->last_used); |
| 490 | |
| 491 | return mv_chan->slots_allocated ? : -ENOMEM; |
| 492 | } |
| 493 | |
| 494 | static struct dma_async_tx_descriptor * |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 495 | mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, |
| 496 | unsigned int src_cnt, size_t len, unsigned long flags) |
| 497 | { |
| 498 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 499 | struct mv_xor_desc_slot *sw_desc; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 500 | |
| 501 | if (unlikely(len < MV_XOR_MIN_BYTE_COUNT)) |
| 502 | return NULL; |
| 503 | |
Coly Li | 7912d300 | 2011-03-27 01:26:53 +0800 | [diff] [blame] | 504 | BUG_ON(len > MV_XOR_MAX_BYTE_COUNT); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 505 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 506 | dev_dbg(mv_chan_to_devp(mv_chan), |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 507 | "%s src_cnt: %d len: %u dest %pad flags: %ld\n", |
| 508 | __func__, src_cnt, len, &dest, flags); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 509 | |
| 510 | spin_lock_bh(&mv_chan->lock); |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 511 | sw_desc = mv_xor_alloc_slot(mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 512 | if (sw_desc) { |
| 513 | sw_desc->type = DMA_XOR; |
| 514 | sw_desc->async_tx.flags = flags; |
Lior Amsalem | ba87d13 | 2014-08-27 10:52:53 -0300 | [diff] [blame] | 515 | mv_desc_init(sw_desc, dest, len, flags); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 516 | while (src_cnt--) |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 517 | mv_desc_set_src_addr(sw_desc, src_cnt, src[src_cnt]); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 518 | } |
| 519 | spin_unlock_bh(&mv_chan->lock); |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 520 | dev_dbg(mv_chan_to_devp(mv_chan), |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 521 | "%s sw_desc %p async_tx %p \n", |
| 522 | __func__, sw_desc, &sw_desc->async_tx); |
| 523 | return sw_desc ? &sw_desc->async_tx : NULL; |
| 524 | } |
| 525 | |
Lior Amsalem | 3e4f52e | 2014-08-27 10:52:50 -0300 | [diff] [blame] | 526 | static struct dma_async_tx_descriptor * |
| 527 | mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
| 528 | size_t len, unsigned long flags) |
| 529 | { |
| 530 | /* |
| 531 | * A MEMCPY operation is identical to an XOR operation with only |
| 532 | * a single source address. |
| 533 | */ |
| 534 | return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags); |
| 535 | } |
| 536 | |
Lior Amsalem | 2284354 | 2014-08-27 10:52:55 -0300 | [diff] [blame] | 537 | static struct dma_async_tx_descriptor * |
| 538 | mv_xor_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags) |
| 539 | { |
| 540 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
| 541 | dma_addr_t src, dest; |
| 542 | size_t len; |
| 543 | |
| 544 | src = mv_chan->dummy_src_addr; |
| 545 | dest = mv_chan->dummy_dst_addr; |
| 546 | len = MV_XOR_MIN_BYTE_COUNT; |
| 547 | |
| 548 | /* |
| 549 | * We implement the DMA_INTERRUPT operation as a minimum sized |
| 550 | * XOR operation with a single dummy source address. |
| 551 | */ |
| 552 | return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags); |
| 553 | } |
| 554 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 555 | static void mv_xor_free_chan_resources(struct dma_chan *chan) |
| 556 | { |
| 557 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
| 558 | struct mv_xor_desc_slot *iter, *_iter; |
| 559 | int in_use_descs = 0; |
| 560 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 561 | spin_lock_bh(&mv_chan->lock); |
Ezequiel Garcia | e43147a | 2014-03-07 16:46:46 -0300 | [diff] [blame] | 562 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 563 | mv_xor_slot_cleanup(mv_chan); |
| 564 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 565 | list_for_each_entry_safe(iter, _iter, &mv_chan->chain, |
| 566 | chain_node) { |
| 567 | in_use_descs++; |
| 568 | list_del(&iter->chain_node); |
| 569 | } |
| 570 | list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots, |
| 571 | completed_node) { |
| 572 | in_use_descs++; |
| 573 | list_del(&iter->completed_node); |
| 574 | } |
| 575 | list_for_each_entry_safe_reverse( |
| 576 | iter, _iter, &mv_chan->all_slots, slot_node) { |
| 577 | list_del(&iter->slot_node); |
| 578 | kfree(iter); |
| 579 | mv_chan->slots_allocated--; |
| 580 | } |
| 581 | mv_chan->last_used = NULL; |
| 582 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 583 | dev_dbg(mv_chan_to_devp(mv_chan), "%s slots_allocated %d\n", |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 584 | __func__, mv_chan->slots_allocated); |
| 585 | spin_unlock_bh(&mv_chan->lock); |
| 586 | |
| 587 | if (in_use_descs) |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 588 | dev_err(mv_chan_to_devp(mv_chan), |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 589 | "freeing %d in use descriptors!\n", in_use_descs); |
| 590 | } |
| 591 | |
| 592 | /** |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 593 | * mv_xor_status - poll the status of an XOR transaction |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 594 | * @chan: XOR channel handle |
| 595 | * @cookie: XOR transaction identifier |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 596 | * @txstate: XOR transactions state holder (or NULL) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 597 | */ |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 598 | static enum dma_status mv_xor_status(struct dma_chan *chan, |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 599 | dma_cookie_t cookie, |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 600 | struct dma_tx_state *txstate) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 601 | { |
| 602 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 603 | enum dma_status ret; |
| 604 | |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 605 | ret = dma_cookie_status(chan, cookie, txstate); |
Ezequiel Garcia | 890766d | 2014-03-07 16:46:45 -0300 | [diff] [blame] | 606 | if (ret == DMA_COMPLETE) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 607 | return ret; |
Ezequiel Garcia | e43147a | 2014-03-07 16:46:46 -0300 | [diff] [blame] | 608 | |
| 609 | spin_lock_bh(&mv_chan->lock); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 610 | mv_xor_slot_cleanup(mv_chan); |
Ezequiel Garcia | e43147a | 2014-03-07 16:46:46 -0300 | [diff] [blame] | 611 | spin_unlock_bh(&mv_chan->lock); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 612 | |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 613 | return dma_cookie_status(chan, cookie, txstate); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 614 | } |
| 615 | |
| 616 | static void mv_dump_xor_regs(struct mv_xor_chan *chan) |
| 617 | { |
| 618 | u32 val; |
| 619 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 620 | val = readl_relaxed(XOR_CONFIG(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 621 | dev_err(mv_chan_to_devp(chan), "config 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 622 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 623 | val = readl_relaxed(XOR_ACTIVATION(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 624 | dev_err(mv_chan_to_devp(chan), "activation 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 625 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 626 | val = readl_relaxed(XOR_INTR_CAUSE(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 627 | dev_err(mv_chan_to_devp(chan), "intr cause 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 628 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 629 | val = readl_relaxed(XOR_INTR_MASK(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 630 | dev_err(mv_chan_to_devp(chan), "intr mask 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 631 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 632 | val = readl_relaxed(XOR_ERROR_CAUSE(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 633 | dev_err(mv_chan_to_devp(chan), "error cause 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 634 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 635 | val = readl_relaxed(XOR_ERROR_ADDR(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 636 | dev_err(mv_chan_to_devp(chan), "error addr 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 637 | } |
| 638 | |
| 639 | static void mv_xor_err_interrupt_handler(struct mv_xor_chan *chan, |
| 640 | u32 intr_cause) |
| 641 | { |
Ezequiel Garcia | 0e7488e | 2014-08-27 10:52:52 -0300 | [diff] [blame] | 642 | if (intr_cause & XOR_INT_ERR_DECODE) { |
| 643 | dev_dbg(mv_chan_to_devp(chan), "ignoring address decode error\n"); |
| 644 | return; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 645 | } |
| 646 | |
Ezequiel Garcia | 0e7488e | 2014-08-27 10:52:52 -0300 | [diff] [blame] | 647 | dev_err(mv_chan_to_devp(chan), "error on chan %d. intr cause 0x%08x\n", |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 648 | chan->idx, intr_cause); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 649 | |
| 650 | mv_dump_xor_regs(chan); |
Ezequiel Garcia | 0e7488e | 2014-08-27 10:52:52 -0300 | [diff] [blame] | 651 | WARN_ON(1); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 652 | } |
| 653 | |
| 654 | static irqreturn_t mv_xor_interrupt_handler(int irq, void *data) |
| 655 | { |
| 656 | struct mv_xor_chan *chan = data; |
| 657 | u32 intr_cause = mv_chan_get_intr_cause(chan); |
| 658 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 659 | dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 660 | |
Ezequiel Garcia | 0e7488e | 2014-08-27 10:52:52 -0300 | [diff] [blame] | 661 | if (intr_cause & XOR_INTR_ERRORS) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 662 | mv_xor_err_interrupt_handler(chan, intr_cause); |
| 663 | |
| 664 | tasklet_schedule(&chan->irq_tasklet); |
| 665 | |
| 666 | mv_xor_device_clear_eoc_cause(chan); |
| 667 | |
| 668 | return IRQ_HANDLED; |
| 669 | } |
| 670 | |
| 671 | static void mv_xor_issue_pending(struct dma_chan *chan) |
| 672 | { |
| 673 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
| 674 | |
| 675 | if (mv_chan->pending >= MV_XOR_THRESHOLD) { |
| 676 | mv_chan->pending = 0; |
| 677 | mv_chan_activate(mv_chan); |
| 678 | } |
| 679 | } |
| 680 | |
| 681 | /* |
| 682 | * Perform a transaction to verify the HW works. |
| 683 | */ |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 684 | |
Linus Torvalds | c271433 | 2012-12-14 14:54:26 -0800 | [diff] [blame] | 685 | static int mv_xor_memcpy_self_test(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 686 | { |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 687 | int i, ret; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 688 | void *src, *dest; |
| 689 | dma_addr_t src_dma, dest_dma; |
| 690 | struct dma_chan *dma_chan; |
| 691 | dma_cookie_t cookie; |
| 692 | struct dma_async_tx_descriptor *tx; |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 693 | struct dmaengine_unmap_data *unmap; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 694 | int err = 0; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 695 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 696 | src = kmalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 697 | if (!src) |
| 698 | return -ENOMEM; |
| 699 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 700 | dest = kzalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 701 | if (!dest) { |
| 702 | kfree(src); |
| 703 | return -ENOMEM; |
| 704 | } |
| 705 | |
| 706 | /* Fill in src buffer */ |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 707 | for (i = 0; i < PAGE_SIZE; i++) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 708 | ((u8 *) src)[i] = (u8)i; |
| 709 | |
Thomas Petazzoni | 275cc0c | 2012-11-15 15:09:42 +0100 | [diff] [blame] | 710 | dma_chan = &mv_chan->dmachan; |
Dan Williams | aa1e6f1 | 2009-01-06 11:38:17 -0700 | [diff] [blame] | 711 | if (mv_xor_alloc_chan_resources(dma_chan) < 1) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 712 | err = -ENODEV; |
| 713 | goto out; |
| 714 | } |
| 715 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 716 | unmap = dmaengine_get_unmap_data(dma_chan->device->dev, 2, GFP_KERNEL); |
| 717 | if (!unmap) { |
| 718 | err = -ENOMEM; |
| 719 | goto free_resources; |
| 720 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 721 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 722 | src_dma = dma_map_page(dma_chan->device->dev, virt_to_page(src), 0, |
| 723 | PAGE_SIZE, DMA_TO_DEVICE); |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 724 | unmap->addr[0] = src_dma; |
| 725 | |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 726 | ret = dma_mapping_error(dma_chan->device->dev, src_dma); |
| 727 | if (ret) { |
| 728 | err = -ENOMEM; |
| 729 | goto free_resources; |
| 730 | } |
| 731 | unmap->to_cnt = 1; |
| 732 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 733 | dest_dma = dma_map_page(dma_chan->device->dev, virt_to_page(dest), 0, |
| 734 | PAGE_SIZE, DMA_FROM_DEVICE); |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 735 | unmap->addr[1] = dest_dma; |
| 736 | |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 737 | ret = dma_mapping_error(dma_chan->device->dev, dest_dma); |
| 738 | if (ret) { |
| 739 | err = -ENOMEM; |
| 740 | goto free_resources; |
| 741 | } |
| 742 | unmap->from_cnt = 1; |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 743 | unmap->len = PAGE_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 744 | |
| 745 | tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma, |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 746 | PAGE_SIZE, 0); |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 747 | if (!tx) { |
| 748 | dev_err(dma_chan->device->dev, |
| 749 | "Self-test cannot prepare operation, disabling\n"); |
| 750 | err = -ENODEV; |
| 751 | goto free_resources; |
| 752 | } |
| 753 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 754 | cookie = mv_xor_tx_submit(tx); |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 755 | if (dma_submit_error(cookie)) { |
| 756 | dev_err(dma_chan->device->dev, |
| 757 | "Self-test submit error, disabling\n"); |
| 758 | err = -ENODEV; |
| 759 | goto free_resources; |
| 760 | } |
| 761 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 762 | mv_xor_issue_pending(dma_chan); |
| 763 | async_tx_ack(tx); |
| 764 | msleep(1); |
| 765 | |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 766 | if (mv_xor_status(dma_chan, cookie, NULL) != |
Vinod Koul | b3efb8f | 2013-10-16 20:51:04 +0530 | [diff] [blame] | 767 | DMA_COMPLETE) { |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 768 | dev_err(dma_chan->device->dev, |
| 769 | "Self-test copy timed out, disabling\n"); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 770 | err = -ENODEV; |
| 771 | goto free_resources; |
| 772 | } |
| 773 | |
Thomas Petazzoni | c35064c | 2012-11-15 13:01:59 +0100 | [diff] [blame] | 774 | dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma, |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 775 | PAGE_SIZE, DMA_FROM_DEVICE); |
| 776 | if (memcmp(src, dest, PAGE_SIZE)) { |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 777 | dev_err(dma_chan->device->dev, |
| 778 | "Self-test copy failed compare, disabling\n"); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 779 | err = -ENODEV; |
| 780 | goto free_resources; |
| 781 | } |
| 782 | |
| 783 | free_resources: |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 784 | dmaengine_unmap_put(unmap); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 785 | mv_xor_free_chan_resources(dma_chan); |
| 786 | out: |
| 787 | kfree(src); |
| 788 | kfree(dest); |
| 789 | return err; |
| 790 | } |
| 791 | |
| 792 | #define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */ |
Bill Pemberton | 463a1f8 | 2012-11-19 13:22:55 -0500 | [diff] [blame] | 793 | static int |
Thomas Petazzoni | 275cc0c | 2012-11-15 15:09:42 +0100 | [diff] [blame] | 794 | mv_xor_xor_self_test(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 795 | { |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 796 | int i, src_idx, ret; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 797 | struct page *dest; |
| 798 | struct page *xor_srcs[MV_XOR_NUM_SRC_TEST]; |
| 799 | dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST]; |
| 800 | dma_addr_t dest_dma; |
| 801 | struct dma_async_tx_descriptor *tx; |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 802 | struct dmaengine_unmap_data *unmap; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 803 | struct dma_chan *dma_chan; |
| 804 | dma_cookie_t cookie; |
| 805 | u8 cmp_byte = 0; |
| 806 | u32 cmp_word; |
| 807 | int err = 0; |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 808 | int src_count = MV_XOR_NUM_SRC_TEST; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 809 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 810 | for (src_idx = 0; src_idx < src_count; src_idx++) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 811 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); |
Roel Kluin | a09b09a | 2009-02-25 13:56:21 +0100 | [diff] [blame] | 812 | if (!xor_srcs[src_idx]) { |
| 813 | while (src_idx--) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 814 | __free_page(xor_srcs[src_idx]); |
Roel Kluin | a09b09a | 2009-02-25 13:56:21 +0100 | [diff] [blame] | 815 | return -ENOMEM; |
| 816 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 817 | } |
| 818 | |
| 819 | dest = alloc_page(GFP_KERNEL); |
Roel Kluin | a09b09a | 2009-02-25 13:56:21 +0100 | [diff] [blame] | 820 | if (!dest) { |
| 821 | while (src_idx--) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 822 | __free_page(xor_srcs[src_idx]); |
Roel Kluin | a09b09a | 2009-02-25 13:56:21 +0100 | [diff] [blame] | 823 | return -ENOMEM; |
| 824 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 825 | |
| 826 | /* Fill in src buffers */ |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 827 | for (src_idx = 0; src_idx < src_count; src_idx++) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 828 | u8 *ptr = page_address(xor_srcs[src_idx]); |
| 829 | for (i = 0; i < PAGE_SIZE; i++) |
| 830 | ptr[i] = (1 << src_idx); |
| 831 | } |
| 832 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 833 | for (src_idx = 0; src_idx < src_count; src_idx++) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 834 | cmp_byte ^= (u8) (1 << src_idx); |
| 835 | |
| 836 | cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | |
| 837 | (cmp_byte << 8) | cmp_byte; |
| 838 | |
| 839 | memset(page_address(dest), 0, PAGE_SIZE); |
| 840 | |
Thomas Petazzoni | 275cc0c | 2012-11-15 15:09:42 +0100 | [diff] [blame] | 841 | dma_chan = &mv_chan->dmachan; |
Dan Williams | aa1e6f1 | 2009-01-06 11:38:17 -0700 | [diff] [blame] | 842 | if (mv_xor_alloc_chan_resources(dma_chan) < 1) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 843 | err = -ENODEV; |
| 844 | goto out; |
| 845 | } |
| 846 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 847 | unmap = dmaengine_get_unmap_data(dma_chan->device->dev, src_count + 1, |
| 848 | GFP_KERNEL); |
| 849 | if (!unmap) { |
| 850 | err = -ENOMEM; |
| 851 | goto free_resources; |
| 852 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 853 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 854 | /* test xor */ |
| 855 | for (i = 0; i < src_count; i++) { |
| 856 | unmap->addr[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i], |
| 857 | 0, PAGE_SIZE, DMA_TO_DEVICE); |
| 858 | dma_srcs[i] = unmap->addr[i]; |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 859 | ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[i]); |
| 860 | if (ret) { |
| 861 | err = -ENOMEM; |
| 862 | goto free_resources; |
| 863 | } |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 864 | unmap->to_cnt++; |
| 865 | } |
| 866 | |
| 867 | unmap->addr[src_count] = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE, |
| 868 | DMA_FROM_DEVICE); |
| 869 | dest_dma = unmap->addr[src_count]; |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 870 | ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[src_count]); |
| 871 | if (ret) { |
| 872 | err = -ENOMEM; |
| 873 | goto free_resources; |
| 874 | } |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 875 | unmap->from_cnt = 1; |
| 876 | unmap->len = PAGE_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 877 | |
| 878 | tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs, |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 879 | src_count, PAGE_SIZE, 0); |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 880 | if (!tx) { |
| 881 | dev_err(dma_chan->device->dev, |
| 882 | "Self-test cannot prepare operation, disabling\n"); |
| 883 | err = -ENODEV; |
| 884 | goto free_resources; |
| 885 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 886 | |
| 887 | cookie = mv_xor_tx_submit(tx); |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 888 | if (dma_submit_error(cookie)) { |
| 889 | dev_err(dma_chan->device->dev, |
| 890 | "Self-test submit error, disabling\n"); |
| 891 | err = -ENODEV; |
| 892 | goto free_resources; |
| 893 | } |
| 894 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 895 | mv_xor_issue_pending(dma_chan); |
| 896 | async_tx_ack(tx); |
| 897 | msleep(8); |
| 898 | |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 899 | if (mv_xor_status(dma_chan, cookie, NULL) != |
Vinod Koul | b3efb8f | 2013-10-16 20:51:04 +0530 | [diff] [blame] | 900 | DMA_COMPLETE) { |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 901 | dev_err(dma_chan->device->dev, |
| 902 | "Self-test xor timed out, disabling\n"); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 903 | err = -ENODEV; |
| 904 | goto free_resources; |
| 905 | } |
| 906 | |
Thomas Petazzoni | c35064c | 2012-11-15 13:01:59 +0100 | [diff] [blame] | 907 | dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma, |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 908 | PAGE_SIZE, DMA_FROM_DEVICE); |
| 909 | for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { |
| 910 | u32 *ptr = page_address(dest); |
| 911 | if (ptr[i] != cmp_word) { |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 912 | dev_err(dma_chan->device->dev, |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 913 | "Self-test xor failed compare, disabling. index %d, data %x, expected %x\n", |
| 914 | i, ptr[i], cmp_word); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 915 | err = -ENODEV; |
| 916 | goto free_resources; |
| 917 | } |
| 918 | } |
| 919 | |
| 920 | free_resources: |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 921 | dmaengine_unmap_put(unmap); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 922 | mv_xor_free_chan_resources(dma_chan); |
| 923 | out: |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 924 | src_idx = src_count; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 925 | while (src_idx--) |
| 926 | __free_page(xor_srcs[src_idx]); |
| 927 | __free_page(dest); |
| 928 | return err; |
| 929 | } |
| 930 | |
Andrew Lunn | 34c93c8 | 2012-11-18 11:44:56 +0100 | [diff] [blame] | 931 | /* This driver does not implement any of the optional DMA operations. */ |
| 932 | static int |
| 933 | mv_xor_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
| 934 | unsigned long arg) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 935 | { |
Andrew Lunn | 34c93c8 | 2012-11-18 11:44:56 +0100 | [diff] [blame] | 936 | return -ENOSYS; |
| 937 | } |
| 938 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 939 | static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 940 | { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 941 | struct dma_chan *chan, *_chan; |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 942 | struct device *dev = mv_chan->dmadev.dev; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 943 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 944 | dma_async_device_unregister(&mv_chan->dmadev); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 945 | |
Thomas Petazzoni | b503fa0 | 2012-11-15 15:55:30 +0100 | [diff] [blame] | 946 | dma_free_coherent(dev, MV_XOR_POOL_SIZE, |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 947 | mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); |
Lior Amsalem | 2284354 | 2014-08-27 10:52:55 -0300 | [diff] [blame] | 948 | dma_unmap_single(dev, mv_chan->dummy_src_addr, |
| 949 | MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE); |
| 950 | dma_unmap_single(dev, mv_chan->dummy_dst_addr, |
| 951 | MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 952 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 953 | list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels, |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 954 | device_node) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 955 | list_del(&chan->device_node); |
| 956 | } |
| 957 | |
Thomas Petazzoni | 88eb92c | 2012-11-15 16:11:18 +0100 | [diff] [blame] | 958 | free_irq(mv_chan->irq, mv_chan); |
| 959 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 960 | return 0; |
| 961 | } |
| 962 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 963 | static struct mv_xor_chan * |
Thomas Petazzoni | 297eedba | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 964 | mv_xor_channel_add(struct mv_xor_device *xordev, |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 965 | struct platform_device *pdev, |
Thomas Petazzoni | b503fa0 | 2012-11-15 15:55:30 +0100 | [diff] [blame] | 966 | int idx, dma_cap_mask_t cap_mask, int irq) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 967 | { |
| 968 | int ret = 0; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 969 | struct mv_xor_chan *mv_chan; |
| 970 | struct dma_device *dma_dev; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 971 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 972 | mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL); |
Sachin Kamat | a577659 | 2013-09-02 13:54:20 +0530 | [diff] [blame] | 973 | if (!mv_chan) |
| 974 | return ERR_PTR(-ENOMEM); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 975 | |
Thomas Petazzoni | 9aedbdb | 2012-11-15 15:36:37 +0100 | [diff] [blame] | 976 | mv_chan->idx = idx; |
Thomas Petazzoni | 88eb92c | 2012-11-15 16:11:18 +0100 | [diff] [blame] | 977 | mv_chan->irq = irq; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 978 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 979 | dma_dev = &mv_chan->dmadev; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 980 | |
Lior Amsalem | 2284354 | 2014-08-27 10:52:55 -0300 | [diff] [blame] | 981 | /* |
| 982 | * These source and destination dummy buffers are used to implement |
| 983 | * a DMA_INTERRUPT operation as a minimum-sized XOR operation. |
| 984 | * Hence, we only need to map the buffers at initialization-time. |
| 985 | */ |
| 986 | mv_chan->dummy_src_addr = dma_map_single(dma_dev->dev, |
| 987 | mv_chan->dummy_src, MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE); |
| 988 | mv_chan->dummy_dst_addr = dma_map_single(dma_dev->dev, |
| 989 | mv_chan->dummy_dst, MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE); |
| 990 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 991 | /* allocate coherent memory for hardware descriptors |
| 992 | * note: writecombine gives slightly better performance, but |
| 993 | * requires that we explicitly flush the writes |
| 994 | */ |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 995 | mv_chan->dma_desc_pool_virt = |
Thomas Petazzoni | b503fa0 | 2012-11-15 15:55:30 +0100 | [diff] [blame] | 996 | dma_alloc_writecombine(&pdev->dev, MV_XOR_POOL_SIZE, |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 997 | &mv_chan->dma_desc_pool, GFP_KERNEL); |
| 998 | if (!mv_chan->dma_desc_pool_virt) |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 999 | return ERR_PTR(-ENOMEM); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1000 | |
| 1001 | /* discover transaction capabilites from the platform data */ |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 1002 | dma_dev->cap_mask = cap_mask; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1003 | |
| 1004 | INIT_LIST_HEAD(&dma_dev->channels); |
| 1005 | |
| 1006 | /* set base routines */ |
| 1007 | dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources; |
| 1008 | dma_dev->device_free_chan_resources = mv_xor_free_chan_resources; |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 1009 | dma_dev->device_tx_status = mv_xor_status; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1010 | dma_dev->device_issue_pending = mv_xor_issue_pending; |
Andrew Lunn | 34c93c8 | 2012-11-18 11:44:56 +0100 | [diff] [blame] | 1011 | dma_dev->device_control = mv_xor_control; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1012 | dma_dev->dev = &pdev->dev; |
| 1013 | |
| 1014 | /* set prep routines based on capability */ |
Lior Amsalem | 2284354 | 2014-08-27 10:52:55 -0300 | [diff] [blame] | 1015 | if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask)) |
| 1016 | dma_dev->device_prep_dma_interrupt = mv_xor_prep_dma_interrupt; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1017 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) |
| 1018 | dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1019 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { |
Joe Perches | c019894 | 2009-06-28 09:26:21 -0700 | [diff] [blame] | 1020 | dma_dev->max_xor = 8; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1021 | dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor; |
| 1022 | } |
| 1023 | |
Thomas Petazzoni | 297eedba | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1024 | mv_chan->mmr_base = xordev->xor_base; |
Ezequiel Garcia | 82a1402 | 2013-10-30 12:01:43 -0300 | [diff] [blame] | 1025 | mv_chan->mmr_high_base = xordev->xor_high_base; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1026 | tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long) |
| 1027 | mv_chan); |
| 1028 | |
| 1029 | /* clear errors before enabling interrupts */ |
| 1030 | mv_xor_device_clear_err_status(mv_chan); |
| 1031 | |
Thomas Petazzoni | 2d0a074 | 2012-11-22 18:19:09 +0100 | [diff] [blame] | 1032 | ret = request_irq(mv_chan->irq, mv_xor_interrupt_handler, |
| 1033 | 0, dev_name(&pdev->dev), mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1034 | if (ret) |
| 1035 | goto err_free_dma; |
| 1036 | |
| 1037 | mv_chan_unmask_interrupts(mv_chan); |
| 1038 | |
Lior Amsalem | 3e4f52e | 2014-08-27 10:52:50 -0300 | [diff] [blame] | 1039 | mv_set_mode(mv_chan, DMA_XOR); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1040 | |
| 1041 | spin_lock_init(&mv_chan->lock); |
| 1042 | INIT_LIST_HEAD(&mv_chan->chain); |
| 1043 | INIT_LIST_HEAD(&mv_chan->completed_slots); |
| 1044 | INIT_LIST_HEAD(&mv_chan->all_slots); |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 1045 | mv_chan->dmachan.device = dma_dev; |
| 1046 | dma_cookie_init(&mv_chan->dmachan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1047 | |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 1048 | list_add_tail(&mv_chan->dmachan.device_node, &dma_dev->channels); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1049 | |
| 1050 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { |
Thomas Petazzoni | 275cc0c | 2012-11-15 15:09:42 +0100 | [diff] [blame] | 1051 | ret = mv_xor_memcpy_self_test(mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1052 | dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret); |
| 1053 | if (ret) |
Thomas Petazzoni | 2d0a074 | 2012-11-22 18:19:09 +0100 | [diff] [blame] | 1054 | goto err_free_irq; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1055 | } |
| 1056 | |
| 1057 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { |
Thomas Petazzoni | 275cc0c | 2012-11-15 15:09:42 +0100 | [diff] [blame] | 1058 | ret = mv_xor_xor_self_test(mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1059 | dev_dbg(&pdev->dev, "xor self test returned %d\n", ret); |
| 1060 | if (ret) |
Thomas Petazzoni | 2d0a074 | 2012-11-22 18:19:09 +0100 | [diff] [blame] | 1061 | goto err_free_irq; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1062 | } |
| 1063 | |
Bartlomiej Zolnierkiewicz | 48a9db4 | 2013-07-03 15:05:06 -0700 | [diff] [blame] | 1064 | dev_info(&pdev->dev, "Marvell XOR: ( %s%s%s)\n", |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 1065 | dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "", |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 1066 | dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "", |
| 1067 | dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : ""); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1068 | |
| 1069 | dma_async_device_register(dma_dev); |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 1070 | return mv_chan; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1071 | |
Thomas Petazzoni | 2d0a074 | 2012-11-22 18:19:09 +0100 | [diff] [blame] | 1072 | err_free_irq: |
| 1073 | free_irq(mv_chan->irq, mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1074 | err_free_dma: |
Thomas Petazzoni | b503fa0 | 2012-11-15 15:55:30 +0100 | [diff] [blame] | 1075 | dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE, |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 1076 | mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 1077 | return ERR_PTR(ret); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1078 | } |
| 1079 | |
| 1080 | static void |
Thomas Petazzoni | 297eedba | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1081 | mv_xor_conf_mbus_windows(struct mv_xor_device *xordev, |
Andrew Lunn | 63a9332 | 2011-12-07 21:48:07 +0100 | [diff] [blame] | 1082 | const struct mbus_dram_target_info *dram) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1083 | { |
Ezequiel Garcia | 82a1402 | 2013-10-30 12:01:43 -0300 | [diff] [blame] | 1084 | void __iomem *base = xordev->xor_high_base; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1085 | u32 win_enable = 0; |
| 1086 | int i; |
| 1087 | |
| 1088 | for (i = 0; i < 8; i++) { |
| 1089 | writel(0, base + WINDOW_BASE(i)); |
| 1090 | writel(0, base + WINDOW_SIZE(i)); |
| 1091 | if (i < 4) |
| 1092 | writel(0, base + WINDOW_REMAP_HIGH(i)); |
| 1093 | } |
| 1094 | |
| 1095 | for (i = 0; i < dram->num_cs; i++) { |
Andrew Lunn | 63a9332 | 2011-12-07 21:48:07 +0100 | [diff] [blame] | 1096 | const struct mbus_dram_window *cs = dram->cs + i; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1097 | |
| 1098 | writel((cs->base & 0xffff0000) | |
| 1099 | (cs->mbus_attr << 8) | |
| 1100 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); |
| 1101 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); |
| 1102 | |
| 1103 | win_enable |= (1 << i); |
| 1104 | win_enable |= 3 << (16 + (2 * i)); |
| 1105 | } |
| 1106 | |
| 1107 | writel(win_enable, base + WINDOW_BAR_ENABLE(0)); |
| 1108 | writel(win_enable, base + WINDOW_BAR_ENABLE(1)); |
Thomas Petazzoni | c4b4b73 | 2012-11-22 18:16:37 +0100 | [diff] [blame] | 1109 | writel(0, base + WINDOW_OVERRIDE_CTRL(0)); |
| 1110 | writel(0, base + WINDOW_OVERRIDE_CTRL(1)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1111 | } |
| 1112 | |
Linus Torvalds | c271433 | 2012-12-14 14:54:26 -0800 | [diff] [blame] | 1113 | static int mv_xor_probe(struct platform_device *pdev) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1114 | { |
Andrew Lunn | 63a9332 | 2011-12-07 21:48:07 +0100 | [diff] [blame] | 1115 | const struct mbus_dram_target_info *dram; |
Thomas Petazzoni | 297eedba | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1116 | struct mv_xor_device *xordev; |
Jingoo Han | d4adcc0 | 2013-07-30 17:09:11 +0900 | [diff] [blame] | 1117 | struct mv_xor_platform_data *pdata = dev_get_platdata(&pdev->dev); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1118 | struct resource *res; |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1119 | int i, ret; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1120 | |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 1121 | dev_notice(&pdev->dev, "Marvell shared XOR driver\n"); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1122 | |
Thomas Petazzoni | 297eedba | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1123 | xordev = devm_kzalloc(&pdev->dev, sizeof(*xordev), GFP_KERNEL); |
| 1124 | if (!xordev) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1125 | return -ENOMEM; |
| 1126 | |
| 1127 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1128 | if (!res) |
| 1129 | return -ENODEV; |
| 1130 | |
Thomas Petazzoni | 297eedba | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1131 | xordev->xor_base = devm_ioremap(&pdev->dev, res->start, |
| 1132 | resource_size(res)); |
| 1133 | if (!xordev->xor_base) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1134 | return -EBUSY; |
| 1135 | |
| 1136 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
| 1137 | if (!res) |
| 1138 | return -ENODEV; |
| 1139 | |
Thomas Petazzoni | 297eedba | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1140 | xordev->xor_high_base = devm_ioremap(&pdev->dev, res->start, |
| 1141 | resource_size(res)); |
| 1142 | if (!xordev->xor_high_base) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1143 | return -EBUSY; |
| 1144 | |
Thomas Petazzoni | 297eedba | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1145 | platform_set_drvdata(pdev, xordev); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1146 | |
| 1147 | /* |
| 1148 | * (Re-)program MBUS remapping windows if we are asked to. |
| 1149 | */ |
Andrew Lunn | 63a9332 | 2011-12-07 21:48:07 +0100 | [diff] [blame] | 1150 | dram = mv_mbus_dram_info(); |
| 1151 | if (dram) |
Thomas Petazzoni | 297eedba | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1152 | mv_xor_conf_mbus_windows(xordev, dram); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1153 | |
Andrew Lunn | c510182 | 2012-02-19 13:30:26 +0100 | [diff] [blame] | 1154 | /* Not all platforms can gate the clock, so it is not |
| 1155 | * an error if the clock does not exists. |
| 1156 | */ |
Thomas Petazzoni | 297eedba | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1157 | xordev->clk = clk_get(&pdev->dev, NULL); |
| 1158 | if (!IS_ERR(xordev->clk)) |
| 1159 | clk_prepare_enable(xordev->clk); |
Andrew Lunn | c510182 | 2012-02-19 13:30:26 +0100 | [diff] [blame] | 1160 | |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1161 | if (pdev->dev.of_node) { |
| 1162 | struct device_node *np; |
| 1163 | int i = 0; |
| 1164 | |
| 1165 | for_each_child_of_node(pdev->dev.of_node, np) { |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1166 | struct mv_xor_chan *chan; |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1167 | dma_cap_mask_t cap_mask; |
| 1168 | int irq; |
| 1169 | |
| 1170 | dma_cap_zero(cap_mask); |
| 1171 | if (of_property_read_bool(np, "dmacap,memcpy")) |
| 1172 | dma_cap_set(DMA_MEMCPY, cap_mask); |
| 1173 | if (of_property_read_bool(np, "dmacap,xor")) |
| 1174 | dma_cap_set(DMA_XOR, cap_mask); |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1175 | if (of_property_read_bool(np, "dmacap,interrupt")) |
| 1176 | dma_cap_set(DMA_INTERRUPT, cap_mask); |
| 1177 | |
| 1178 | irq = irq_of_parse_and_map(np, 0); |
Thomas Petazzoni | f8eb9e7 | 2012-11-22 18:22:12 +0100 | [diff] [blame] | 1179 | if (!irq) { |
| 1180 | ret = -ENODEV; |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1181 | goto err_channel_add; |
| 1182 | } |
| 1183 | |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1184 | chan = mv_xor_channel_add(xordev, pdev, i, |
| 1185 | cap_mask, irq); |
| 1186 | if (IS_ERR(chan)) { |
| 1187 | ret = PTR_ERR(chan); |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1188 | irq_dispose_mapping(irq); |
| 1189 | goto err_channel_add; |
| 1190 | } |
| 1191 | |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1192 | xordev->channels[i] = chan; |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1193 | i++; |
| 1194 | } |
| 1195 | } else if (pdata && pdata->channels) { |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1196 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) { |
Thomas Petazzoni | e39f6ec | 2012-10-30 11:56:26 +0100 | [diff] [blame] | 1197 | struct mv_xor_channel_data *cd; |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1198 | struct mv_xor_chan *chan; |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1199 | int irq; |
| 1200 | |
| 1201 | cd = &pdata->channels[i]; |
| 1202 | if (!cd) { |
| 1203 | ret = -ENODEV; |
| 1204 | goto err_channel_add; |
| 1205 | } |
| 1206 | |
| 1207 | irq = platform_get_irq(pdev, i); |
| 1208 | if (irq < 0) { |
| 1209 | ret = irq; |
| 1210 | goto err_channel_add; |
| 1211 | } |
| 1212 | |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1213 | chan = mv_xor_channel_add(xordev, pdev, i, |
| 1214 | cd->cap_mask, irq); |
| 1215 | if (IS_ERR(chan)) { |
| 1216 | ret = PTR_ERR(chan); |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1217 | goto err_channel_add; |
| 1218 | } |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1219 | |
| 1220 | xordev->channels[i] = chan; |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1221 | } |
| 1222 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1223 | |
| 1224 | return 0; |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1225 | |
| 1226 | err_channel_add: |
| 1227 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1228 | if (xordev->channels[i]) { |
Thomas Petazzoni | ab6e439 | 2013-01-06 11:10:43 +0100 | [diff] [blame] | 1229 | mv_xor_channel_remove(xordev->channels[i]); |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1230 | if (pdev->dev.of_node) |
| 1231 | irq_dispose_mapping(xordev->channels[i]->irq); |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1232 | } |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1233 | |
Thomas Petazzoni | dab9206 | 2013-01-06 11:10:44 +0100 | [diff] [blame] | 1234 | if (!IS_ERR(xordev->clk)) { |
| 1235 | clk_disable_unprepare(xordev->clk); |
| 1236 | clk_put(xordev->clk); |
| 1237 | } |
| 1238 | |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1239 | return ret; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1240 | } |
| 1241 | |
Linus Torvalds | c271433 | 2012-12-14 14:54:26 -0800 | [diff] [blame] | 1242 | static int mv_xor_remove(struct platform_device *pdev) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1243 | { |
Thomas Petazzoni | 297eedba | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1244 | struct mv_xor_device *xordev = platform_get_drvdata(pdev); |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1245 | int i; |
Andrew Lunn | c510182 | 2012-02-19 13:30:26 +0100 | [diff] [blame] | 1246 | |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1247 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) { |
Thomas Petazzoni | 297eedba | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1248 | if (xordev->channels[i]) |
| 1249 | mv_xor_channel_remove(xordev->channels[i]); |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1250 | } |
Andrew Lunn | c510182 | 2012-02-19 13:30:26 +0100 | [diff] [blame] | 1251 | |
Thomas Petazzoni | 297eedba | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1252 | if (!IS_ERR(xordev->clk)) { |
| 1253 | clk_disable_unprepare(xordev->clk); |
| 1254 | clk_put(xordev->clk); |
Andrew Lunn | c510182 | 2012-02-19 13:30:26 +0100 | [diff] [blame] | 1255 | } |
| 1256 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1257 | return 0; |
| 1258 | } |
| 1259 | |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1260 | #ifdef CONFIG_OF |
Linus Torvalds | c271433 | 2012-12-14 14:54:26 -0800 | [diff] [blame] | 1261 | static struct of_device_id mv_xor_dt_ids[] = { |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1262 | { .compatible = "marvell,orion-xor", }, |
| 1263 | {}, |
| 1264 | }; |
| 1265 | MODULE_DEVICE_TABLE(of, mv_xor_dt_ids); |
| 1266 | #endif |
| 1267 | |
Thomas Petazzoni | 6197165 | 2012-10-30 12:05:40 +0100 | [diff] [blame] | 1268 | static struct platform_driver mv_xor_driver = { |
| 1269 | .probe = mv_xor_probe, |
Linus Torvalds | c271433 | 2012-12-14 14:54:26 -0800 | [diff] [blame] | 1270 | .remove = mv_xor_remove, |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1271 | .driver = { |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1272 | .owner = THIS_MODULE, |
| 1273 | .name = MV_XOR_NAME, |
| 1274 | .of_match_table = of_match_ptr(mv_xor_dt_ids), |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1275 | }, |
| 1276 | }; |
| 1277 | |
| 1278 | |
| 1279 | static int __init mv_xor_init(void) |
| 1280 | { |
Thomas Petazzoni | 6197165 | 2012-10-30 12:05:40 +0100 | [diff] [blame] | 1281 | return platform_driver_register(&mv_xor_driver); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1282 | } |
| 1283 | module_init(mv_xor_init); |
| 1284 | |
| 1285 | /* it's currently unsafe to unload this module */ |
| 1286 | #if 0 |
| 1287 | static void __exit mv_xor_exit(void) |
| 1288 | { |
| 1289 | platform_driver_unregister(&mv_xor_driver); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1290 | return; |
| 1291 | } |
| 1292 | |
| 1293 | module_exit(mv_xor_exit); |
| 1294 | #endif |
| 1295 | |
| 1296 | MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>"); |
| 1297 | MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine"); |
| 1298 | MODULE_LICENSE("GPL"); |