Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; either version 2 of the License, or |
| 8 | * (at your option) any later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along |
| 16 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | * |
| 19 | * |
| 20 | * File: rf.c |
| 21 | * |
| 22 | * Purpose: rf function code |
| 23 | * |
| 24 | * Author: Jerry Chen |
| 25 | * |
| 26 | * Date: Feb. 19, 2004 |
| 27 | * |
| 28 | * Functions: |
| 29 | * IFRFbWriteEmbeded - Embeded write RF register via MAC |
| 30 | * |
| 31 | * Revision History: |
| 32 | * |
| 33 | */ |
| 34 | #if !defined(__MAC_H__) |
| 35 | #include "mac.h" |
| 36 | #endif |
| 37 | #if !defined(__SROM_H__) |
| 38 | #include "srom.h" |
| 39 | #endif |
| 40 | #if !defined(__TBIT_H__) |
| 41 | #include "tbit.h" |
| 42 | #endif |
| 43 | #if !defined(__RF_H__) |
| 44 | #include "rf.h" |
| 45 | #endif |
| 46 | #if !defined(__BASEBAND_H__) |
| 47 | #include "baseband.h" |
| 48 | #endif |
| 49 | |
| 50 | /*--------------------- Static Definitions -------------------------*/ |
| 51 | |
| 52 | //static int msglevel =MSG_LEVEL_INFO; |
| 53 | |
| 54 | #define BY_RF2959_REG_LEN 23 //24bits |
| 55 | #define CB_RF2959_INIT_SEQ 15 |
| 56 | #define SWITCH_CHANNEL_DELAY_RF2959 200 //us |
| 57 | #define RF2959_PWR_IDX_LEN 32 |
| 58 | |
| 59 | #define BY_MA2825_REG_LEN 23 //24bit |
| 60 | #define CB_MA2825_INIT_SEQ 13 |
| 61 | #define SWITCH_CHANNEL_DELAY_MA2825 200 //us |
| 62 | #define MA2825_PWR_IDX_LEN 31 |
| 63 | |
| 64 | #define BY_AL2230_REG_LEN 23 //24bit |
| 65 | #define CB_AL2230_INIT_SEQ 15 |
| 66 | #define SWITCH_CHANNEL_DELAY_AL2230 200 //us |
| 67 | #define AL2230_PWR_IDX_LEN 64 |
| 68 | |
| 69 | |
| 70 | #define BY_UW2451_REG_LEN 23 |
| 71 | #define CB_UW2451_INIT_SEQ 6 |
| 72 | #define SWITCH_CHANNEL_DELAY_UW2451 200 //us |
| 73 | #define UW2451_PWR_IDX_LEN 25 |
| 74 | |
| 75 | //{{ RobertYu: 20041118 |
| 76 | #define BY_MA2829_REG_LEN 23 //24bit |
| 77 | #define CB_MA2829_INIT_SEQ 13 |
| 78 | #define SWITCH_CHANNEL_DELAY_MA2829 200 //us |
| 79 | #define MA2829_PWR_IDX_LEN 64 |
| 80 | //}} RobertYu |
| 81 | |
| 82 | //{{ RobertYu:20050103 |
| 83 | #define BY_AL7230_REG_LEN 23 //24bit |
| 84 | #define CB_AL7230_INIT_SEQ 16 |
| 85 | #define SWITCH_CHANNEL_DELAY_AL7230 200 //us |
| 86 | #define AL7230_PWR_IDX_LEN 64 |
| 87 | //}} RobertYu |
| 88 | |
| 89 | //{{ RobertYu: 20041210 |
| 90 | #define BY_UW2452_REG_LEN 23 |
| 91 | #define CB_UW2452_INIT_SEQ 5 //RoberYu:20050113, Rev0.2 Programming Guide(remove R3, so 6-->5) |
| 92 | #define SWITCH_CHANNEL_DELAY_UW2452 100 //us |
| 93 | #define UW2452_PWR_IDX_LEN 64 |
| 94 | //}} RobertYu |
| 95 | |
| 96 | #define BY_VT3226_REG_LEN 23 |
| 97 | #define CB_VT3226_INIT_SEQ 12 |
| 98 | #define SWITCH_CHANNEL_DELAY_VT3226 200 //us |
| 99 | #define VT3226_PWR_IDX_LEN 16 |
| 100 | |
| 101 | /*--------------------- Static Classes ----------------------------*/ |
| 102 | |
| 103 | /*--------------------- Static Variables --------------------------*/ |
| 104 | |
| 105 | |
| 106 | |
| 107 | const DWORD dwAL2230InitTable[CB_AL2230_INIT_SEQ] = { |
| 108 | 0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // |
| 109 | 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // |
| 110 | 0x01A00200+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // |
| 111 | 0x00FFF300+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // |
| 112 | 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // |
| 113 | 0x0F4DC500+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // |
| 114 | 0x0805B600+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // |
| 115 | 0x0146C700+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // |
| 116 | 0x00068800+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // |
| 117 | 0x0403B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // |
| 118 | 0x00DBBA00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // |
| 119 | 0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // |
| 120 | 0x0BDFFC00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 121 | 0x00000D00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 122 | 0x00580F00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW |
| 123 | }; |
| 124 | |
| 125 | const DWORD dwAL2230ChannelTable0[CB_MAX_CHANNEL] = { |
| 126 | 0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz |
| 127 | 0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz |
| 128 | 0x03E79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz |
| 129 | 0x03E79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz |
| 130 | 0x03F7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz |
| 131 | 0x03F7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz |
| 132 | 0x03E7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz |
| 133 | 0x03E7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz |
| 134 | 0x03F7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz |
| 135 | 0x03F7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz |
| 136 | 0x03E7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz |
| 137 | 0x03E7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz |
| 138 | 0x03F7C000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz |
| 139 | 0x03E7C000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW // channel = 14, Tf = 2412M |
| 140 | }; |
| 141 | |
| 142 | const DWORD dwAL2230ChannelTable1[CB_MAX_CHANNEL] = { |
| 143 | 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz |
| 144 | 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz |
| 145 | 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz |
| 146 | 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz |
| 147 | 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz |
| 148 | 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz |
| 149 | 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz |
| 150 | 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz |
| 151 | 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz |
| 152 | 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz |
| 153 | 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz |
| 154 | 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz |
| 155 | 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz |
| 156 | 0x06666100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW // channel = 14, Tf = 2412M |
| 157 | }; |
| 158 | |
| 159 | DWORD dwAL2230PowerTable[AL2230_PWR_IDX_LEN] = { |
| 160 | 0x04040900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 161 | 0x04041900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 162 | 0x04042900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 163 | 0x04043900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 164 | 0x04044900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 165 | 0x04045900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 166 | 0x04046900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 167 | 0x04047900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 168 | 0x04048900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 169 | 0x04049900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 170 | 0x0404A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 171 | 0x0404B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 172 | 0x0404C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 173 | 0x0404D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 174 | 0x0404E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 175 | 0x0404F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 176 | 0x04050900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 177 | 0x04051900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 178 | 0x04052900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 179 | 0x04053900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 180 | 0x04054900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 181 | 0x04055900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 182 | 0x04056900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 183 | 0x04057900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 184 | 0x04058900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 185 | 0x04059900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 186 | 0x0405A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 187 | 0x0405B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 188 | 0x0405C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 189 | 0x0405D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 190 | 0x0405E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 191 | 0x0405F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 192 | 0x04060900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 193 | 0x04061900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 194 | 0x04062900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 195 | 0x04063900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 196 | 0x04064900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 197 | 0x04065900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 198 | 0x04066900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 199 | 0x04067900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 200 | 0x04068900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 201 | 0x04069900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 202 | 0x0406A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 203 | 0x0406B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 204 | 0x0406C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 205 | 0x0406D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 206 | 0x0406E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 207 | 0x0406F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 208 | 0x04070900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 209 | 0x04071900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 210 | 0x04072900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 211 | 0x04073900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 212 | 0x04074900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 213 | 0x04075900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 214 | 0x04076900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 215 | 0x04077900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 216 | 0x04078900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 217 | 0x04079900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 218 | 0x0407A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 219 | 0x0407B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 220 | 0x0407C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 221 | 0x0407D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 222 | 0x0407E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, |
| 223 | 0x0407F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW |
| 224 | }; |
| 225 | |
| 226 | //{{ RobertYu:20050104 |
| 227 | // 40MHz reference frequency |
| 228 | // Need to Pull PLLON(PE3) low when writing channel registers through 3-wire. |
| 229 | const DWORD dwAL7230InitTable[CB_AL7230_INIT_SEQ] = { |
| 230 | 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel1 // Need modify for 11a |
| 231 | 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel1 // Need modify for 11a |
| 232 | 0x841FF200+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 451FE2 |
| 233 | 0x3FDFA300+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 5FDFA3 |
| 234 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // 11b/g // Need modify for 11a |
| 235 | //0x802B4500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 8D1B45 |
| 236 | // RoberYu:20050113, Rev0.47 Regsiter Setting Guide |
| 237 | 0x802B5500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 8D1B55 |
| 238 | 0x56AF3600+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, |
| 239 | 0xCE020700+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 860207 |
| 240 | 0x6EBC0800+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, |
| 241 | 0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, |
| 242 | 0xE0000A00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: E0600A |
| 243 | 0x08031B00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10) |
| 244 | //0x00093C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 00143C |
| 245 | // RoberYu:20050113, Rev0.47 Regsiter Setting Guide |
| 246 | 0x000A3C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 00143C |
| 247 | 0xFFFFFD00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, |
| 248 | 0x00000E00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, |
| 249 | 0x1ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // Need modify for 11a: 12BACF |
| 250 | }; |
| 251 | |
| 252 | const DWORD dwAL7230InitTableAMode[CB_AL7230_INIT_SEQ] = { |
| 253 | 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel184 // Need modify for 11b/g |
| 254 | 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel184 // Need modify for 11b/g |
| 255 | 0x451FE200+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g |
| 256 | 0x5FDFA300+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g |
| 257 | 0x67F78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // 11a // Need modify for 11b/g |
| 258 | 0x853F5500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g, RoberYu:20050113 |
| 259 | 0x56AF3600+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, |
| 260 | 0xCE020700+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g |
| 261 | 0x6EBC0800+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, |
| 262 | 0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, |
| 263 | 0xE0600A00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g |
| 264 | 0x08031B00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10) |
| 265 | 0x00147C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g |
| 266 | 0xFFFFFD00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, |
| 267 | 0x00000E00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, |
| 268 | 0x12BACF00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // Need modify for 11b/g |
| 269 | }; |
| 270 | |
| 271 | |
| 272 | const DWORD dwAL7230ChannelTable0[CB_MAX_CHANNEL] = { |
| 273 | 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz |
| 274 | 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz |
| 275 | 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz |
| 276 | 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz |
| 277 | 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz |
| 278 | 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz |
| 279 | 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz |
| 280 | 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz //RobertYu: 20050218, update for APNode 0.49 |
| 281 | 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz //RobertYu: 20050218, update for APNode 0.49 |
| 282 | 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz //RobertYu: 20050218, update for APNode 0.49 |
| 283 | 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz //RobertYu: 20050218, update for APNode 0.49 |
| 284 | 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz //RobertYu: 20050218, update for APNode 0.49 |
| 285 | 0x0037C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz //RobertYu: 20050218, update for APNode 0.49 |
| 286 | 0x0037C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 14, Tf = 2484MHz |
| 287 | |
| 288 | // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22) |
| 289 | 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 183, Tf = 4915MHz (15) |
| 290 | 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 184, Tf = 4920MHz (16) |
| 291 | 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 185, Tf = 4925MHz (17) |
| 292 | 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 187, Tf = 4935MHz (18) |
| 293 | 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 188, Tf = 4940MHz (19) |
| 294 | 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 189, Tf = 4945MHz (20) |
| 295 | 0x0FF53000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 192, Tf = 4960MHz (21) |
| 296 | 0x0FF53000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 196, Tf = 4980MHz (22) |
| 297 | |
| 298 | // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64, |
| 299 | // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56) |
| 300 | |
| 301 | 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 5035MHz (23) |
| 302 | 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 5040MHz (24) |
| 303 | 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 5045MHz (25) |
| 304 | 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 5055MHz (26) |
| 305 | 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 5060MHz (27) |
| 306 | 0x0FF55000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 16, Tf = 5080MHz (28) |
| 307 | 0x0FF56000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 34, Tf = 5170MHz (29) |
| 308 | 0x0FF56000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 36, Tf = 5180MHz (30) |
| 309 | 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 38, Tf = 5190MHz (31) //RobertYu: 20050218, update for APNode 0.49 |
| 310 | 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 40, Tf = 5200MHz (32) |
| 311 | 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 42, Tf = 5210MHz (33) |
| 312 | 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 44, Tf = 5220MHz (34) |
| 313 | 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 46, Tf = 5230MHz (35) |
| 314 | 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 48, Tf = 5240MHz (36) |
| 315 | 0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 52, Tf = 5260MHz (37) |
| 316 | 0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 56, Tf = 5280MHz (38) |
| 317 | 0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 60, Tf = 5300MHz (39) |
| 318 | 0x0FF59000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 64, Tf = 5320MHz (40) |
| 319 | |
| 320 | 0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 100, Tf = 5500MHz (41) |
| 321 | 0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 104, Tf = 5520MHz (42) |
| 322 | 0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 108, Tf = 5540MHz (43) |
| 323 | 0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 112, Tf = 5560MHz (44) |
| 324 | 0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 116, Tf = 5580MHz (45) |
| 325 | 0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 120, Tf = 5600MHz (46) |
| 326 | 0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 124, Tf = 5620MHz (47) |
| 327 | 0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 128, Tf = 5640MHz (48) |
| 328 | 0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 132, Tf = 5660MHz (49) |
| 329 | 0x0FF5F000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 136, Tf = 5680MHz (50) |
| 330 | 0x0FF5F000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 140, Tf = 5700MHz (51) |
| 331 | 0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 149, Tf = 5745MHz (52) |
| 332 | 0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 153, Tf = 5765MHz (53) |
| 333 | 0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 157, Tf = 5785MHz (54) |
| 334 | 0x0FF61000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 161, Tf = 5805MHz (55) |
| 335 | 0x0FF61000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // channel = 165, Tf = 5825MHz (56) |
| 336 | }; |
| 337 | |
| 338 | const DWORD dwAL7230ChannelTable1[CB_MAX_CHANNEL] = { |
| 339 | 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz |
| 340 | 0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz |
| 341 | 0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz |
| 342 | 0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz |
| 343 | 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz |
| 344 | 0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz |
| 345 | 0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz |
| 346 | 0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz |
| 347 | 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz |
| 348 | 0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz |
| 349 | 0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz |
| 350 | 0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz |
| 351 | 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz |
| 352 | 0x06666100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 14, Tf = 2484MHz |
| 353 | |
| 354 | // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22) |
| 355 | 0x1D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 183, Tf = 4915MHz (15) |
| 356 | 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 184, Tf = 4920MHz (16) |
| 357 | 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 185, Tf = 4925MHz (17) |
| 358 | 0x08000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 187, Tf = 4935MHz (18) |
| 359 | 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 188, Tf = 4940MHz (19) |
| 360 | 0x0D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 189, Tf = 4945MHz (20) |
| 361 | 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 192, Tf = 4960MHz (21) |
| 362 | 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 196, Tf = 4980MHz (22) |
| 363 | |
| 364 | // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64, |
| 365 | // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56) |
| 366 | 0x1D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 5035MHz (23) |
| 367 | 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 5040MHz (24) |
| 368 | 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 5045MHz (25) |
| 369 | 0x08000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 5055MHz (26) |
| 370 | 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 5060MHz (27) |
| 371 | 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 16, Tf = 5080MHz (28) |
| 372 | 0x05555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 34, Tf = 5170MHz (29) |
| 373 | 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 36, Tf = 5180MHz (30) |
| 374 | 0x10000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 38, Tf = 5190MHz (31) |
| 375 | 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 40, Tf = 5200MHz (32) |
| 376 | 0x1AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 42, Tf = 5210MHz (33) |
| 377 | 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 44, Tf = 5220MHz (34) |
| 378 | 0x05555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 46, Tf = 5230MHz (35) |
| 379 | 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 48, Tf = 5240MHz (36) |
| 380 | 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 52, Tf = 5260MHz (37) |
| 381 | 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 56, Tf = 5280MHz (38) |
| 382 | 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 60, Tf = 5300MHz (39) |
| 383 | 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 64, Tf = 5320MHz (40) |
| 384 | 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 100, Tf = 5500MHz (41) |
| 385 | 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 104, Tf = 5520MHz (42) |
| 386 | 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 108, Tf = 5540MHz (43) |
| 387 | 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 112, Tf = 5560MHz (44) |
| 388 | 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 116, Tf = 5580MHz (45) |
| 389 | 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 120, Tf = 5600MHz (46) |
| 390 | 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 124, Tf = 5620MHz (47) |
| 391 | 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 128, Tf = 5640MHz (48) |
| 392 | 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 132, Tf = 5660MHz (49) |
| 393 | 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 136, Tf = 5680MHz (50) |
| 394 | 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 140, Tf = 5700MHz (51) |
| 395 | 0x18000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 149, Tf = 5745MHz (52) |
| 396 | 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 153, Tf = 5765MHz (53) |
| 397 | 0x0D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 157, Tf = 5785MHz (54) |
| 398 | 0x18000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 161, Tf = 5805MHz (55) |
| 399 | 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // channel = 165, Tf = 5825MHz (56) |
| 400 | }; |
| 401 | |
| 402 | const DWORD dwAL7230ChannelTable2[CB_MAX_CHANNEL] = { |
| 403 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz |
| 404 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz |
| 405 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz |
| 406 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz |
| 407 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz |
| 408 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz |
| 409 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz |
| 410 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz |
| 411 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz |
| 412 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz |
| 413 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz |
| 414 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz |
| 415 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz |
| 416 | 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 14, Tf = 2484MHz |
| 417 | |
| 418 | // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22) |
| 419 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 183, Tf = 4915MHz (15) |
| 420 | 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 184, Tf = 4920MHz (16) |
| 421 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 185, Tf = 4925MHz (17) |
| 422 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 187, Tf = 4935MHz (18) |
| 423 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 188, Tf = 4940MHz (19) |
| 424 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 189, Tf = 4945MHz (20) |
| 425 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 192, Tf = 4960MHz (21) |
| 426 | 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 196, Tf = 4980MHz (22) |
| 427 | |
| 428 | // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64, |
| 429 | // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56) |
| 430 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 5035MHz (23) |
| 431 | 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 5040MHz (24) |
| 432 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 5045MHz (25) |
| 433 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 5055MHz (26) |
| 434 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 5060MHz (27) |
| 435 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 16, Tf = 5080MHz (28) |
| 436 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 34, Tf = 5170MHz (29) |
| 437 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 36, Tf = 5180MHz (30) |
| 438 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 38, Tf = 5190MHz (31) |
| 439 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 40, Tf = 5200MHz (32) |
| 440 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 42, Tf = 5210MHz (33) |
| 441 | 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 44, Tf = 5220MHz (34) |
| 442 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 46, Tf = 5230MHz (35) |
| 443 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 48, Tf = 5240MHz (36) |
| 444 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 52, Tf = 5260MHz (37) |
| 445 | 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 56, Tf = 5280MHz (38) |
| 446 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 60, Tf = 5300MHz (39) |
| 447 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 64, Tf = 5320MHz (40) |
| 448 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 100, Tf = 5500MHz (41) |
| 449 | 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 104, Tf = 5520MHz (42) |
| 450 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 108, Tf = 5540MHz (43) |
| 451 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 112, Tf = 5560MHz (44) |
| 452 | 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 116, Tf = 5580MHz (45) |
| 453 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 120, Tf = 5600MHz (46) |
| 454 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 124, Tf = 5620MHz (47) |
| 455 | 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 128, Tf = 5640MHz (48) |
| 456 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 132, Tf = 5660MHz (49) |
| 457 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 136, Tf = 5680MHz (50) |
| 458 | 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 140, Tf = 5700MHz (51) |
| 459 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 149, Tf = 5745MHz (52) |
| 460 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 153, Tf = 5765MHz (53) |
| 461 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 157, Tf = 5785MHz (54) |
| 462 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 161, Tf = 5805MHz (55) |
| 463 | 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // channel = 165, Tf = 5825MHz (56) |
| 464 | }; |
| 465 | //}} RobertYu |
| 466 | |
| 467 | |
| 468 | |
| 469 | |
| 470 | /*--------------------- Static Functions --------------------------*/ |
| 471 | |
| 472 | |
| 473 | |
| 474 | |
| 475 | /* |
| 476 | * Description: AIROHA IFRF chip init function |
| 477 | * |
| 478 | * Parameters: |
| 479 | * In: |
| 480 | * dwIoBase - I/O base address |
| 481 | * Out: |
| 482 | * none |
| 483 | * |
| 484 | * Return Value: TRUE if succeeded; FALSE if failed. |
| 485 | * |
| 486 | */ |
| 487 | BOOL s_bAL7230Init (DWORD_PTR dwIoBase) |
| 488 | { |
| 489 | int ii; |
| 490 | BOOL bResult; |
| 491 | |
| 492 | bResult = TRUE; |
| 493 | |
| 494 | //3-wire control for normal mode |
| 495 | VNSvOutPortB(dwIoBase + MAC_REG_SOFTPWRCTL, 0); |
| 496 | |
| 497 | MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI | |
| 498 | SOFTPWRCTL_TXPEINV)); |
| 499 | BBvPowerSaveModeOFF(dwIoBase); //RobertYu:20050106, have DC value for Calibration |
| 500 | |
| 501 | for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++) |
| 502 | bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[ii]); |
| 503 | |
| 504 | // PLL On |
| 505 | MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); |
| 506 | |
| 507 | //Calibration |
| 508 | MACvTimer0MicroSDelay(dwIoBase, 150);//150us |
| 509 | bResult &= IFRFbWriteEmbeded(dwIoBase, (0x9ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW)); //TXDCOC:active, RCK:diable |
| 510 | MACvTimer0MicroSDelay(dwIoBase, 30);//30us |
| 511 | bResult &= IFRFbWriteEmbeded(dwIoBase, (0x3ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW)); //TXDCOC:diable, RCK:active |
| 512 | MACvTimer0MicroSDelay(dwIoBase, 30);//30us |
| 513 | bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[CB_AL7230_INIT_SEQ-1]); //TXDCOC:diable, RCK:diable |
| 514 | |
| 515 | MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 | |
| 516 | SOFTPWRCTL_SWPE2 | |
| 517 | SOFTPWRCTL_SWPECTI | |
| 518 | SOFTPWRCTL_TXPEINV)); |
| 519 | |
| 520 | BBvPowerSaveModeON(dwIoBase); // RobertYu:20050106 |
| 521 | |
| 522 | // PE1: TX_ON, PE2: RX_ON, PE3: PLLON |
| 523 | //3-wire control for power saving mode |
| 524 | VNSvOutPortB(dwIoBase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); //1100 0000 |
| 525 | |
| 526 | return bResult; |
| 527 | } |
| 528 | |
| 529 | // Need to Pull PLLON low when writing channel registers through 3-wire interface |
| 530 | BOOL s_bAL7230SelectChannel (DWORD_PTR dwIoBase, BYTE byChannel) |
| 531 | { |
| 532 | BOOL bResult; |
| 533 | |
| 534 | bResult = TRUE; |
| 535 | |
| 536 | // PLLON Off |
| 537 | MACvWordRegBitsOff(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); |
| 538 | |
| 539 | bResult &= IFRFbWriteEmbeded (dwIoBase, dwAL7230ChannelTable0[byChannel-1]); //Reg0 |
| 540 | bResult &= IFRFbWriteEmbeded (dwIoBase, dwAL7230ChannelTable1[byChannel-1]); //Reg1 |
| 541 | bResult &= IFRFbWriteEmbeded (dwIoBase, dwAL7230ChannelTable2[byChannel-1]); //Reg4 |
| 542 | |
| 543 | // PLLOn On |
| 544 | MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); |
| 545 | |
| 546 | // Set Channel[7] = 0 to tell H/W channel is changing now. |
| 547 | VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel & 0x7F)); |
| 548 | MACvTimer0MicroSDelay(dwIoBase, SWITCH_CHANNEL_DELAY_AL7230); |
| 549 | // Set Channel[7] = 1 to tell H/W channel change is done. |
| 550 | VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel | 0x80)); |
| 551 | |
| 552 | return bResult; |
| 553 | } |
| 554 | |
| 555 | /* |
| 556 | * Description: Select channel with UW2452 chip |
| 557 | * |
| 558 | * Parameters: |
| 559 | * In: |
| 560 | * dwIoBase - I/O base address |
| 561 | * uChannel - Channel number |
| 562 | * Out: |
| 563 | * none |
| 564 | * |
| 565 | * Return Value: TRUE if succeeded; FALSE if failed. |
| 566 | * |
| 567 | */ |
| 568 | |
| 569 | |
| 570 | //{{ RobertYu: 20041210 |
| 571 | /* |
| 572 | * Description: UW2452 IFRF chip init function |
| 573 | * |
| 574 | * Parameters: |
| 575 | * In: |
| 576 | * dwIoBase - I/O base address |
| 577 | * Out: |
| 578 | * none |
| 579 | * |
| 580 | * Return Value: TRUE if succeeded; FALSE if failed. |
| 581 | * |
| 582 | */ |
| 583 | |
| 584 | |
| 585 | |
| 586 | //}} RobertYu |
| 587 | //////////////////////////////////////////////////////////////////////////////// |
| 588 | |
| 589 | /* |
| 590 | * Description: VT3226 IFRF chip init function |
| 591 | * |
| 592 | * Parameters: |
| 593 | * In: |
| 594 | * dwIoBase - I/O base address |
| 595 | * Out: |
| 596 | * none |
| 597 | * |
| 598 | * Return Value: TRUE if succeeded; FALSE if failed. |
| 599 | * |
| 600 | */ |
| 601 | |
| 602 | /* |
| 603 | * Description: Select channel with VT3226 chip |
| 604 | * |
| 605 | * Parameters: |
| 606 | * In: |
| 607 | * dwIoBase - I/O base address |
| 608 | * uChannel - Channel number |
| 609 | * Out: |
| 610 | * none |
| 611 | * |
| 612 | * Return Value: TRUE if succeeded; FALSE if failed. |
| 613 | * |
| 614 | */ |
| 615 | |
| 616 | |
| 617 | |
| 618 | /*--------------------- Export Variables --------------------------*/ |
| 619 | |
| 620 | /*--------------------- Export Functions --------------------------*/ |
| 621 | |
| 622 | /* |
| 623 | * Description: Write to IF/RF, by embeded programming |
| 624 | * |
| 625 | * Parameters: |
| 626 | * In: |
| 627 | * dwIoBase - I/O base address |
| 628 | * dwData - data to write |
| 629 | * Out: |
| 630 | * none |
| 631 | * |
| 632 | * Return Value: TRUE if succeeded; FALSE if failed. |
| 633 | * |
| 634 | */ |
| 635 | BOOL IFRFbWriteEmbeded (DWORD_PTR dwIoBase, DWORD dwData) |
| 636 | { |
| 637 | WORD ww; |
| 638 | DWORD dwValue; |
| 639 | |
| 640 | VNSvOutPortD(dwIoBase + MAC_REG_IFREGCTL, dwData); |
| 641 | |
| 642 | // W_MAX_TIMEOUT is the timeout period |
| 643 | for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { |
| 644 | VNSvInPortD(dwIoBase + MAC_REG_IFREGCTL, &dwValue); |
| 645 | if (BITbIsBitOn(dwValue, IFREGCTL_DONE)) |
| 646 | break; |
| 647 | } |
| 648 | |
| 649 | if (ww == W_MAX_TIMEOUT) { |
| 650 | // DBG_PORT80_ALWAYS(0x32); |
| 651 | return FALSE; |
| 652 | } |
| 653 | return TRUE; |
| 654 | } |
| 655 | |
| 656 | |
| 657 | |
| 658 | /* |
| 659 | * Description: RFMD RF2959 IFRF chip init function |
| 660 | * |
| 661 | * Parameters: |
| 662 | * In: |
| 663 | * dwIoBase - I/O base address |
| 664 | * Out: |
| 665 | * none |
| 666 | * |
| 667 | * Return Value: TRUE if succeeded; FALSE if failed. |
| 668 | * |
| 669 | */ |
| 670 | |
| 671 | /* |
| 672 | * Description: Select channel with RFMD 2959 chip |
| 673 | * |
| 674 | * Parameters: |
| 675 | * In: |
| 676 | * dwIoBase - I/O base address |
| 677 | * uChannel - Channel number |
| 678 | * Out: |
| 679 | * none |
| 680 | * |
| 681 | * Return Value: TRUE if succeeded; FALSE if failed. |
| 682 | * |
| 683 | */ |
| 684 | |
| 685 | /* |
| 686 | * Description: AIROHA IFRF chip init function |
| 687 | * |
| 688 | * Parameters: |
| 689 | * In: |
| 690 | * dwIoBase - I/O base address |
| 691 | * Out: |
| 692 | * none |
| 693 | * |
| 694 | * Return Value: TRUE if succeeded; FALSE if failed. |
| 695 | * |
| 696 | */ |
| 697 | BOOL RFbAL2230Init (DWORD_PTR dwIoBase) |
| 698 | { |
| 699 | int ii; |
| 700 | BOOL bResult; |
| 701 | |
| 702 | bResult = TRUE; |
| 703 | |
| 704 | //3-wire control for normal mode |
| 705 | VNSvOutPortB(dwIoBase + MAC_REG_SOFTPWRCTL, 0); |
| 706 | |
| 707 | MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI | |
| 708 | SOFTPWRCTL_TXPEINV)); |
| 709 | //2008-8-21 chester <add> |
| 710 | // PLL Off |
| 711 | |
| 712 | MACvWordRegBitsOff(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); |
| 713 | |
| 714 | |
| 715 | |
| 716 | //patch abnormal AL2230 frequency output |
| 717 | //2008-8-21 chester <add> |
| 718 | IFRFbWriteEmbeded(dwIoBase, (0x07168700+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW)); |
| 719 | |
| 720 | |
| 721 | for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++) |
| 722 | bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL2230InitTable[ii]); |
| 723 | //2008-8-21 chester <add> |
| 724 | MACvTimer0MicroSDelay(dwIoBase, 30); //delay 30 us |
| 725 | |
| 726 | // PLL On |
| 727 | MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); |
| 728 | |
| 729 | MACvTimer0MicroSDelay(dwIoBase, 150);//150us |
| 730 | bResult &= IFRFbWriteEmbeded(dwIoBase, (0x00d80f00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW)); |
| 731 | MACvTimer0MicroSDelay(dwIoBase, 30);//30us |
| 732 | bResult &= IFRFbWriteEmbeded(dwIoBase, (0x00780f00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW)); |
| 733 | MACvTimer0MicroSDelay(dwIoBase, 30);//30us |
| 734 | bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL2230InitTable[CB_AL2230_INIT_SEQ-1]); |
| 735 | |
| 736 | MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 | |
| 737 | SOFTPWRCTL_SWPE2 | |
| 738 | SOFTPWRCTL_SWPECTI | |
| 739 | SOFTPWRCTL_TXPEINV)); |
| 740 | |
| 741 | //3-wire control for power saving mode |
| 742 | VNSvOutPortB(dwIoBase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); //1100 0000 |
| 743 | |
| 744 | return bResult; |
| 745 | } |
| 746 | |
| 747 | BOOL RFbAL2230SelectChannel (DWORD_PTR dwIoBase, BYTE byChannel) |
| 748 | { |
| 749 | BOOL bResult; |
| 750 | |
| 751 | bResult = TRUE; |
| 752 | |
| 753 | bResult &= IFRFbWriteEmbeded (dwIoBase, dwAL2230ChannelTable0[byChannel-1]); |
| 754 | bResult &= IFRFbWriteEmbeded (dwIoBase, dwAL2230ChannelTable1[byChannel-1]); |
| 755 | |
| 756 | // Set Channel[7] = 0 to tell H/W channel is changing now. |
| 757 | VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel & 0x7F)); |
| 758 | MACvTimer0MicroSDelay(dwIoBase, SWITCH_CHANNEL_DELAY_AL2230); |
| 759 | // Set Channel[7] = 1 to tell H/W channel change is done. |
| 760 | VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel | 0x80)); |
| 761 | |
| 762 | return bResult; |
| 763 | } |
| 764 | |
| 765 | /* |
| 766 | * Description: UW2451 IFRF chip init function |
| 767 | * |
| 768 | * Parameters: |
| 769 | * In: |
| 770 | * dwIoBase - I/O base address |
| 771 | * Out: |
| 772 | * none |
| 773 | * |
| 774 | * Return Value: TRUE if succeeded; FALSE if failed. |
| 775 | * |
| 776 | */ |
| 777 | |
| 778 | |
| 779 | /* |
| 780 | * Description: Select channel with UW2451 chip |
| 781 | * |
| 782 | * Parameters: |
| 783 | * In: |
| 784 | * dwIoBase - I/O base address |
| 785 | * uChannel - Channel number |
| 786 | * Out: |
| 787 | * none |
| 788 | * |
| 789 | * Return Value: TRUE if succeeded; FALSE if failed. |
| 790 | * |
| 791 | */ |
| 792 | |
| 793 | /* |
| 794 | * Description: Set sleep mode to UW2451 chip |
| 795 | * |
| 796 | * Parameters: |
| 797 | * In: |
| 798 | * dwIoBase - I/O base address |
| 799 | * uChannel - Channel number |
| 800 | * Out: |
| 801 | * none |
| 802 | * |
| 803 | * Return Value: TRUE if succeeded; FALSE if failed. |
| 804 | * |
| 805 | */ |
| 806 | |
| 807 | /* |
| 808 | * Description: RF init function |
| 809 | * |
| 810 | * Parameters: |
| 811 | * In: |
| 812 | * byBBType |
| 813 | * byRFType |
| 814 | * Out: |
| 815 | * none |
| 816 | * |
| 817 | * Return Value: TRUE if succeeded; FALSE if failed. |
| 818 | * |
| 819 | */ |
| 820 | BOOL RFbInit ( |
| 821 | IN PSDevice pDevice |
| 822 | ) |
| 823 | { |
| 824 | BOOL bResult = TRUE; |
| 825 | switch (pDevice->byRFType) { |
| 826 | case RF_AIROHA : |
| 827 | case RF_AL2230S: |
| 828 | pDevice->byMaxPwrLevel = AL2230_PWR_IDX_LEN; |
| 829 | bResult = RFbAL2230Init(pDevice->PortOffset); |
| 830 | break; |
| 831 | case RF_AIROHA7230 : |
| 832 | pDevice->byMaxPwrLevel = AL7230_PWR_IDX_LEN; |
| 833 | bResult = s_bAL7230Init(pDevice->PortOffset); |
| 834 | break; |
| 835 | case RF_NOTHING : |
| 836 | bResult = TRUE; |
| 837 | break; |
| 838 | default : |
| 839 | bResult = FALSE; |
| 840 | break; |
| 841 | } |
| 842 | return bResult; |
| 843 | } |
| 844 | |
| 845 | /* |
| 846 | * Description: RF ShutDown function |
| 847 | * |
| 848 | * Parameters: |
| 849 | * In: |
| 850 | * byBBType |
| 851 | * byRFType |
| 852 | * Out: |
| 853 | * none |
| 854 | * |
| 855 | * Return Value: TRUE if succeeded; FALSE if failed. |
| 856 | * |
| 857 | */ |
| 858 | BOOL RFbShutDown ( |
| 859 | IN PSDevice pDevice |
| 860 | ) |
| 861 | { |
| 862 | BOOL bResult = TRUE; |
| 863 | |
| 864 | switch (pDevice->byRFType) { |
| 865 | case RF_AIROHA7230 : |
| 866 | bResult = IFRFbWriteEmbeded (pDevice->PortOffset, 0x1ABAEF00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW); |
| 867 | break; |
| 868 | default : |
| 869 | bResult = TRUE; |
| 870 | break; |
| 871 | } |
| 872 | return bResult; |
| 873 | } |
| 874 | |
| 875 | /* |
| 876 | * Description: Select channel |
| 877 | * |
| 878 | * Parameters: |
| 879 | * In: |
| 880 | * byRFType |
| 881 | * byChannel - Channel number |
| 882 | * Out: |
| 883 | * none |
| 884 | * |
| 885 | * Return Value: TRUE if succeeded; FALSE if failed. |
| 886 | * |
| 887 | */ |
| 888 | BOOL RFbSelectChannel (DWORD_PTR dwIoBase, BYTE byRFType, BYTE byChannel) |
| 889 | { |
| 890 | BOOL bResult = TRUE; |
| 891 | switch (byRFType) { |
| 892 | |
| 893 | case RF_AIROHA : |
| 894 | case RF_AL2230S: |
| 895 | bResult = RFbAL2230SelectChannel(dwIoBase, byChannel); |
| 896 | break; |
| 897 | //{{ RobertYu: 20050104 |
| 898 | case RF_AIROHA7230 : |
| 899 | bResult = s_bAL7230SelectChannel(dwIoBase, byChannel); |
| 900 | break; |
| 901 | //}} RobertYu |
| 902 | case RF_NOTHING : |
| 903 | bResult = TRUE; |
| 904 | break; |
| 905 | default: |
| 906 | bResult = FALSE; |
| 907 | break; |
| 908 | } |
| 909 | return bResult; |
| 910 | } |
| 911 | |
| 912 | /* |
| 913 | * Description: Write WakeProgSyn |
| 914 | * |
| 915 | * Parameters: |
| 916 | * In: |
| 917 | * dwIoBase - I/O base address |
| 918 | * uChannel - channel number |
| 919 | * bySleepCnt - SleepProgSyn count |
| 920 | * |
| 921 | * Return Value: None. |
| 922 | * |
| 923 | */ |
| 924 | BOOL RFvWriteWakeProgSyn (DWORD_PTR dwIoBase, BYTE byRFType, UINT uChannel) |
| 925 | { |
| 926 | int ii; |
| 927 | BYTE byInitCount = 0; |
| 928 | BYTE bySleepCount = 0; |
| 929 | |
| 930 | VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, 0); |
| 931 | switch (byRFType) { |
| 932 | case RF_AIROHA: |
| 933 | case RF_AL2230S: |
| 934 | |
| 935 | if (uChannel > CB_MAX_CHANNEL_24G) |
| 936 | return FALSE; |
| 937 | |
| 938 | byInitCount = CB_AL2230_INIT_SEQ + 2; // Init Reg + Channel Reg (2) |
| 939 | bySleepCount = 0; |
| 940 | if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount)) { |
| 941 | return FALSE; |
| 942 | } |
| 943 | |
| 944 | for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++ ) { |
| 945 | MACvSetMISCFifo(dwIoBase, (WORD)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230InitTable[ii]); |
| 946 | } |
| 947 | MACvSetMISCFifo(dwIoBase, (WORD)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable0[uChannel-1]); |
| 948 | ii ++; |
| 949 | MACvSetMISCFifo(dwIoBase, (WORD)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable1[uChannel-1]); |
| 950 | break; |
| 951 | |
| 952 | //{{ RobertYu: 20050104 |
| 953 | // Need to check, PLLON need to be low for channel setting |
| 954 | case RF_AIROHA7230: |
| 955 | byInitCount = CB_AL7230_INIT_SEQ + 3; // Init Reg + Channel Reg (3) |
| 956 | bySleepCount = 0; |
| 957 | if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount)) { |
| 958 | return FALSE; |
| 959 | } |
| 960 | |
| 961 | if (uChannel <= CB_MAX_CHANNEL_24G) |
| 962 | { |
| 963 | for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++ ) { |
| 964 | MACvSetMISCFifo(dwIoBase, (WORD)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTable[ii]); |
| 965 | } |
| 966 | } |
| 967 | else |
| 968 | { |
| 969 | for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++ ) { |
| 970 | MACvSetMISCFifo(dwIoBase, (WORD)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTableAMode[ii]); |
| 971 | } |
| 972 | } |
| 973 | |
| 974 | MACvSetMISCFifo(dwIoBase, (WORD)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable0[uChannel-1]); |
| 975 | ii ++; |
| 976 | MACvSetMISCFifo(dwIoBase, (WORD)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable1[uChannel-1]); |
| 977 | ii ++; |
| 978 | MACvSetMISCFifo(dwIoBase, (WORD)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable2[uChannel-1]); |
| 979 | break; |
| 980 | //}} RobertYu |
| 981 | |
| 982 | case RF_NOTHING : |
| 983 | return TRUE; |
| 984 | break; |
| 985 | |
| 986 | default: |
| 987 | return FALSE; |
| 988 | break; |
| 989 | } |
| 990 | |
| 991 | MACvSetMISCFifo(dwIoBase, MISCFIFO_SYNINFO_IDX, (DWORD)MAKEWORD(bySleepCount, byInitCount)); |
| 992 | |
| 993 | return TRUE; |
| 994 | } |
| 995 | |
| 996 | /* |
| 997 | * Description: Set Tx power |
| 998 | * |
| 999 | * Parameters: |
| 1000 | * In: |
| 1001 | * dwIoBase - I/O base address |
| 1002 | * dwRFPowerTable - RF Tx Power Setting |
| 1003 | * Out: |
| 1004 | * none |
| 1005 | * |
| 1006 | * Return Value: TRUE if succeeded; FALSE if failed. |
| 1007 | * |
| 1008 | */ |
| 1009 | BOOL RFbSetPower ( |
| 1010 | IN PSDevice pDevice, |
| 1011 | IN UINT uRATE, |
| 1012 | IN UINT uCH |
| 1013 | ) |
| 1014 | { |
| 1015 | BOOL bResult = TRUE; |
| 1016 | BYTE byPwr = 0; |
| 1017 | BYTE byDec = 0; |
| 1018 | BYTE byPwrdBm = 0; |
| 1019 | |
| 1020 | if (pDevice->dwDiagRefCount != 0) { |
| 1021 | return TRUE; |
| 1022 | } |
| 1023 | if ((uCH < 1) || (uCH > CB_MAX_CHANNEL)) { |
| 1024 | return FALSE; |
| 1025 | } |
| 1026 | |
| 1027 | switch (uRATE) { |
| 1028 | case RATE_1M: |
| 1029 | case RATE_2M: |
| 1030 | case RATE_5M: |
| 1031 | case RATE_11M: |
| 1032 | byPwr = pDevice->abyCCKPwrTbl[uCH]; |
| 1033 | byPwrdBm = pDevice->abyCCKDefaultPwr[uCH]; |
| 1034 | //PLICE_DEBUG-> |
| 1035 | //byPwr+=5; |
| 1036 | //PLICE_DEBUG <- |
| 1037 | |
| 1038 | //printk("Rate <11:byPwr is %d\n",byPwr); |
| 1039 | break; |
| 1040 | case RATE_6M: |
| 1041 | case RATE_9M: |
| 1042 | case RATE_18M: |
| 1043 | byPwr = pDevice->abyOFDMPwrTbl[uCH]; |
| 1044 | if (pDevice->byRFType == RF_UW2452) { |
| 1045 | byDec = byPwr + 14; |
| 1046 | } else { |
| 1047 | byDec = byPwr + 10; |
| 1048 | } |
| 1049 | if (byDec >= pDevice->byMaxPwrLevel) { |
| 1050 | byDec = pDevice->byMaxPwrLevel-1; |
| 1051 | } |
| 1052 | if (pDevice->byRFType == RF_UW2452) { |
| 1053 | byPwrdBm = byDec - byPwr; |
| 1054 | byPwrdBm /= 3; |
| 1055 | } else { |
| 1056 | byPwrdBm = byDec - byPwr; |
| 1057 | byPwrdBm >>= 1; |
| 1058 | } |
| 1059 | byPwrdBm += pDevice->abyOFDMDefaultPwr[uCH]; |
| 1060 | byPwr = byDec; |
| 1061 | //PLICE_DEBUG-> |
| 1062 | //byPwr+=5; |
| 1063 | //PLICE_DEBUG<- |
| 1064 | |
| 1065 | //printk("Rate <24:byPwr is %d\n",byPwr); |
| 1066 | break; |
| 1067 | case RATE_24M: |
| 1068 | case RATE_36M: |
| 1069 | case RATE_48M: |
| 1070 | case RATE_54M: |
| 1071 | byPwr = pDevice->abyOFDMPwrTbl[uCH]; |
| 1072 | byPwrdBm = pDevice->abyOFDMDefaultPwr[uCH]; |
| 1073 | //PLICE_DEBUG-> |
| 1074 | //byPwr+=5; |
| 1075 | //PLICE_DEBUG<- |
| 1076 | //printk("Rate < 54:byPwr is %d\n",byPwr); |
| 1077 | break; |
| 1078 | } |
| 1079 | |
| 1080 | #if 0 |
| 1081 | |
| 1082 | // 802.11h TPC |
| 1083 | if (pDevice->bLinkPass == TRUE) { |
| 1084 | // do not over local constraint |
| 1085 | if (byPwrdBm > pDevice->abyLocalPwr[uCH]) { |
| 1086 | pDevice->byCurPwrdBm = pDevice->abyLocalPwr[uCH]; |
| 1087 | byDec = byPwrdBm - pDevice->abyLocalPwr[uCH]; |
| 1088 | if (pDevice->byRFType == RF_UW2452) { |
| 1089 | byDec *= 3; |
| 1090 | } else { |
| 1091 | byDec <<= 1; |
| 1092 | } |
| 1093 | if (byPwr > byDec) { |
| 1094 | byPwr -= byDec; |
| 1095 | } else { |
| 1096 | byPwr = 0; |
| 1097 | } |
| 1098 | } else { |
| 1099 | pDevice->byCurPwrdBm = byPwrdBm; |
| 1100 | } |
| 1101 | } else { |
| 1102 | // do not over regulatory constraint |
| 1103 | if (byPwrdBm > pDevice->abyRegPwr[uCH]) { |
| 1104 | pDevice->byCurPwrdBm = pDevice->abyRegPwr[uCH]; |
| 1105 | byDec = byPwrdBm - pDevice->abyRegPwr[uCH]; |
| 1106 | if (pDevice->byRFType == RF_UW2452) { |
| 1107 | byDec *= 3; |
| 1108 | } else { |
| 1109 | byDec <<= 1; |
| 1110 | } |
| 1111 | if (byPwr > byDec) { |
| 1112 | byPwr -= byDec; |
| 1113 | } else { |
| 1114 | byPwr = 0; |
| 1115 | } |
| 1116 | } else { |
| 1117 | pDevice->byCurPwrdBm = byPwrdBm; |
| 1118 | } |
| 1119 | } |
| 1120 | #endif |
| 1121 | |
| 1122 | // if (pDevice->byLocalID <= REV_ID_VT3253_B1) { |
| 1123 | if (pDevice->byCurPwr == byPwr) { |
| 1124 | return TRUE; |
| 1125 | } |
| 1126 | bResult = RFbRawSetPower(pDevice, byPwr, uRATE); |
| 1127 | // } |
| 1128 | if (bResult == TRUE) { |
| 1129 | pDevice->byCurPwr = byPwr; |
| 1130 | } |
| 1131 | return bResult; |
| 1132 | } |
| 1133 | |
| 1134 | /* |
| 1135 | * Description: Set Tx power |
| 1136 | * |
| 1137 | * Parameters: |
| 1138 | * In: |
| 1139 | * dwIoBase - I/O base address |
| 1140 | * dwRFPowerTable - RF Tx Power Setting |
| 1141 | * Out: |
| 1142 | * none |
| 1143 | * |
| 1144 | * Return Value: TRUE if succeeded; FALSE if failed. |
| 1145 | * |
| 1146 | */ |
| 1147 | |
| 1148 | BOOL RFbRawSetPower ( |
| 1149 | IN PSDevice pDevice, |
| 1150 | IN BYTE byPwr, |
| 1151 | IN UINT uRATE |
| 1152 | ) |
| 1153 | { |
| 1154 | BOOL bResult = TRUE; |
| 1155 | DWORD dwMax7230Pwr = 0; |
| 1156 | |
| 1157 | if (byPwr >= pDevice->byMaxPwrLevel) { |
| 1158 | return (FALSE); |
| 1159 | } |
| 1160 | switch (pDevice->byRFType) { |
| 1161 | |
| 1162 | case RF_AIROHA : |
| 1163 | bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, dwAL2230PowerTable[byPwr]); |
| 1164 | if (uRATE <= RATE_11M) { |
| 1165 | bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, 0x0001B400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); |
| 1166 | } else { |
| 1167 | bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); |
| 1168 | } |
| 1169 | break; |
| 1170 | |
| 1171 | |
| 1172 | case RF_AL2230S : |
| 1173 | bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, dwAL2230PowerTable[byPwr]); |
| 1174 | if (uRATE <= RATE_11M) { |
| 1175 | bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, 0x040C1400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); |
| 1176 | bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, 0x00299B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); |
| 1177 | }else { |
| 1178 | bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); |
| 1179 | bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, 0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); |
| 1180 | } |
| 1181 | |
| 1182 | break; |
| 1183 | |
| 1184 | case RF_AIROHA7230: |
| 1185 | // 0x080F1B00 for 3 wire control TxGain(D10) and 0x31 as TX Gain value |
| 1186 | dwMax7230Pwr = 0x080C0B00 | ( (byPwr) << 12 ) | |
| 1187 | (BY_AL7230_REG_LEN << 3 ) | IFREGCTL_REGW; |
| 1188 | |
| 1189 | bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, dwMax7230Pwr); |
| 1190 | break; |
| 1191 | |
| 1192 | |
| 1193 | default : |
| 1194 | break; |
| 1195 | } |
| 1196 | return bResult; |
| 1197 | } |
| 1198 | |
| 1199 | /*+ |
| 1200 | * |
| 1201 | * Routine Description: |
| 1202 | * Translate RSSI to dBm |
| 1203 | * |
| 1204 | * Parameters: |
| 1205 | * In: |
| 1206 | * pDevice - The adapter to be translated |
| 1207 | * byCurrRSSI - RSSI to be translated |
| 1208 | * Out: |
| 1209 | * pdwdbm - Translated dbm number |
| 1210 | * |
| 1211 | * Return Value: none |
| 1212 | * |
| 1213 | -*/ |
| 1214 | VOID |
| 1215 | RFvRSSITodBm ( |
| 1216 | IN PSDevice pDevice, |
| 1217 | IN BYTE byCurrRSSI, |
| 1218 | OUT PLONG pldBm |
| 1219 | ) |
| 1220 | { |
| 1221 | BYTE byIdx = (((byCurrRSSI & 0xC0) >> 6) & 0x03); |
| 1222 | LONG b = (byCurrRSSI & 0x3F); |
| 1223 | LONG a = 0; |
| 1224 | BYTE abyAIROHARF[4] = {0, 18, 0, 40}; |
| 1225 | |
| 1226 | switch (pDevice->byRFType) { |
| 1227 | case RF_AIROHA: |
| 1228 | case RF_AL2230S: |
| 1229 | case RF_AIROHA7230: //RobertYu: 20040104 |
| 1230 | a = abyAIROHARF[byIdx]; |
| 1231 | break; |
| 1232 | default: |
| 1233 | break; |
| 1234 | } |
| 1235 | |
| 1236 | *pldBm = -1 * (a + b * 2); |
| 1237 | } |
| 1238 | |
| 1239 | //////////////////////////////////////////////////////////////////////////////// |
| 1240 | //{{ RobertYu: 20050104 |
| 1241 | |
| 1242 | |
| 1243 | // Post processing for the 11b/g and 11a. |
| 1244 | // for save time on changing Reg2,3,5,7,10,12,15 |
| 1245 | BOOL RFbAL7230SelectChannelPostProcess (DWORD_PTR dwIoBase, BYTE byOldChannel, BYTE byNewChannel) |
| 1246 | { |
| 1247 | BOOL bResult; |
| 1248 | |
| 1249 | bResult = TRUE; |
| 1250 | |
| 1251 | // if change between 11 b/g and 11a need to update the following register |
| 1252 | // Channel Index 1~14 |
| 1253 | |
| 1254 | if( (byOldChannel <= CB_MAX_CHANNEL_24G) && (byNewChannel > CB_MAX_CHANNEL_24G) ) |
| 1255 | { |
| 1256 | // Change from 2.4G to 5G |
| 1257 | bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTableAMode[2]); //Reg2 |
| 1258 | bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTableAMode[3]); //Reg3 |
| 1259 | bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTableAMode[5]); //Reg5 |
| 1260 | bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTableAMode[7]); //Reg7 |
| 1261 | bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTableAMode[10]);//Reg10 |
| 1262 | bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTableAMode[12]);//Reg12 |
| 1263 | bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTableAMode[15]);//Reg15 |
| 1264 | } |
| 1265 | else if( (byOldChannel > CB_MAX_CHANNEL_24G) && (byNewChannel <= CB_MAX_CHANNEL_24G) ) |
| 1266 | { |
| 1267 | // change from 5G to 2.4G |
| 1268 | bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[2]); //Reg2 |
| 1269 | bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[3]); //Reg3 |
| 1270 | bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[5]); //Reg5 |
| 1271 | bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[7]); //Reg7 |
| 1272 | bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[10]);//Reg10 |
| 1273 | bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[12]);//Reg12 |
| 1274 | bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[15]);//Reg15 |
| 1275 | } |
| 1276 | |
| 1277 | return bResult; |
| 1278 | } |
| 1279 | |
| 1280 | |
| 1281 | //}} RobertYu |
| 1282 | //////////////////////////////////////////////////////////////////////////////// |
| 1283 | |