Mauro Carvalho Chehab | 4d2e26a | 2019-04-10 08:32:42 -0300 | [diff] [blame] | 1 | ============ |
Michael Ellerman | 91a6151 | 2014-05-26 21:44:25 +1000 | [diff] [blame] | 2 | CPU Families |
| 3 | ============ |
| 4 | |
| 5 | This document tries to summarise some of the different cpu families that exist |
| 6 | and are supported by arch/powerpc. |
| 7 | |
| 8 | |
| 9 | Book3S (aka sPAPR) |
| 10 | ------------------ |
| 11 | |
Christophe Leroy | 7d38f08 | 2020-07-02 14:09:21 +0000 | [diff] [blame] | 12 | - Hash MMU (except 603 and e300) |
Nicholas Miehlbradt | addebe1 | 2022-08-10 04:03:21 +0000 | [diff] [blame] | 13 | - Radix MMU (POWER9 and later) |
Christophe Leroy | 7d38f08 | 2020-07-02 14:09:21 +0000 | [diff] [blame] | 14 | - Software loaded TLB (603 and e300) |
| 15 | - Selectable Software loaded TLB in addition to hash MMU (755, 7450, e600) |
Mauro Carvalho Chehab | 4d2e26a | 2019-04-10 08:32:42 -0300 | [diff] [blame] | 16 | - Mix of 32 & 64 bit:: |
Michael Ellerman | 91a6151 | 2014-05-26 21:44:25 +1000 | [diff] [blame] | 17 | |
| 18 | +--------------+ +----------------+ |
| 19 | | Old POWER | --------------> | RS64 (threads) | |
| 20 | +--------------+ +----------------+ |
| 21 | | |
| 22 | | |
| 23 | v |
| 24 | +--------------+ +----------------+ +------+ |
| 25 | | 601 | --------------> | 603 | ---> | e300 | |
| 26 | +--------------+ +----------------+ +------+ |
| 27 | | | |
| 28 | | | |
| 29 | v v |
Christophe Leroy | 7d38f08 | 2020-07-02 14:09:21 +0000 | [diff] [blame] | 30 | +--------------+ +-----+ +----------------+ +-------+ |
| 31 | | 604 | | 755 | <--- | 750 (G3) | ---> | 750CX | |
| 32 | +--------------+ +-----+ +----------------+ +-------+ |
Michael Ellerman | 91a6151 | 2014-05-26 21:44:25 +1000 | [diff] [blame] | 33 | | | | |
| 34 | | | | |
| 35 | v v v |
| 36 | +--------------+ +----------------+ +-------+ |
| 37 | | 620 (64 bit) | | 7400 | | 750CL | |
| 38 | +--------------+ +----------------+ +-------+ |
| 39 | | | | |
| 40 | | | | |
| 41 | v v v |
| 42 | +--------------+ +----------------+ +-------+ |
| 43 | | POWER3/630 | | 7410 | | 750FX | |
| 44 | +--------------+ +----------------+ +-------+ |
| 45 | | | |
| 46 | | | |
| 47 | v v |
| 48 | +--------------+ +----------------+ |
| 49 | | POWER3+ | | 7450 | |
| 50 | +--------------+ +----------------+ |
| 51 | | | |
| 52 | | | |
| 53 | v v |
| 54 | +--------------+ +----------------+ |
| 55 | | POWER4 | | 7455 | |
| 56 | +--------------+ +----------------+ |
| 57 | | | |
| 58 | | | |
| 59 | v v |
| 60 | +--------------+ +-------+ +----------------+ |
| 61 | | POWER4+ | --> | 970 | | 7447 | |
| 62 | +--------------+ +-------+ +----------------+ |
| 63 | | | | |
| 64 | | | | |
| 65 | v v v |
| 66 | +--------------+ +-------+ +----------------+ |
| 67 | | POWER5 | | 970FX | | 7448 | |
| 68 | +--------------+ +-------+ +----------------+ |
| 69 | | | | |
| 70 | | | | |
| 71 | v v v |
| 72 | +--------------+ +-------+ +----------------+ |
| 73 | | POWER5+ | | 970MP | | e600 | |
| 74 | +--------------+ +-------+ +----------------+ |
| 75 | | |
| 76 | | |
| 77 | v |
| 78 | +--------------+ |
| 79 | | POWER5++ | |
| 80 | +--------------+ |
| 81 | | |
| 82 | | |
| 83 | v |
| 84 | +--------------+ +-------+ |
| 85 | | POWER6 | <-?-> | Cell | |
| 86 | +--------------+ +-------+ |
| 87 | | |
| 88 | | |
| 89 | v |
| 90 | +--------------+ |
| 91 | | POWER7 | |
| 92 | +--------------+ |
| 93 | | |
| 94 | | |
| 95 | v |
| 96 | +--------------+ |
| 97 | | POWER7+ | |
| 98 | +--------------+ |
| 99 | | |
| 100 | | |
| 101 | v |
| 102 | +--------------+ |
| 103 | | POWER8 | |
| 104 | +--------------+ |
Nicholas Miehlbradt | addebe1 | 2022-08-10 04:03:21 +0000 | [diff] [blame] | 105 | | |
| 106 | | |
| 107 | v |
| 108 | +--------------+ |
| 109 | | POWER9 | |
| 110 | +--------------+ |
| 111 | | |
| 112 | | |
| 113 | v |
| 114 | +--------------+ |
| 115 | | POWER10 | |
| 116 | +--------------+ |
Michael Ellerman | 91a6151 | 2014-05-26 21:44:25 +1000 | [diff] [blame] | 117 | |
| 118 | |
| 119 | +---------------+ |
| 120 | | PA6T (64 bit) | |
| 121 | +---------------+ |
| 122 | |
| 123 | |
| 124 | IBM BookE |
| 125 | --------- |
| 126 | |
Mauro Carvalho Chehab | 4d2e26a | 2019-04-10 08:32:42 -0300 | [diff] [blame] | 127 | - Software loaded TLB. |
| 128 | - All 32 bit:: |
Michael Ellerman | 91a6151 | 2014-05-26 21:44:25 +1000 | [diff] [blame] | 129 | |
| 130 | +--------------+ |
| 131 | | 401 | |
| 132 | +--------------+ |
| 133 | | |
| 134 | | |
| 135 | v |
| 136 | +--------------+ |
| 137 | | 403 | |
| 138 | +--------------+ |
| 139 | | |
| 140 | | |
| 141 | v |
| 142 | +--------------+ |
| 143 | | 405 | |
| 144 | +--------------+ |
| 145 | | |
| 146 | | |
| 147 | v |
| 148 | +--------------+ |
| 149 | | 440 | |
| 150 | +--------------+ |
| 151 | | |
| 152 | | |
| 153 | v |
| 154 | +--------------+ +----------------+ |
| 155 | | 450 | --> | BG/P | |
| 156 | +--------------+ +----------------+ |
| 157 | | |
| 158 | | |
| 159 | v |
| 160 | +--------------+ |
| 161 | | 460 | |
| 162 | +--------------+ |
| 163 | | |
| 164 | | |
| 165 | v |
| 166 | +--------------+ |
| 167 | | 476 | |
| 168 | +--------------+ |
| 169 | |
| 170 | |
| 171 | Motorola/Freescale 8xx |
| 172 | ---------------------- |
| 173 | |
Mauro Carvalho Chehab | 4d2e26a | 2019-04-10 08:32:42 -0300 | [diff] [blame] | 174 | - Software loaded with hardware assist. |
| 175 | - All 32 bit:: |
Michael Ellerman | 91a6151 | 2014-05-26 21:44:25 +1000 | [diff] [blame] | 176 | |
| 177 | +-------------+ |
| 178 | | MPC8xx Core | |
| 179 | +-------------+ |
| 180 | |
| 181 | |
| 182 | Freescale BookE |
| 183 | --------------- |
| 184 | |
Mauro Carvalho Chehab | 4d2e26a | 2019-04-10 08:32:42 -0300 | [diff] [blame] | 185 | - Software loaded TLB. |
| 186 | - e6500 adds HW loaded indirect TLB entries. |
| 187 | - Mix of 32 & 64 bit:: |
Michael Ellerman | 91a6151 | 2014-05-26 21:44:25 +1000 | [diff] [blame] | 188 | |
| 189 | +--------------+ |
| 190 | | e200 | |
| 191 | +--------------+ |
| 192 | |
| 193 | |
| 194 | +--------------------------------+ |
| 195 | | e500 | |
| 196 | +--------------------------------+ |
| 197 | | |
| 198 | | |
| 199 | v |
| 200 | +--------------------------------+ |
| 201 | | e500v2 | |
| 202 | +--------------------------------+ |
| 203 | | |
| 204 | | |
| 205 | v |
| 206 | +--------------------------------+ |
| 207 | | e500mc (Book3e) | |
| 208 | +--------------------------------+ |
| 209 | | |
| 210 | | |
| 211 | v |
| 212 | +--------------------------------+ |
| 213 | | e5500 (64 bit) | |
| 214 | +--------------------------------+ |
| 215 | | |
| 216 | | |
| 217 | v |
| 218 | +--------------------------------+ |
| 219 | | e6500 (HW TLB) (Multithreaded) | |
| 220 | +--------------------------------+ |
| 221 | |
| 222 | |
| 223 | IBM A2 core |
| 224 | ----------- |
| 225 | |
Mauro Carvalho Chehab | 4d2e26a | 2019-04-10 08:32:42 -0300 | [diff] [blame] | 226 | - Book3E, software loaded TLB + HW loaded indirect TLB entries. |
| 227 | - 64 bit:: |
Michael Ellerman | 91a6151 | 2014-05-26 21:44:25 +1000 | [diff] [blame] | 228 | |
| 229 | +--------------+ +----------------+ |
| 230 | | A2 core | --> | WSP | |
| 231 | +--------------+ +----------------+ |
| 232 | | |
| 233 | | |
| 234 | v |
| 235 | +--------------+ |
| 236 | | BG/Q | |
| 237 | +--------------+ |