blob: 1271b839a107ef28013ab10f342c64a835a52047 [file] [log] [blame]
Kuninori Morimoto5933f6d2018-12-28 00:32:24 -08001// SPDX-License-Identifier: GPL-2.0
Paul Mundt6b002232006-10-12 17:07:45 +09002/*
3 * 'traps.c' handles hardware traps and faults after we have saved some
4 * state in 'entry.S'.
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 *
6 * SuperH version: Copyright (C) 1999 Niibe Yutaka
7 * Copyright (C) 2000 Philipp Rumpf
8 * Copyright (C) 2000 David Howells
Paul Mundtace2dc72010-10-13 06:55:26 +09009 * Copyright (C) 2002 - 2010 Paul Mundt
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070011#include <linux/kernel.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070012#include <linux/ptrace.h>
Russell Kingba84be22009-01-06 14:41:07 -080013#include <linux/hardirq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/init.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070015#include <linux/spinlock.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070016#include <linux/kallsyms.h>
Paul Mundt1f666582006-10-19 16:20:25 +090017#include <linux/io.h>
Paul Mundtfa691512007-03-08 19:41:21 +090018#include <linux/bug.h>
Paul Mundt9b8c90e2006-12-06 11:07:51 +090019#include <linux/debug_locks.h>
Paul Mundtb118ca52007-05-09 10:55:38 +090020#include <linux/kdebug.h>
Paul Mundtdc34d312006-12-08 17:41:43 +090021#include <linux/limits.h>
Paul Mundtaf67c3a2009-10-13 10:57:52 +090022#include <linux/sysfs.h>
Paul Mundta99eae52010-01-12 16:12:25 +090023#include <linux/uaccess.h>
Paul Mundtace2dc72010-10-13 06:55:26 +090024#include <linux/perf_event.h>
Ingo Molnar68db0cf2017-02-08 18:51:37 +010025#include <linux/sched/task_stack.h>
26
Paul Mundta99eae52010-01-12 16:12:25 +090027#include <asm/alignment.h>
Andrew Mortonfad0f902008-04-16 02:03:51 +090028#include <asm/fpu.h>
Chris Smithd39f5452008-09-05 17:15:39 +090029#include <asm/kprobes.h>
Geert Uytterhoeven86a2da42024-03-01 22:02:20 +010030#include <asm/setup.h>
David Howellse839ca52012-03-28 18:30:03 +010031#include <asm/traps.h>
32#include <asm/bl_bit.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070033
Linus Torvalds1da177e2005-04-16 15:20:36 -070034#ifdef CONFIG_CPU_SH2
Yoshinori Sato0983b312006-11-05 15:58:47 +090035# define TRAP_RESERVED_INST 4
36# define TRAP_ILLEGAL_SLOT_INST 6
37# define TRAP_ADDRESS_ERROR 9
38# ifdef CONFIG_CPU_SH2A
Peter Griffincd894362009-05-08 15:51:51 +010039# define TRAP_UBC 12
Yoshinori Sato6e80f5e2008-07-10 01:20:03 +090040# define TRAP_FPU_ERROR 13
Yoshinori Sato0983b312006-11-05 15:58:47 +090041# define TRAP_DIVZERO_ERROR 17
42# define TRAP_DIVOVF_ERROR 18
43# endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070044#else
45#define TRAP_RESERVED_INST 12
46#define TRAP_ILLEGAL_SLOT_INST 13
47#endif
48
Magnus Damm86c01792008-02-07 00:02:50 +090049static inline void sign_extend(unsigned int count, unsigned char *dst)
50{
51#ifdef __LITTLE_ENDIAN__
Magnus Damm4252c652008-02-07 19:58:46 +090052 if ((count == 1) && dst[0] & 0x80) {
53 dst[1] = 0xff;
54 dst[2] = 0xff;
55 dst[3] = 0xff;
56 }
Magnus Damm86c01792008-02-07 00:02:50 +090057 if ((count == 2) && dst[1] & 0x80) {
58 dst[2] = 0xff;
59 dst[3] = 0xff;
60 }
61#else
Magnus Damm4252c652008-02-07 19:58:46 +090062 if ((count == 1) && dst[3] & 0x80) {
63 dst[2] = 0xff;
Magnus Damm86c01792008-02-07 00:02:50 +090064 dst[1] = 0xff;
Magnus Damm4252c652008-02-07 19:58:46 +090065 dst[0] = 0xff;
66 }
67 if ((count == 2) && dst[2] & 0x80) {
68 dst[1] = 0xff;
69 dst[0] = 0xff;
Magnus Damm86c01792008-02-07 00:02:50 +090070 }
71#endif
72}
73
Magnus Damme7cc9a72008-02-07 20:18:21 +090074static struct mem_access user_mem_access = {
75 copy_from_user,
76 copy_to_user,
77};
78
Arnd Bergmann75d4d292022-02-11 17:26:42 +010079static unsigned long copy_from_kernel_wrapper(void *dst, const void __user *src,
80 unsigned long cnt)
81{
82 return copy_from_kernel_nofault(dst, (const void __force *)src, cnt);
83}
84
85static unsigned long copy_to_kernel_wrapper(void __user *dst, const void *src,
86 unsigned long cnt)
87{
88 return copy_to_kernel_nofault((void __force *)dst, src, cnt);
89}
90
91static struct mem_access kernel_mem_access = {
92 copy_from_kernel_wrapper,
93 copy_to_kernel_wrapper,
94};
95
Linus Torvalds1da177e2005-04-16 15:20:36 -070096/*
97 * handle an instruction that does an unaligned memory access by emulating the
98 * desired behaviour
99 * - note that PC _may not_ point to the faulting instruction
100 * (if that instruction is in a branch delay slot)
101 * - return 0 if emulation okay, -EFAULT on existential error
102 */
Paul Mundt2bcfffa2009-05-09 16:02:08 +0900103static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
Magnus Damme7cc9a72008-02-07 20:18:21 +0900104 struct mem_access *ma)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105{
106 int ret, index, count;
107 unsigned long *rm, *rn;
108 unsigned char *src, *dst;
Paul Mundtfa439722008-09-04 18:53:58 +0900109 unsigned char __user *srcu, *dstu;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110
111 index = (instruction>>8)&15; /* 0x0F00 */
112 rn = &regs->regs[index];
113
114 index = (instruction>>4)&15; /* 0x00F0 */
115 rm = &regs->regs[index];
116
117 count = 1<<(instruction&3);
118
Andre Draszik7436cde2009-08-24 14:53:46 +0900119 switch (count) {
Paul Mundta99eae52010-01-12 16:12:25 +0900120 case 1: inc_unaligned_byte_access(); break;
121 case 2: inc_unaligned_word_access(); break;
122 case 4: inc_unaligned_dword_access(); break;
123 case 8: inc_unaligned_multi_access(); break;
Andre Draszik7436cde2009-08-24 14:53:46 +0900124 }
125
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126 ret = -EFAULT;
127 switch (instruction>>12) {
128 case 0: /* mov.[bwl] to/from memory via r0+rn */
129 if (instruction & 8) {
130 /* from memory */
Paul Mundtfa439722008-09-04 18:53:58 +0900131 srcu = (unsigned char __user *)*rm;
132 srcu += regs->regs[0];
133 dst = (unsigned char *)rn;
134 *(unsigned long *)dst = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135
Magnus Damm86c01792008-02-07 00:02:50 +0900136#if !defined(__LITTLE_ENDIAN__)
137 dst += 4-count;
138#endif
Paul Mundtfa439722008-09-04 18:53:58 +0900139 if (ma->from(dst, srcu, count))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140 goto fetch_fault;
141
Magnus Damm86c01792008-02-07 00:02:50 +0900142 sign_extend(count, dst);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143 } else {
144 /* to memory */
Paul Mundtfa439722008-09-04 18:53:58 +0900145 src = (unsigned char *)rm;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146#if !defined(__LITTLE_ENDIAN__)
147 src += 4-count;
148#endif
Paul Mundtfa439722008-09-04 18:53:58 +0900149 dstu = (unsigned char __user *)*rn;
150 dstu += regs->regs[0];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151
Paul Mundtfa439722008-09-04 18:53:58 +0900152 if (ma->to(dstu, src, count))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153 goto fetch_fault;
154 }
155 ret = 0;
156 break;
157
158 case 1: /* mov.l Rm,@(disp,Rn) */
159 src = (unsigned char*) rm;
Paul Mundtfa439722008-09-04 18:53:58 +0900160 dstu = (unsigned char __user *)*rn;
161 dstu += (instruction&0x000F)<<2;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700162
Paul Mundtfa439722008-09-04 18:53:58 +0900163 if (ma->to(dstu, src, 4))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700164 goto fetch_fault;
165 ret = 0;
Stuart Menefyb5a1bcb2006-11-21 13:34:04 +0900166 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167
168 case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
169 if (instruction & 4)
170 *rn -= count;
171 src = (unsigned char*) rm;
Paul Mundtfa439722008-09-04 18:53:58 +0900172 dstu = (unsigned char __user *)*rn;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700173#if !defined(__LITTLE_ENDIAN__)
174 src += 4-count;
175#endif
Paul Mundtfa439722008-09-04 18:53:58 +0900176 if (ma->to(dstu, src, count))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177 goto fetch_fault;
178 ret = 0;
179 break;
180
181 case 5: /* mov.l @(disp,Rm),Rn */
Paul Mundtfa439722008-09-04 18:53:58 +0900182 srcu = (unsigned char __user *)*rm;
183 srcu += (instruction & 0x000F) << 2;
184 dst = (unsigned char *)rn;
185 *(unsigned long *)dst = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186
Paul Mundtfa439722008-09-04 18:53:58 +0900187 if (ma->from(dst, srcu, 4))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188 goto fetch_fault;
189 ret = 0;
Stuart Menefyb5a1bcb2006-11-21 13:34:04 +0900190 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191
192 case 6: /* mov.[bwl] from memory, possibly with post-increment */
Paul Mundtfa439722008-09-04 18:53:58 +0900193 srcu = (unsigned char __user *)*rm;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194 if (instruction & 4)
195 *rm += count;
196 dst = (unsigned char*) rn;
197 *(unsigned long*)dst = 0;
Stuart Menefyb5a1bcb2006-11-21 13:34:04 +0900198
Magnus Damm86c01792008-02-07 00:02:50 +0900199#if !defined(__LITTLE_ENDIAN__)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700200 dst += 4-count;
Magnus Damm86c01792008-02-07 00:02:50 +0900201#endif
Paul Mundtfa439722008-09-04 18:53:58 +0900202 if (ma->from(dst, srcu, count))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203 goto fetch_fault;
Magnus Damm86c01792008-02-07 00:02:50 +0900204 sign_extend(count, dst);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700205 ret = 0;
206 break;
207
208 case 8:
209 switch ((instruction&0xFF00)>>8) {
210 case 0x81: /* mov.w R0,@(disp,Rn) */
Paul Mundtfa439722008-09-04 18:53:58 +0900211 src = (unsigned char *) &regs->regs[0];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700212#if !defined(__LITTLE_ENDIAN__)
213 src += 2;
214#endif
Paul Mundtfa439722008-09-04 18:53:58 +0900215 dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
216 dstu += (instruction & 0x000F) << 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217
Paul Mundtfa439722008-09-04 18:53:58 +0900218 if (ma->to(dstu, src, 2))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219 goto fetch_fault;
220 ret = 0;
221 break;
222
223 case 0x85: /* mov.w @(disp,Rm),R0 */
Paul Mundtfa439722008-09-04 18:53:58 +0900224 srcu = (unsigned char __user *)*rm;
225 srcu += (instruction & 0x000F) << 1;
226 dst = (unsigned char *) &regs->regs[0];
227 *(unsigned long *)dst = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700228
229#if !defined(__LITTLE_ENDIAN__)
230 dst += 2;
231#endif
Paul Mundtfa439722008-09-04 18:53:58 +0900232 if (ma->from(dst, srcu, 2))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233 goto fetch_fault;
Magnus Damm86c01792008-02-07 00:02:50 +0900234 sign_extend(2, dst);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235 ret = 0;
236 break;
237 }
238 break;
Phil Edworthy34f71452011-08-24 10:43:59 +0000239
240 case 9: /* mov.w @(disp,PC),Rn */
241 srcu = (unsigned char __user *)regs->pc;
242 srcu += 4;
243 srcu += (instruction & 0x00FF) << 1;
244 dst = (unsigned char *)rn;
245 *(unsigned long *)dst = 0;
246
247#if !defined(__LITTLE_ENDIAN__)
248 dst += 2;
249#endif
250
251 if (ma->from(dst, srcu, 2))
252 goto fetch_fault;
253 sign_extend(2, dst);
254 ret = 0;
255 break;
256
257 case 0xd: /* mov.l @(disp,PC),Rn */
258 srcu = (unsigned char __user *)(regs->pc & ~0x3);
259 srcu += 4;
260 srcu += (instruction & 0x00FF) << 2;
261 dst = (unsigned char *)rn;
262 *(unsigned long *)dst = 0;
263
264 if (ma->from(dst, srcu, 4))
265 goto fetch_fault;
266 ret = 0;
267 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268 }
269 return ret;
270
271 fetch_fault:
272 /* Argh. Address not only misaligned but also non-existent.
273 * Raise an EFAULT and see if it's trapped
274 */
SUGIOKA Toshinobu2afb4472009-01-21 09:42:10 +0900275 die_if_no_fixup("Fault in unaligned fixup", regs, 0);
276 return -EFAULT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700277}
278
279/*
280 * emulate the instruction in the delay slot
281 * - fetches the instruction from PC+2
282 */
Magnus Damme7cc9a72008-02-07 20:18:21 +0900283static inline int handle_delayslot(struct pt_regs *regs,
Paul Mundt2bcfffa2009-05-09 16:02:08 +0900284 insn_size_t old_instruction,
Magnus Damme7cc9a72008-02-07 20:18:21 +0900285 struct mem_access *ma)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700286{
Paul Mundt2bcfffa2009-05-09 16:02:08 +0900287 insn_size_t instruction;
Paul Mundtfa439722008-09-04 18:53:58 +0900288 void __user *addr = (void __user *)(regs->pc +
289 instruction_size(old_instruction));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700290
Magnus Damm4b5a9ef2008-02-07 20:04:12 +0900291 if (copy_from_user(&instruction, addr, sizeof(instruction))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700292 /* the instruction-fetch faulted */
293 if (user_mode(regs))
294 return -EFAULT;
295
296 /* kernel */
Stuart Menefyb5a1bcb2006-11-21 13:34:04 +0900297 die("delay-slot-insn faulting in handle_unaligned_delayslot",
298 regs, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700299 }
300
Magnus Damme7cc9a72008-02-07 20:18:21 +0900301 return handle_unaligned_ins(instruction, regs, ma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700302}
303
304/*
305 * handle an instruction that does an unaligned memory access
306 * - have to be careful of branch delay-slot instructions that fault
307 * SH3:
308 * - if the branch would be taken PC points to the branch
309 * - if the branch would not be taken, PC points to delay-slot
310 * SH4:
311 * - PC always points to delayed branch
312 * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
313 */
314
315/* Macros to determine offset from current PC for branch instructions */
316/* Explicit type coercion is used to force sign extension where needed */
317#define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
318#define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
319
Paul Mundt2bcfffa2009-05-09 16:02:08 +0900320int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
Paul Mundtace2dc72010-10-13 06:55:26 +0900321 struct mem_access *ma, int expected,
322 unsigned long address)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323{
324 u_int rm;
325 int ret, index;
326
Paul Mundt23c4c822009-09-24 17:38:18 +0900327 /*
328 * XXX: We can't handle mixed 16/32-bit instructions yet
329 */
330 if (instruction_size(instruction) != 2)
331 return -EINVAL;
332
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333 index = (instruction>>8)&15; /* 0x0F00 */
334 rm = regs->regs[index];
335
Paul Mundtace2dc72010-10-13 06:55:26 +0900336 /*
337 * Log the unexpected fixups, and then pass them on to perf.
338 *
339 * We intentionally don't report the expected cases to perf as
340 * otherwise the trapped I/O case will skew the results too much
341 * to be useful.
342 */
343 if (!expected) {
Paul Mundta99eae52010-01-12 16:12:25 +0900344 unaligned_fixups_notify(current, instruction, regs);
Peter Zijlstraa8b0ca12011-06-27 14:41:57 +0200345 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1,
Paul Mundtace2dc72010-10-13 06:55:26 +0900346 regs, address);
347 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700348
349 ret = -EFAULT;
350 switch (instruction&0xF000) {
351 case 0x0000:
352 if (instruction==0x000B) {
353 /* rts */
Magnus Damme7cc9a72008-02-07 20:18:21 +0900354 ret = handle_delayslot(regs, instruction, ma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700355 if (ret==0)
356 regs->pc = regs->pr;
357 }
358 else if ((instruction&0x00FF)==0x0023) {
359 /* braf @Rm */
Magnus Damme7cc9a72008-02-07 20:18:21 +0900360 ret = handle_delayslot(regs, instruction, ma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700361 if (ret==0)
362 regs->pc += rm + 4;
363 }
364 else if ((instruction&0x00FF)==0x0003) {
365 /* bsrf @Rm */
Magnus Damme7cc9a72008-02-07 20:18:21 +0900366 ret = handle_delayslot(regs, instruction, ma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367 if (ret==0) {
368 regs->pr = regs->pc + 4;
369 regs->pc += rm + 4;
370 }
371 }
372 else {
373 /* mov.[bwl] to/from memory via r0+rn */
374 goto simple;
375 }
376 break;
377
378 case 0x1000: /* mov.l Rm,@(disp,Rn) */
379 goto simple;
380
381 case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
382 goto simple;
383
384 case 0x4000:
385 if ((instruction&0x00FF)==0x002B) {
386 /* jmp @Rm */
Magnus Damme7cc9a72008-02-07 20:18:21 +0900387 ret = handle_delayslot(regs, instruction, ma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388 if (ret==0)
389 regs->pc = rm;
390 }
391 else if ((instruction&0x00FF)==0x000B) {
392 /* jsr @Rm */
Magnus Damme7cc9a72008-02-07 20:18:21 +0900393 ret = handle_delayslot(regs, instruction, ma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394 if (ret==0) {
395 regs->pr = regs->pc + 4;
396 regs->pc = rm;
397 }
398 }
399 else {
400 /* mov.[bwl] to/from memory via r0+rn */
401 goto simple;
402 }
403 break;
404
405 case 0x5000: /* mov.l @(disp,Rm),Rn */
406 goto simple;
407
408 case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
409 goto simple;
410
411 case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
412 switch (instruction&0x0F00) {
413 case 0x0100: /* mov.w R0,@(disp,Rm) */
414 goto simple;
415 case 0x0500: /* mov.w @(disp,Rm),R0 */
416 goto simple;
417 case 0x0B00: /* bf lab - no delayslot*/
Phil Edworthy0710b91c2011-08-22 15:56:08 +0000418 ret = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700419 break;
420 case 0x0F00: /* bf/s lab */
Magnus Damme7cc9a72008-02-07 20:18:21 +0900421 ret = handle_delayslot(regs, instruction, ma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700422 if (ret==0) {
423#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
424 if ((regs->sr & 0x00000001) != 0)
425 regs->pc += 4; /* next after slot */
426 else
427#endif
428 regs->pc += SH_PC_8BIT_OFFSET(instruction);
429 }
430 break;
431 case 0x0900: /* bt lab - no delayslot */
Phil Edworthy0710b91c2011-08-22 15:56:08 +0000432 ret = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700433 break;
434 case 0x0D00: /* bt/s lab */
Magnus Damme7cc9a72008-02-07 20:18:21 +0900435 ret = handle_delayslot(regs, instruction, ma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700436 if (ret==0) {
437#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
438 if ((regs->sr & 0x00000001) == 0)
439 regs->pc += 4; /* next after slot */
440 else
441#endif
442 regs->pc += SH_PC_8BIT_OFFSET(instruction);
443 }
444 break;
445 }
446 break;
447
Phil Edworthy34f71452011-08-24 10:43:59 +0000448 case 0x9000: /* mov.w @(disp,Rm),Rn */
449 goto simple;
450
Linus Torvalds1da177e2005-04-16 15:20:36 -0700451 case 0xA000: /* bra label */
Magnus Damme7cc9a72008-02-07 20:18:21 +0900452 ret = handle_delayslot(regs, instruction, ma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700453 if (ret==0)
454 regs->pc += SH_PC_12BIT_OFFSET(instruction);
455 break;
456
457 case 0xB000: /* bsr label */
Magnus Damme7cc9a72008-02-07 20:18:21 +0900458 ret = handle_delayslot(regs, instruction, ma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700459 if (ret==0) {
460 regs->pr = regs->pc + 4;
461 regs->pc += SH_PC_12BIT_OFFSET(instruction);
462 }
463 break;
Phil Edworthy34f71452011-08-24 10:43:59 +0000464
465 case 0xD000: /* mov.l @(disp,Rm),Rn */
466 goto simple;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700467 }
468 return ret;
469
470 /* handle non-delay-slot instruction */
471 simple:
Magnus Damme7cc9a72008-02-07 20:18:21 +0900472 ret = handle_unaligned_ins(instruction, regs, ma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473 if (ret==0)
Paul Mundt53f983a2007-05-08 15:31:48 +0900474 regs->pc += instruction_size(instruction);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700475 return ret;
476}
477
478/*
Stuart Menefyb5a1bcb2006-11-21 13:34:04 +0900479 * Handle various address error exceptions:
480 * - instruction address error:
481 * misaligned PC
482 * PC >= 0x80000000 in user mode
483 * - data address error (read and write)
484 * misaligned data access
485 * access to >= 0x80000000 is user mode
486 * Unfortuntaly we can't distinguish between instruction address error
Simon Arlotte868d612007-05-14 08:15:10 +0900487 * and data address errors caused by read accesses.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488 */
Stuart Menefyf0bc8142006-11-21 11:16:57 +0900489asmlinkage void do_address_error(struct pt_regs *regs,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700490 unsigned long writeaccess,
491 unsigned long address)
492{
Yoshinori Sato0983b312006-11-05 15:58:47 +0900493 unsigned long error_code = 0;
Paul Mundt2bcfffa2009-05-09 16:02:08 +0900494 insn_size_t instruction;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700495 int tmp;
496
Yoshinori Sato0983b312006-11-05 15:58:47 +0900497 /* Intentional ifdef */
498#ifdef CONFIG_CPU_HAS_SR_RB
Paul Mundt4c59e292008-09-21 12:00:23 +0900499 error_code = lookup_exception_vector();
Yoshinori Sato0983b312006-11-05 15:58:47 +0900500#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700501
Linus Torvalds1da177e2005-04-16 15:20:36 -0700502 if (user_mode(regs)) {
Stuart Menefyb5a1bcb2006-11-21 13:34:04 +0900503 int si_code = BUS_ADRERR;
Paul Mundta99eae52010-01-12 16:12:25 +0900504 unsigned int user_action;
Stuart Menefyb5a1bcb2006-11-21 13:34:04 +0900505
Linus Torvalds1da177e2005-04-16 15:20:36 -0700506 local_irq_enable();
Paul Mundta99eae52010-01-12 16:12:25 +0900507 inc_unaligned_user_access();
Andre Draszik7436cde2009-08-24 14:53:46 +0900508
Al Viroca42bc42020-12-31 23:23:01 +0000509 if (copy_from_user(&instruction, (insn_size_t __user *)(regs->pc & ~1),
Paul Mundt23c4c822009-09-24 17:38:18 +0900510 sizeof(instruction))) {
Andre Draszik5a0ab352009-08-24 15:01:10 +0900511 goto uspace_segv;
512 }
Andre Draszik5a0ab352009-08-24 15:01:10 +0900513
Andre Draszik7436cde2009-08-24 14:53:46 +0900514 /* shout about userspace fixups */
Paul Mundta99eae52010-01-12 16:12:25 +0900515 unaligned_fixups_notify(current, instruction, regs);
Andre Draszik7436cde2009-08-24 14:53:46 +0900516
Paul Mundta99eae52010-01-12 16:12:25 +0900517 user_action = unaligned_user_action();
518 if (user_action & UM_FIXUP)
Andre Draszik7436cde2009-08-24 14:53:46 +0900519 goto fixup;
Paul Mundta99eae52010-01-12 16:12:25 +0900520 if (user_action & UM_SIGNAL)
Andre Draszik7436cde2009-08-24 14:53:46 +0900521 goto uspace_segv;
522 else {
523 /* ignore */
Andre Draszik5a0ab352009-08-24 15:01:10 +0900524 regs->pc += instruction_size(instruction);
Andre Draszik7436cde2009-08-24 14:53:46 +0900525 return;
526 }
527
528fixup:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700529 /* bad PC is not something we can fix */
Stuart Menefyb5a1bcb2006-11-21 13:34:04 +0900530 if (regs->pc & 1) {
531 si_code = BUS_ADRALN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700532 goto uspace_segv;
Stuart Menefyb5a1bcb2006-11-21 13:34:04 +0900533 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700534
Magnus Damme7cc9a72008-02-07 20:18:21 +0900535 tmp = handle_unaligned_access(instruction, regs,
Paul Mundtace2dc72010-10-13 06:55:26 +0900536 &user_mem_access, 0,
537 address);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700538
Paul Mundta99eae52010-01-12 16:12:25 +0900539 if (tmp == 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700540 return; /* sorted */
Stuart Menefyb5a1bcb2006-11-21 13:34:04 +0900541uspace_segv:
542 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
543 "access (PC %lx PR %lx)\n", current->comm, regs->pc,
544 regs->pr);
545
Eric W. Biederman2e1661d22019-05-23 11:04:24 -0500546 force_sig_fault(SIGBUS, si_code, (void __user *)address);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700547 } else {
Paul Mundta99eae52010-01-12 16:12:25 +0900548 inc_unaligned_kernel_access();
Andre Draszik7436cde2009-08-24 14:53:46 +0900549
Linus Torvalds1da177e2005-04-16 15:20:36 -0700550 if (regs->pc & 1)
551 die("unaligned program counter", regs, error_code);
552
Arnd Bergmann75d4d292022-02-11 17:26:42 +0100553 if (copy_from_kernel_nofault(&instruction, (void *)(regs->pc),
Magnus Damm4b5a9ef2008-02-07 20:04:12 +0900554 sizeof(instruction))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700555 /* Argh. Fault on the instruction itself.
556 This should never happen non-SMP
557 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700558 die("insn faulting in do_address_error", regs, 0);
559 }
560
Paul Mundta99eae52010-01-12 16:12:25 +0900561 unaligned_fixups_notify(current, instruction, regs);
Paul Mundt40258ee2009-09-24 17:48:15 +0900562
Arnd Bergmann75d4d292022-02-11 17:26:42 +0100563 handle_unaligned_access(instruction, regs, &kernel_mem_access,
Paul Mundtace2dc72010-10-13 06:55:26 +0900564 0, address);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565 }
566}
567
568#ifdef CONFIG_SH_DSP
569/*
570 * SH-DSP support gerg@snapgear.com.
571 */
Geert Uytterhoevenfdb2dd72024-03-04 20:10:44 +0100572static int is_dsp_inst(struct pt_regs *regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700573{
Paul Mundt882c12c2007-05-14 17:26:34 +0900574 unsigned short inst = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700575
Stuart Menefyf0bc8142006-11-21 11:16:57 +0900576 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700577 * Safe guard if DSP mode is already enabled or we're lacking
578 * the DSP altogether.
579 */
Paul Mundt11c19652006-12-25 10:19:56 +0900580 if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700581 return 0;
582
583 get_user(inst, ((unsigned short *) regs->pc));
584
585 inst &= 0xf000;
586
587 /* Check for any type of DSP or support instruction */
588 if ((inst == 0xf000) || (inst == 0x4000))
589 return 1;
590
591 return 0;
592}
593#else
Geert Uytterhoevenfdb2dd72024-03-04 20:10:44 +0100594static inline int is_dsp_inst(struct pt_regs *regs) { return 0; }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700595#endif /* CONFIG_SH_DSP */
596
Yoshinori Sato0983b312006-11-05 15:58:47 +0900597#ifdef CONFIG_CPU_SH2A
Bobby Binghama3c19512014-04-03 14:46:41 -0700598asmlinkage void do_divide_error(unsigned long r4)
Yoshinori Sato0983b312006-11-05 15:58:47 +0900599{
Eric W. Biedermanc65626c2018-04-15 19:56:33 -0500600 int code;
Yoshinori Sato0983b312006-11-05 15:58:47 +0900601
Yoshinori Sato0983b312006-11-05 15:58:47 +0900602 switch (r4) {
603 case TRAP_DIVZERO_ERROR:
Eric W. Biedermanc65626c2018-04-15 19:56:33 -0500604 code = FPE_INTDIV;
Yoshinori Sato0983b312006-11-05 15:58:47 +0900605 break;
606 case TRAP_DIVOVF_ERROR:
Eric W. Biedermanc65626c2018-04-15 19:56:33 -0500607 code = FPE_INTOVF;
Yoshinori Sato0983b312006-11-05 15:58:47 +0900608 break;
Eric W. Biederman26da3502018-05-29 09:40:11 -0500609 default:
610 /* Let gcc know unhandled cases don't make it past here */
611 return;
Yoshinori Sato0983b312006-11-05 15:58:47 +0900612 }
Eric W. Biederman2e1661d22019-05-23 11:04:24 -0500613 force_sig_fault(SIGFPE, code, NULL);
Yoshinori Sato0983b312006-11-05 15:58:47 +0900614}
615#endif
616
Bobby Binghama3c19512014-04-03 14:46:41 -0700617asmlinkage void do_reserved_inst(void)
Takashi YOSHII4b565682006-09-27 17:15:32 +0900618{
Bobby Binghama3c19512014-04-03 14:46:41 -0700619 struct pt_regs *regs = current_pt_regs();
Takashi YOSHII4b565682006-09-27 17:15:32 +0900620 unsigned long error_code;
Takashi YOSHII4b565682006-09-27 17:15:32 +0900621
622#ifdef CONFIG_SH_FPU_EMU
Yoshinori Sato0983b312006-11-05 15:58:47 +0900623 unsigned short inst = 0;
Takashi YOSHII4b565682006-09-27 17:15:32 +0900624 int err;
625
Al Viroca42bc42020-12-31 23:23:01 +0000626 get_user(inst, (unsigned short __user *)regs->pc);
Takashi YOSHII4b565682006-09-27 17:15:32 +0900627
Stuart Menefyf0bc8142006-11-21 11:16:57 +0900628 err = do_fpu_inst(inst, regs);
Takashi YOSHII4b565682006-09-27 17:15:32 +0900629 if (!err) {
Paul Mundt53f983a2007-05-08 15:31:48 +0900630 regs->pc += instruction_size(inst);
Takashi YOSHII4b565682006-09-27 17:15:32 +0900631 return;
632 }
633 /* not a FPU inst. */
634#endif
635
636#ifdef CONFIG_SH_DSP
637 /* Check if it's a DSP instruction */
Stuart Menefyb5a1bcb2006-11-21 13:34:04 +0900638 if (is_dsp_inst(regs)) {
Takashi YOSHII4b565682006-09-27 17:15:32 +0900639 /* Enable DSP mode, and restart instruction. */
Stuart Menefyf0bc8142006-11-21 11:16:57 +0900640 regs->sr |= SR_DSP;
Michael Trimarchi01ab1032009-04-03 17:32:33 +0000641 /* Save DSP mode */
Eric W. Biederman3cf5d072019-05-23 10:17:27 -0500642 current->thread.dsp_status.status |= SR_DSP;
Takashi YOSHII4b565682006-09-27 17:15:32 +0900643 return;
644 }
645#endif
646
Paul Mundt4c59e292008-09-21 12:00:23 +0900647 error_code = lookup_exception_vector();
Yoshinori Sato0983b312006-11-05 15:58:47 +0900648
Takashi YOSHII4b565682006-09-27 17:15:32 +0900649 local_irq_enable();
Eric W. Biederman3cf5d072019-05-23 10:17:27 -0500650 force_sig(SIGILL);
Stuart Menefyf0bc8142006-11-21 11:16:57 +0900651 die_if_no_fixup("reserved instruction", regs, error_code);
Takashi YOSHII4b565682006-09-27 17:15:32 +0900652}
653
654#ifdef CONFIG_SH_FPU_EMU
Paul Mundtedfd6da2008-11-26 13:06:04 +0900655static int emulate_branch(unsigned short inst, struct pt_regs *regs)
Takashi YOSHII4b565682006-09-27 17:15:32 +0900656{
657 /*
658 * bfs: 8fxx: PC+=d*2+4;
659 * bts: 8dxx: PC+=d*2+4;
660 * bra: axxx: PC+=D*2+4;
661 * bsr: bxxx: PC+=D*2+4 after PR=PC+4;
662 * braf:0x23: PC+=Rn*2+4;
663 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
664 * jmp: 4x2b: PC=Rn;
665 * jsr: 4x0b: PC=Rn after PR=PC+4;
666 * rts: 000b: PC=PR;
667 */
Paul Mundtedfd6da2008-11-26 13:06:04 +0900668 if (((inst & 0xf000) == 0xb000) || /* bsr */
669 ((inst & 0xf0ff) == 0x0003) || /* bsrf */
670 ((inst & 0xf0ff) == 0x400b)) /* jsr */
671 regs->pr = regs->pc + 4;
672
673 if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */
Takashi YOSHII4b565682006-09-27 17:15:32 +0900674 regs->pc += SH_PC_8BIT_OFFSET(inst);
675 return 0;
676 }
677
Paul Mundtedfd6da2008-11-26 13:06:04 +0900678 if ((inst & 0xe000) == 0xa000) { /* bra, bsr */
Takashi YOSHII4b565682006-09-27 17:15:32 +0900679 regs->pc += SH_PC_12BIT_OFFSET(inst);
680 return 0;
681 }
682
Paul Mundtedfd6da2008-11-26 13:06:04 +0900683 if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */
Takashi YOSHII4b565682006-09-27 17:15:32 +0900684 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
685 return 0;
686 }
687
Paul Mundtedfd6da2008-11-26 13:06:04 +0900688 if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */
Takashi YOSHII4b565682006-09-27 17:15:32 +0900689 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
690 return 0;
691 }
692
Paul Mundtedfd6da2008-11-26 13:06:04 +0900693 if ((inst & 0xffff) == 0x000b) { /* rts */
Takashi YOSHII4b565682006-09-27 17:15:32 +0900694 regs->pc = regs->pr;
695 return 0;
696 }
697
698 return 1;
699}
700#endif
701
Bobby Binghama3c19512014-04-03 14:46:41 -0700702asmlinkage void do_illegal_slot_inst(void)
Takashi YOSHII4b565682006-09-27 17:15:32 +0900703{
Bobby Binghama3c19512014-04-03 14:46:41 -0700704 struct pt_regs *regs = current_pt_regs();
Paul Mundtb3d765f2008-09-17 23:12:11 +0900705 unsigned long inst;
Chris Smithd39f5452008-09-05 17:15:39 +0900706
707 if (kprobe_handle_illslot(regs->pc) == 0)
708 return;
709
Takashi YOSHII4b565682006-09-27 17:15:32 +0900710#ifdef CONFIG_SH_FPU_EMU
Al Viroca42bc42020-12-31 23:23:01 +0000711 get_user(inst, (unsigned short __user *)regs->pc + 1);
Stuart Menefyf0bc8142006-11-21 11:16:57 +0900712 if (!do_fpu_inst(inst, regs)) {
Al Viroca42bc42020-12-31 23:23:01 +0000713 get_user(inst, (unsigned short __user *)regs->pc);
Stuart Menefyf0bc8142006-11-21 11:16:57 +0900714 if (!emulate_branch(inst, regs))
Takashi YOSHII4b565682006-09-27 17:15:32 +0900715 return;
716 /* fault in branch.*/
717 }
718 /* not a FPU inst. */
719#endif
720
Paul Mundt4c59e292008-09-21 12:00:23 +0900721 inst = lookup_exception_vector();
Yoshinori Sato0983b312006-11-05 15:58:47 +0900722
Takashi YOSHII4b565682006-09-27 17:15:32 +0900723 local_irq_enable();
Eric W. Biederman3cf5d072019-05-23 10:17:27 -0500724 force_sig(SIGILL);
Paul Mundtb3d765f2008-09-17 23:12:11 +0900725 die_if_no_fixup("illegal slot instruction", regs, inst);
Takashi YOSHII4b565682006-09-27 17:15:32 +0900726}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700727
Bobby Binghama3c19512014-04-03 14:46:41 -0700728asmlinkage void do_exception_error(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700729{
730 long ex;
Yoshinori Sato0983b312006-11-05 15:58:47 +0900731
Paul Mundt4c59e292008-09-21 12:00:23 +0900732 ex = lookup_exception_vector();
Bobby Binghama3c19512014-04-03 14:46:41 -0700733 die_if_kernel("exception", current_pt_regs(), ex);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700734}
735
Paul Gortmaker4603f532013-06-18 17:10:12 -0400736void per_cpu_trap_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700737{
738 extern void *vbr_base;
739
Linus Torvalds1da177e2005-04-16 15:20:36 -0700740 /* NOTE: The VBR value should be at P1
741 (or P2, virtural "fixed" address space).
742 It's definitely should not in physical address. */
743
744 asm volatile("ldc %0, vbr"
745 : /* no output */
746 : "r" (&vbr_base)
747 : "memory");
Magnus Damm68a1aed2010-09-24 09:05:38 +0000748
749 /* disable exception blocking now when the vbr has been setup */
750 clear_bl_bit();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700751}
752
Paul Mundt1f666582006-10-19 16:20:25 +0900753void *set_exception_table_vec(unsigned int vec, void *handler)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700754{
755 extern void *exception_handling_table[];
Paul Mundt1f666582006-10-19 16:20:25 +0900756 void *old_handler;
Stuart Menefyb5a1bcb2006-11-21 13:34:04 +0900757
Paul Mundt1f666582006-10-19 16:20:25 +0900758 old_handler = exception_handling_table[vec];
759 exception_handling_table[vec] = handler;
760 return old_handler;
761}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700762
Paul Mundt1f666582006-10-19 16:20:25 +0900763void __init trap_init(void)
764{
765 set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
766 set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700767
Takashi YOSHII4b565682006-09-27 17:15:32 +0900768#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
769 defined(CONFIG_SH_FPU_EMU)
770 /*
771 * For SH-4 lacking an FPU, treat floating point instructions as
772 * reserved. They'll be handled in the math-emu case, or faulted on
773 * otherwise.
774 */
Paul Mundt1f666582006-10-19 16:20:25 +0900775 set_exception_table_evt(0x800, do_reserved_inst);
776 set_exception_table_evt(0x820, do_illegal_slot_inst);
777#elif defined(CONFIG_SH_FPU)
Paul Mundt74d99a52007-11-26 20:38:36 +0900778 set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
779 set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700780#endif
Yoshinori Sato0983b312006-11-05 15:58:47 +0900781
782#ifdef CONFIG_CPU_SH2
Paul Mundt5a4f7c62007-11-20 18:08:06 +0900783 set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
Yoshinori Sato0983b312006-11-05 15:58:47 +0900784#endif
785#ifdef CONFIG_CPU_SH2A
786 set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
787 set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
Yoshinori Sato6e80f5e2008-07-10 01:20:03 +0900788#ifdef CONFIG_SH_FPU
789 set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
790#endif
Yoshinori Sato0983b312006-11-05 15:58:47 +0900791#endif
Stuart Menefyb5a1bcb2006-11-21 13:34:04 +0900792
Peter Griffincd894362009-05-08 15:51:51 +0100793#ifdef TRAP_UBC
Paul Mundtc4761812010-01-05 12:44:02 +0900794 set_exception_table_vec(TRAP_UBC, breakpoint_trap_handler);
Peter Griffincd894362009-05-08 15:51:51 +0100795#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700796}