Kuninori Morimoto | 5933f6d | 2018-12-28 00:32:24 -0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Paul Mundt | 6b00223 | 2006-10-12 17:07:45 +0900 | [diff] [blame] | 2 | /* |
| 3 | * 'traps.c' handles hardware traps and faults after we have saved some |
| 4 | * state in 'entry.S'. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * |
| 6 | * SuperH version: Copyright (C) 1999 Niibe Yutaka |
| 7 | * Copyright (C) 2000 Philipp Rumpf |
| 8 | * Copyright (C) 2000 David Howells |
Paul Mundt | ace2dc7 | 2010-10-13 06:55:26 +0900 | [diff] [blame] | 9 | * Copyright (C) 2002 - 2010 Paul Mundt |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11 | #include <linux/kernel.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12 | #include <linux/ptrace.h> |
Russell King | ba84be2 | 2009-01-06 14:41:07 -0800 | [diff] [blame] | 13 | #include <linux/hardirq.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | #include <linux/init.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 | #include <linux/spinlock.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | #include <linux/kallsyms.h> |
Paul Mundt | 1f66658 | 2006-10-19 16:20:25 +0900 | [diff] [blame] | 17 | #include <linux/io.h> |
Paul Mundt | fa69151 | 2007-03-08 19:41:21 +0900 | [diff] [blame] | 18 | #include <linux/bug.h> |
Paul Mundt | 9b8c90e | 2006-12-06 11:07:51 +0900 | [diff] [blame] | 19 | #include <linux/debug_locks.h> |
Paul Mundt | b118ca5 | 2007-05-09 10:55:38 +0900 | [diff] [blame] | 20 | #include <linux/kdebug.h> |
Paul Mundt | dc34d31 | 2006-12-08 17:41:43 +0900 | [diff] [blame] | 21 | #include <linux/limits.h> |
Paul Mundt | af67c3a | 2009-10-13 10:57:52 +0900 | [diff] [blame] | 22 | #include <linux/sysfs.h> |
Paul Mundt | a99eae5 | 2010-01-12 16:12:25 +0900 | [diff] [blame] | 23 | #include <linux/uaccess.h> |
Paul Mundt | ace2dc7 | 2010-10-13 06:55:26 +0900 | [diff] [blame] | 24 | #include <linux/perf_event.h> |
Ingo Molnar | 68db0cf | 2017-02-08 18:51:37 +0100 | [diff] [blame] | 25 | #include <linux/sched/task_stack.h> |
| 26 | |
Paul Mundt | a99eae5 | 2010-01-12 16:12:25 +0900 | [diff] [blame] | 27 | #include <asm/alignment.h> |
Andrew Morton | fad0f90 | 2008-04-16 02:03:51 +0900 | [diff] [blame] | 28 | #include <asm/fpu.h> |
Chris Smith | d39f545 | 2008-09-05 17:15:39 +0900 | [diff] [blame] | 29 | #include <asm/kprobes.h> |
Geert Uytterhoeven | 86a2da4 | 2024-03-01 22:02:20 +0100 | [diff] [blame] | 30 | #include <asm/setup.h> |
David Howells | e839ca5 | 2012-03-28 18:30:03 +0100 | [diff] [blame] | 31 | #include <asm/traps.h> |
| 32 | #include <asm/bl_bit.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 33 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | #ifdef CONFIG_CPU_SH2 |
Yoshinori Sato | 0983b31 | 2006-11-05 15:58:47 +0900 | [diff] [blame] | 35 | # define TRAP_RESERVED_INST 4 |
| 36 | # define TRAP_ILLEGAL_SLOT_INST 6 |
| 37 | # define TRAP_ADDRESS_ERROR 9 |
| 38 | # ifdef CONFIG_CPU_SH2A |
Peter Griffin | cd89436 | 2009-05-08 15:51:51 +0100 | [diff] [blame] | 39 | # define TRAP_UBC 12 |
Yoshinori Sato | 6e80f5e | 2008-07-10 01:20:03 +0900 | [diff] [blame] | 40 | # define TRAP_FPU_ERROR 13 |
Yoshinori Sato | 0983b31 | 2006-11-05 15:58:47 +0900 | [diff] [blame] | 41 | # define TRAP_DIVZERO_ERROR 17 |
| 42 | # define TRAP_DIVOVF_ERROR 18 |
| 43 | # endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | #else |
| 45 | #define TRAP_RESERVED_INST 12 |
| 46 | #define TRAP_ILLEGAL_SLOT_INST 13 |
| 47 | #endif |
| 48 | |
Magnus Damm | 86c0179 | 2008-02-07 00:02:50 +0900 | [diff] [blame] | 49 | static inline void sign_extend(unsigned int count, unsigned char *dst) |
| 50 | { |
| 51 | #ifdef __LITTLE_ENDIAN__ |
Magnus Damm | 4252c65 | 2008-02-07 19:58:46 +0900 | [diff] [blame] | 52 | if ((count == 1) && dst[0] & 0x80) { |
| 53 | dst[1] = 0xff; |
| 54 | dst[2] = 0xff; |
| 55 | dst[3] = 0xff; |
| 56 | } |
Magnus Damm | 86c0179 | 2008-02-07 00:02:50 +0900 | [diff] [blame] | 57 | if ((count == 2) && dst[1] & 0x80) { |
| 58 | dst[2] = 0xff; |
| 59 | dst[3] = 0xff; |
| 60 | } |
| 61 | #else |
Magnus Damm | 4252c65 | 2008-02-07 19:58:46 +0900 | [diff] [blame] | 62 | if ((count == 1) && dst[3] & 0x80) { |
| 63 | dst[2] = 0xff; |
Magnus Damm | 86c0179 | 2008-02-07 00:02:50 +0900 | [diff] [blame] | 64 | dst[1] = 0xff; |
Magnus Damm | 4252c65 | 2008-02-07 19:58:46 +0900 | [diff] [blame] | 65 | dst[0] = 0xff; |
| 66 | } |
| 67 | if ((count == 2) && dst[2] & 0x80) { |
| 68 | dst[1] = 0xff; |
| 69 | dst[0] = 0xff; |
Magnus Damm | 86c0179 | 2008-02-07 00:02:50 +0900 | [diff] [blame] | 70 | } |
| 71 | #endif |
| 72 | } |
| 73 | |
Magnus Damm | e7cc9a7 | 2008-02-07 20:18:21 +0900 | [diff] [blame] | 74 | static struct mem_access user_mem_access = { |
| 75 | copy_from_user, |
| 76 | copy_to_user, |
| 77 | }; |
| 78 | |
Arnd Bergmann | 75d4d29 | 2022-02-11 17:26:42 +0100 | [diff] [blame] | 79 | static unsigned long copy_from_kernel_wrapper(void *dst, const void __user *src, |
| 80 | unsigned long cnt) |
| 81 | { |
| 82 | return copy_from_kernel_nofault(dst, (const void __force *)src, cnt); |
| 83 | } |
| 84 | |
| 85 | static unsigned long copy_to_kernel_wrapper(void __user *dst, const void *src, |
| 86 | unsigned long cnt) |
| 87 | { |
| 88 | return copy_to_kernel_nofault((void __force *)dst, src, cnt); |
| 89 | } |
| 90 | |
| 91 | static struct mem_access kernel_mem_access = { |
| 92 | copy_from_kernel_wrapper, |
| 93 | copy_to_kernel_wrapper, |
| 94 | }; |
| 95 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 96 | /* |
| 97 | * handle an instruction that does an unaligned memory access by emulating the |
| 98 | * desired behaviour |
| 99 | * - note that PC _may not_ point to the faulting instruction |
| 100 | * (if that instruction is in a branch delay slot) |
| 101 | * - return 0 if emulation okay, -EFAULT on existential error |
| 102 | */ |
Paul Mundt | 2bcfffa | 2009-05-09 16:02:08 +0900 | [diff] [blame] | 103 | static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs, |
Magnus Damm | e7cc9a7 | 2008-02-07 20:18:21 +0900 | [diff] [blame] | 104 | struct mem_access *ma) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 105 | { |
| 106 | int ret, index, count; |
| 107 | unsigned long *rm, *rn; |
| 108 | unsigned char *src, *dst; |
Paul Mundt | fa43972 | 2008-09-04 18:53:58 +0900 | [diff] [blame] | 109 | unsigned char __user *srcu, *dstu; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 110 | |
| 111 | index = (instruction>>8)&15; /* 0x0F00 */ |
| 112 | rn = ®s->regs[index]; |
| 113 | |
| 114 | index = (instruction>>4)&15; /* 0x00F0 */ |
| 115 | rm = ®s->regs[index]; |
| 116 | |
| 117 | count = 1<<(instruction&3); |
| 118 | |
Andre Draszik | 7436cde | 2009-08-24 14:53:46 +0900 | [diff] [blame] | 119 | switch (count) { |
Paul Mundt | a99eae5 | 2010-01-12 16:12:25 +0900 | [diff] [blame] | 120 | case 1: inc_unaligned_byte_access(); break; |
| 121 | case 2: inc_unaligned_word_access(); break; |
| 122 | case 4: inc_unaligned_dword_access(); break; |
| 123 | case 8: inc_unaligned_multi_access(); break; |
Andre Draszik | 7436cde | 2009-08-24 14:53:46 +0900 | [diff] [blame] | 124 | } |
| 125 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 126 | ret = -EFAULT; |
| 127 | switch (instruction>>12) { |
| 128 | case 0: /* mov.[bwl] to/from memory via r0+rn */ |
| 129 | if (instruction & 8) { |
| 130 | /* from memory */ |
Paul Mundt | fa43972 | 2008-09-04 18:53:58 +0900 | [diff] [blame] | 131 | srcu = (unsigned char __user *)*rm; |
| 132 | srcu += regs->regs[0]; |
| 133 | dst = (unsigned char *)rn; |
| 134 | *(unsigned long *)dst = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 135 | |
Magnus Damm | 86c0179 | 2008-02-07 00:02:50 +0900 | [diff] [blame] | 136 | #if !defined(__LITTLE_ENDIAN__) |
| 137 | dst += 4-count; |
| 138 | #endif |
Paul Mundt | fa43972 | 2008-09-04 18:53:58 +0900 | [diff] [blame] | 139 | if (ma->from(dst, srcu, count)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 140 | goto fetch_fault; |
| 141 | |
Magnus Damm | 86c0179 | 2008-02-07 00:02:50 +0900 | [diff] [blame] | 142 | sign_extend(count, dst); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 143 | } else { |
| 144 | /* to memory */ |
Paul Mundt | fa43972 | 2008-09-04 18:53:58 +0900 | [diff] [blame] | 145 | src = (unsigned char *)rm; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 146 | #if !defined(__LITTLE_ENDIAN__) |
| 147 | src += 4-count; |
| 148 | #endif |
Paul Mundt | fa43972 | 2008-09-04 18:53:58 +0900 | [diff] [blame] | 149 | dstu = (unsigned char __user *)*rn; |
| 150 | dstu += regs->regs[0]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 151 | |
Paul Mundt | fa43972 | 2008-09-04 18:53:58 +0900 | [diff] [blame] | 152 | if (ma->to(dstu, src, count)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 153 | goto fetch_fault; |
| 154 | } |
| 155 | ret = 0; |
| 156 | break; |
| 157 | |
| 158 | case 1: /* mov.l Rm,@(disp,Rn) */ |
| 159 | src = (unsigned char*) rm; |
Paul Mundt | fa43972 | 2008-09-04 18:53:58 +0900 | [diff] [blame] | 160 | dstu = (unsigned char __user *)*rn; |
| 161 | dstu += (instruction&0x000F)<<2; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 162 | |
Paul Mundt | fa43972 | 2008-09-04 18:53:58 +0900 | [diff] [blame] | 163 | if (ma->to(dstu, src, 4)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | goto fetch_fault; |
| 165 | ret = 0; |
Stuart Menefy | b5a1bcb | 2006-11-21 13:34:04 +0900 | [diff] [blame] | 166 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 167 | |
| 168 | case 2: /* mov.[bwl] to memory, possibly with pre-decrement */ |
| 169 | if (instruction & 4) |
| 170 | *rn -= count; |
| 171 | src = (unsigned char*) rm; |
Paul Mundt | fa43972 | 2008-09-04 18:53:58 +0900 | [diff] [blame] | 172 | dstu = (unsigned char __user *)*rn; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 173 | #if !defined(__LITTLE_ENDIAN__) |
| 174 | src += 4-count; |
| 175 | #endif |
Paul Mundt | fa43972 | 2008-09-04 18:53:58 +0900 | [diff] [blame] | 176 | if (ma->to(dstu, src, count)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 177 | goto fetch_fault; |
| 178 | ret = 0; |
| 179 | break; |
| 180 | |
| 181 | case 5: /* mov.l @(disp,Rm),Rn */ |
Paul Mundt | fa43972 | 2008-09-04 18:53:58 +0900 | [diff] [blame] | 182 | srcu = (unsigned char __user *)*rm; |
| 183 | srcu += (instruction & 0x000F) << 2; |
| 184 | dst = (unsigned char *)rn; |
| 185 | *(unsigned long *)dst = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 186 | |
Paul Mundt | fa43972 | 2008-09-04 18:53:58 +0900 | [diff] [blame] | 187 | if (ma->from(dst, srcu, 4)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 188 | goto fetch_fault; |
| 189 | ret = 0; |
Stuart Menefy | b5a1bcb | 2006-11-21 13:34:04 +0900 | [diff] [blame] | 190 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 191 | |
| 192 | case 6: /* mov.[bwl] from memory, possibly with post-increment */ |
Paul Mundt | fa43972 | 2008-09-04 18:53:58 +0900 | [diff] [blame] | 193 | srcu = (unsigned char __user *)*rm; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 194 | if (instruction & 4) |
| 195 | *rm += count; |
| 196 | dst = (unsigned char*) rn; |
| 197 | *(unsigned long*)dst = 0; |
Stuart Menefy | b5a1bcb | 2006-11-21 13:34:04 +0900 | [diff] [blame] | 198 | |
Magnus Damm | 86c0179 | 2008-02-07 00:02:50 +0900 | [diff] [blame] | 199 | #if !defined(__LITTLE_ENDIAN__) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 200 | dst += 4-count; |
Magnus Damm | 86c0179 | 2008-02-07 00:02:50 +0900 | [diff] [blame] | 201 | #endif |
Paul Mundt | fa43972 | 2008-09-04 18:53:58 +0900 | [diff] [blame] | 202 | if (ma->from(dst, srcu, count)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 203 | goto fetch_fault; |
Magnus Damm | 86c0179 | 2008-02-07 00:02:50 +0900 | [diff] [blame] | 204 | sign_extend(count, dst); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 205 | ret = 0; |
| 206 | break; |
| 207 | |
| 208 | case 8: |
| 209 | switch ((instruction&0xFF00)>>8) { |
| 210 | case 0x81: /* mov.w R0,@(disp,Rn) */ |
Paul Mundt | fa43972 | 2008-09-04 18:53:58 +0900 | [diff] [blame] | 211 | src = (unsigned char *) ®s->regs[0]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 212 | #if !defined(__LITTLE_ENDIAN__) |
| 213 | src += 2; |
| 214 | #endif |
Paul Mundt | fa43972 | 2008-09-04 18:53:58 +0900 | [diff] [blame] | 215 | dstu = (unsigned char __user *)*rm; /* called Rn in the spec */ |
| 216 | dstu += (instruction & 0x000F) << 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 217 | |
Paul Mundt | fa43972 | 2008-09-04 18:53:58 +0900 | [diff] [blame] | 218 | if (ma->to(dstu, src, 2)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 219 | goto fetch_fault; |
| 220 | ret = 0; |
| 221 | break; |
| 222 | |
| 223 | case 0x85: /* mov.w @(disp,Rm),R0 */ |
Paul Mundt | fa43972 | 2008-09-04 18:53:58 +0900 | [diff] [blame] | 224 | srcu = (unsigned char __user *)*rm; |
| 225 | srcu += (instruction & 0x000F) << 1; |
| 226 | dst = (unsigned char *) ®s->regs[0]; |
| 227 | *(unsigned long *)dst = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 228 | |
| 229 | #if !defined(__LITTLE_ENDIAN__) |
| 230 | dst += 2; |
| 231 | #endif |
Paul Mundt | fa43972 | 2008-09-04 18:53:58 +0900 | [diff] [blame] | 232 | if (ma->from(dst, srcu, 2)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 233 | goto fetch_fault; |
Magnus Damm | 86c0179 | 2008-02-07 00:02:50 +0900 | [diff] [blame] | 234 | sign_extend(2, dst); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 235 | ret = 0; |
| 236 | break; |
| 237 | } |
| 238 | break; |
Phil Edworthy | 34f7145 | 2011-08-24 10:43:59 +0000 | [diff] [blame] | 239 | |
| 240 | case 9: /* mov.w @(disp,PC),Rn */ |
| 241 | srcu = (unsigned char __user *)regs->pc; |
| 242 | srcu += 4; |
| 243 | srcu += (instruction & 0x00FF) << 1; |
| 244 | dst = (unsigned char *)rn; |
| 245 | *(unsigned long *)dst = 0; |
| 246 | |
| 247 | #if !defined(__LITTLE_ENDIAN__) |
| 248 | dst += 2; |
| 249 | #endif |
| 250 | |
| 251 | if (ma->from(dst, srcu, 2)) |
| 252 | goto fetch_fault; |
| 253 | sign_extend(2, dst); |
| 254 | ret = 0; |
| 255 | break; |
| 256 | |
| 257 | case 0xd: /* mov.l @(disp,PC),Rn */ |
| 258 | srcu = (unsigned char __user *)(regs->pc & ~0x3); |
| 259 | srcu += 4; |
| 260 | srcu += (instruction & 0x00FF) << 2; |
| 261 | dst = (unsigned char *)rn; |
| 262 | *(unsigned long *)dst = 0; |
| 263 | |
| 264 | if (ma->from(dst, srcu, 4)) |
| 265 | goto fetch_fault; |
| 266 | ret = 0; |
| 267 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 268 | } |
| 269 | return ret; |
| 270 | |
| 271 | fetch_fault: |
| 272 | /* Argh. Address not only misaligned but also non-existent. |
| 273 | * Raise an EFAULT and see if it's trapped |
| 274 | */ |
SUGIOKA Toshinobu | 2afb447 | 2009-01-21 09:42:10 +0900 | [diff] [blame] | 275 | die_if_no_fixup("Fault in unaligned fixup", regs, 0); |
| 276 | return -EFAULT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 277 | } |
| 278 | |
| 279 | /* |
| 280 | * emulate the instruction in the delay slot |
| 281 | * - fetches the instruction from PC+2 |
| 282 | */ |
Magnus Damm | e7cc9a7 | 2008-02-07 20:18:21 +0900 | [diff] [blame] | 283 | static inline int handle_delayslot(struct pt_regs *regs, |
Paul Mundt | 2bcfffa | 2009-05-09 16:02:08 +0900 | [diff] [blame] | 284 | insn_size_t old_instruction, |
Magnus Damm | e7cc9a7 | 2008-02-07 20:18:21 +0900 | [diff] [blame] | 285 | struct mem_access *ma) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 286 | { |
Paul Mundt | 2bcfffa | 2009-05-09 16:02:08 +0900 | [diff] [blame] | 287 | insn_size_t instruction; |
Paul Mundt | fa43972 | 2008-09-04 18:53:58 +0900 | [diff] [blame] | 288 | void __user *addr = (void __user *)(regs->pc + |
| 289 | instruction_size(old_instruction)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 290 | |
Magnus Damm | 4b5a9ef | 2008-02-07 20:04:12 +0900 | [diff] [blame] | 291 | if (copy_from_user(&instruction, addr, sizeof(instruction))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 292 | /* the instruction-fetch faulted */ |
| 293 | if (user_mode(regs)) |
| 294 | return -EFAULT; |
| 295 | |
| 296 | /* kernel */ |
Stuart Menefy | b5a1bcb | 2006-11-21 13:34:04 +0900 | [diff] [blame] | 297 | die("delay-slot-insn faulting in handle_unaligned_delayslot", |
| 298 | regs, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 299 | } |
| 300 | |
Magnus Damm | e7cc9a7 | 2008-02-07 20:18:21 +0900 | [diff] [blame] | 301 | return handle_unaligned_ins(instruction, regs, ma); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 302 | } |
| 303 | |
| 304 | /* |
| 305 | * handle an instruction that does an unaligned memory access |
| 306 | * - have to be careful of branch delay-slot instructions that fault |
| 307 | * SH3: |
| 308 | * - if the branch would be taken PC points to the branch |
| 309 | * - if the branch would not be taken, PC points to delay-slot |
| 310 | * SH4: |
| 311 | * - PC always points to delayed branch |
| 312 | * - return 0 if handled, -EFAULT if failed (may not return if in kernel) |
| 313 | */ |
| 314 | |
| 315 | /* Macros to determine offset from current PC for branch instructions */ |
| 316 | /* Explicit type coercion is used to force sign extension where needed */ |
| 317 | #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4) |
| 318 | #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4) |
| 319 | |
Paul Mundt | 2bcfffa | 2009-05-09 16:02:08 +0900 | [diff] [blame] | 320 | int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, |
Paul Mundt | ace2dc7 | 2010-10-13 06:55:26 +0900 | [diff] [blame] | 321 | struct mem_access *ma, int expected, |
| 322 | unsigned long address) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 323 | { |
| 324 | u_int rm; |
| 325 | int ret, index; |
| 326 | |
Paul Mundt | 23c4c82 | 2009-09-24 17:38:18 +0900 | [diff] [blame] | 327 | /* |
| 328 | * XXX: We can't handle mixed 16/32-bit instructions yet |
| 329 | */ |
| 330 | if (instruction_size(instruction) != 2) |
| 331 | return -EINVAL; |
| 332 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 333 | index = (instruction>>8)&15; /* 0x0F00 */ |
| 334 | rm = regs->regs[index]; |
| 335 | |
Paul Mundt | ace2dc7 | 2010-10-13 06:55:26 +0900 | [diff] [blame] | 336 | /* |
| 337 | * Log the unexpected fixups, and then pass them on to perf. |
| 338 | * |
| 339 | * We intentionally don't report the expected cases to perf as |
| 340 | * otherwise the trapped I/O case will skew the results too much |
| 341 | * to be useful. |
| 342 | */ |
| 343 | if (!expected) { |
Paul Mundt | a99eae5 | 2010-01-12 16:12:25 +0900 | [diff] [blame] | 344 | unaligned_fixups_notify(current, instruction, regs); |
Peter Zijlstra | a8b0ca1 | 2011-06-27 14:41:57 +0200 | [diff] [blame] | 345 | perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, |
Paul Mundt | ace2dc7 | 2010-10-13 06:55:26 +0900 | [diff] [blame] | 346 | regs, address); |
| 347 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 348 | |
| 349 | ret = -EFAULT; |
| 350 | switch (instruction&0xF000) { |
| 351 | case 0x0000: |
| 352 | if (instruction==0x000B) { |
| 353 | /* rts */ |
Magnus Damm | e7cc9a7 | 2008-02-07 20:18:21 +0900 | [diff] [blame] | 354 | ret = handle_delayslot(regs, instruction, ma); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 355 | if (ret==0) |
| 356 | regs->pc = regs->pr; |
| 357 | } |
| 358 | else if ((instruction&0x00FF)==0x0023) { |
| 359 | /* braf @Rm */ |
Magnus Damm | e7cc9a7 | 2008-02-07 20:18:21 +0900 | [diff] [blame] | 360 | ret = handle_delayslot(regs, instruction, ma); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 361 | if (ret==0) |
| 362 | regs->pc += rm + 4; |
| 363 | } |
| 364 | else if ((instruction&0x00FF)==0x0003) { |
| 365 | /* bsrf @Rm */ |
Magnus Damm | e7cc9a7 | 2008-02-07 20:18:21 +0900 | [diff] [blame] | 366 | ret = handle_delayslot(regs, instruction, ma); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 367 | if (ret==0) { |
| 368 | regs->pr = regs->pc + 4; |
| 369 | regs->pc += rm + 4; |
| 370 | } |
| 371 | } |
| 372 | else { |
| 373 | /* mov.[bwl] to/from memory via r0+rn */ |
| 374 | goto simple; |
| 375 | } |
| 376 | break; |
| 377 | |
| 378 | case 0x1000: /* mov.l Rm,@(disp,Rn) */ |
| 379 | goto simple; |
| 380 | |
| 381 | case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */ |
| 382 | goto simple; |
| 383 | |
| 384 | case 0x4000: |
| 385 | if ((instruction&0x00FF)==0x002B) { |
| 386 | /* jmp @Rm */ |
Magnus Damm | e7cc9a7 | 2008-02-07 20:18:21 +0900 | [diff] [blame] | 387 | ret = handle_delayslot(regs, instruction, ma); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 388 | if (ret==0) |
| 389 | regs->pc = rm; |
| 390 | } |
| 391 | else if ((instruction&0x00FF)==0x000B) { |
| 392 | /* jsr @Rm */ |
Magnus Damm | e7cc9a7 | 2008-02-07 20:18:21 +0900 | [diff] [blame] | 393 | ret = handle_delayslot(regs, instruction, ma); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 394 | if (ret==0) { |
| 395 | regs->pr = regs->pc + 4; |
| 396 | regs->pc = rm; |
| 397 | } |
| 398 | } |
| 399 | else { |
| 400 | /* mov.[bwl] to/from memory via r0+rn */ |
| 401 | goto simple; |
| 402 | } |
| 403 | break; |
| 404 | |
| 405 | case 0x5000: /* mov.l @(disp,Rm),Rn */ |
| 406 | goto simple; |
| 407 | |
| 408 | case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */ |
| 409 | goto simple; |
| 410 | |
| 411 | case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */ |
| 412 | switch (instruction&0x0F00) { |
| 413 | case 0x0100: /* mov.w R0,@(disp,Rm) */ |
| 414 | goto simple; |
| 415 | case 0x0500: /* mov.w @(disp,Rm),R0 */ |
| 416 | goto simple; |
| 417 | case 0x0B00: /* bf lab - no delayslot*/ |
Phil Edworthy | 0710b91c | 2011-08-22 15:56:08 +0000 | [diff] [blame] | 418 | ret = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 419 | break; |
| 420 | case 0x0F00: /* bf/s lab */ |
Magnus Damm | e7cc9a7 | 2008-02-07 20:18:21 +0900 | [diff] [blame] | 421 | ret = handle_delayslot(regs, instruction, ma); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 422 | if (ret==0) { |
| 423 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) |
| 424 | if ((regs->sr & 0x00000001) != 0) |
| 425 | regs->pc += 4; /* next after slot */ |
| 426 | else |
| 427 | #endif |
| 428 | regs->pc += SH_PC_8BIT_OFFSET(instruction); |
| 429 | } |
| 430 | break; |
| 431 | case 0x0900: /* bt lab - no delayslot */ |
Phil Edworthy | 0710b91c | 2011-08-22 15:56:08 +0000 | [diff] [blame] | 432 | ret = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 433 | break; |
| 434 | case 0x0D00: /* bt/s lab */ |
Magnus Damm | e7cc9a7 | 2008-02-07 20:18:21 +0900 | [diff] [blame] | 435 | ret = handle_delayslot(regs, instruction, ma); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 436 | if (ret==0) { |
| 437 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) |
| 438 | if ((regs->sr & 0x00000001) == 0) |
| 439 | regs->pc += 4; /* next after slot */ |
| 440 | else |
| 441 | #endif |
| 442 | regs->pc += SH_PC_8BIT_OFFSET(instruction); |
| 443 | } |
| 444 | break; |
| 445 | } |
| 446 | break; |
| 447 | |
Phil Edworthy | 34f7145 | 2011-08-24 10:43:59 +0000 | [diff] [blame] | 448 | case 0x9000: /* mov.w @(disp,Rm),Rn */ |
| 449 | goto simple; |
| 450 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 451 | case 0xA000: /* bra label */ |
Magnus Damm | e7cc9a7 | 2008-02-07 20:18:21 +0900 | [diff] [blame] | 452 | ret = handle_delayslot(regs, instruction, ma); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 453 | if (ret==0) |
| 454 | regs->pc += SH_PC_12BIT_OFFSET(instruction); |
| 455 | break; |
| 456 | |
| 457 | case 0xB000: /* bsr label */ |
Magnus Damm | e7cc9a7 | 2008-02-07 20:18:21 +0900 | [diff] [blame] | 458 | ret = handle_delayslot(regs, instruction, ma); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 459 | if (ret==0) { |
| 460 | regs->pr = regs->pc + 4; |
| 461 | regs->pc += SH_PC_12BIT_OFFSET(instruction); |
| 462 | } |
| 463 | break; |
Phil Edworthy | 34f7145 | 2011-08-24 10:43:59 +0000 | [diff] [blame] | 464 | |
| 465 | case 0xD000: /* mov.l @(disp,Rm),Rn */ |
| 466 | goto simple; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 467 | } |
| 468 | return ret; |
| 469 | |
| 470 | /* handle non-delay-slot instruction */ |
| 471 | simple: |
Magnus Damm | e7cc9a7 | 2008-02-07 20:18:21 +0900 | [diff] [blame] | 472 | ret = handle_unaligned_ins(instruction, regs, ma); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 473 | if (ret==0) |
Paul Mundt | 53f983a | 2007-05-08 15:31:48 +0900 | [diff] [blame] | 474 | regs->pc += instruction_size(instruction); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 475 | return ret; |
| 476 | } |
| 477 | |
| 478 | /* |
Stuart Menefy | b5a1bcb | 2006-11-21 13:34:04 +0900 | [diff] [blame] | 479 | * Handle various address error exceptions: |
| 480 | * - instruction address error: |
| 481 | * misaligned PC |
| 482 | * PC >= 0x80000000 in user mode |
| 483 | * - data address error (read and write) |
| 484 | * misaligned data access |
| 485 | * access to >= 0x80000000 is user mode |
| 486 | * Unfortuntaly we can't distinguish between instruction address error |
Simon Arlott | e868d61 | 2007-05-14 08:15:10 +0900 | [diff] [blame] | 487 | * and data address errors caused by read accesses. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 488 | */ |
Stuart Menefy | f0bc814 | 2006-11-21 11:16:57 +0900 | [diff] [blame] | 489 | asmlinkage void do_address_error(struct pt_regs *regs, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 490 | unsigned long writeaccess, |
| 491 | unsigned long address) |
| 492 | { |
Yoshinori Sato | 0983b31 | 2006-11-05 15:58:47 +0900 | [diff] [blame] | 493 | unsigned long error_code = 0; |
Paul Mundt | 2bcfffa | 2009-05-09 16:02:08 +0900 | [diff] [blame] | 494 | insn_size_t instruction; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 495 | int tmp; |
| 496 | |
Yoshinori Sato | 0983b31 | 2006-11-05 15:58:47 +0900 | [diff] [blame] | 497 | /* Intentional ifdef */ |
| 498 | #ifdef CONFIG_CPU_HAS_SR_RB |
Paul Mundt | 4c59e29 | 2008-09-21 12:00:23 +0900 | [diff] [blame] | 499 | error_code = lookup_exception_vector(); |
Yoshinori Sato | 0983b31 | 2006-11-05 15:58:47 +0900 | [diff] [blame] | 500 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 501 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 502 | if (user_mode(regs)) { |
Stuart Menefy | b5a1bcb | 2006-11-21 13:34:04 +0900 | [diff] [blame] | 503 | int si_code = BUS_ADRERR; |
Paul Mundt | a99eae5 | 2010-01-12 16:12:25 +0900 | [diff] [blame] | 504 | unsigned int user_action; |
Stuart Menefy | b5a1bcb | 2006-11-21 13:34:04 +0900 | [diff] [blame] | 505 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 506 | local_irq_enable(); |
Paul Mundt | a99eae5 | 2010-01-12 16:12:25 +0900 | [diff] [blame] | 507 | inc_unaligned_user_access(); |
Andre Draszik | 7436cde | 2009-08-24 14:53:46 +0900 | [diff] [blame] | 508 | |
Al Viro | ca42bc4 | 2020-12-31 23:23:01 +0000 | [diff] [blame] | 509 | if (copy_from_user(&instruction, (insn_size_t __user *)(regs->pc & ~1), |
Paul Mundt | 23c4c82 | 2009-09-24 17:38:18 +0900 | [diff] [blame] | 510 | sizeof(instruction))) { |
Andre Draszik | 5a0ab35 | 2009-08-24 15:01:10 +0900 | [diff] [blame] | 511 | goto uspace_segv; |
| 512 | } |
Andre Draszik | 5a0ab35 | 2009-08-24 15:01:10 +0900 | [diff] [blame] | 513 | |
Andre Draszik | 7436cde | 2009-08-24 14:53:46 +0900 | [diff] [blame] | 514 | /* shout about userspace fixups */ |
Paul Mundt | a99eae5 | 2010-01-12 16:12:25 +0900 | [diff] [blame] | 515 | unaligned_fixups_notify(current, instruction, regs); |
Andre Draszik | 7436cde | 2009-08-24 14:53:46 +0900 | [diff] [blame] | 516 | |
Paul Mundt | a99eae5 | 2010-01-12 16:12:25 +0900 | [diff] [blame] | 517 | user_action = unaligned_user_action(); |
| 518 | if (user_action & UM_FIXUP) |
Andre Draszik | 7436cde | 2009-08-24 14:53:46 +0900 | [diff] [blame] | 519 | goto fixup; |
Paul Mundt | a99eae5 | 2010-01-12 16:12:25 +0900 | [diff] [blame] | 520 | if (user_action & UM_SIGNAL) |
Andre Draszik | 7436cde | 2009-08-24 14:53:46 +0900 | [diff] [blame] | 521 | goto uspace_segv; |
| 522 | else { |
| 523 | /* ignore */ |
Andre Draszik | 5a0ab35 | 2009-08-24 15:01:10 +0900 | [diff] [blame] | 524 | regs->pc += instruction_size(instruction); |
Andre Draszik | 7436cde | 2009-08-24 14:53:46 +0900 | [diff] [blame] | 525 | return; |
| 526 | } |
| 527 | |
| 528 | fixup: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 529 | /* bad PC is not something we can fix */ |
Stuart Menefy | b5a1bcb | 2006-11-21 13:34:04 +0900 | [diff] [blame] | 530 | if (regs->pc & 1) { |
| 531 | si_code = BUS_ADRALN; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 532 | goto uspace_segv; |
Stuart Menefy | b5a1bcb | 2006-11-21 13:34:04 +0900 | [diff] [blame] | 533 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 534 | |
Magnus Damm | e7cc9a7 | 2008-02-07 20:18:21 +0900 | [diff] [blame] | 535 | tmp = handle_unaligned_access(instruction, regs, |
Paul Mundt | ace2dc7 | 2010-10-13 06:55:26 +0900 | [diff] [blame] | 536 | &user_mem_access, 0, |
| 537 | address); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 538 | |
Paul Mundt | a99eae5 | 2010-01-12 16:12:25 +0900 | [diff] [blame] | 539 | if (tmp == 0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 540 | return; /* sorted */ |
Stuart Menefy | b5a1bcb | 2006-11-21 13:34:04 +0900 | [diff] [blame] | 541 | uspace_segv: |
| 542 | printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned " |
| 543 | "access (PC %lx PR %lx)\n", current->comm, regs->pc, |
| 544 | regs->pr); |
| 545 | |
Eric W. Biederman | 2e1661d2 | 2019-05-23 11:04:24 -0500 | [diff] [blame] | 546 | force_sig_fault(SIGBUS, si_code, (void __user *)address); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 547 | } else { |
Paul Mundt | a99eae5 | 2010-01-12 16:12:25 +0900 | [diff] [blame] | 548 | inc_unaligned_kernel_access(); |
Andre Draszik | 7436cde | 2009-08-24 14:53:46 +0900 | [diff] [blame] | 549 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 550 | if (regs->pc & 1) |
| 551 | die("unaligned program counter", regs, error_code); |
| 552 | |
Arnd Bergmann | 75d4d29 | 2022-02-11 17:26:42 +0100 | [diff] [blame] | 553 | if (copy_from_kernel_nofault(&instruction, (void *)(regs->pc), |
Magnus Damm | 4b5a9ef | 2008-02-07 20:04:12 +0900 | [diff] [blame] | 554 | sizeof(instruction))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 555 | /* Argh. Fault on the instruction itself. |
| 556 | This should never happen non-SMP |
| 557 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 558 | die("insn faulting in do_address_error", regs, 0); |
| 559 | } |
| 560 | |
Paul Mundt | a99eae5 | 2010-01-12 16:12:25 +0900 | [diff] [blame] | 561 | unaligned_fixups_notify(current, instruction, regs); |
Paul Mundt | 40258ee | 2009-09-24 17:48:15 +0900 | [diff] [blame] | 562 | |
Arnd Bergmann | 75d4d29 | 2022-02-11 17:26:42 +0100 | [diff] [blame] | 563 | handle_unaligned_access(instruction, regs, &kernel_mem_access, |
Paul Mundt | ace2dc7 | 2010-10-13 06:55:26 +0900 | [diff] [blame] | 564 | 0, address); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 565 | } |
| 566 | } |
| 567 | |
| 568 | #ifdef CONFIG_SH_DSP |
| 569 | /* |
| 570 | * SH-DSP support gerg@snapgear.com. |
| 571 | */ |
Geert Uytterhoeven | fdb2dd7 | 2024-03-04 20:10:44 +0100 | [diff] [blame] | 572 | static int is_dsp_inst(struct pt_regs *regs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 573 | { |
Paul Mundt | 882c12c | 2007-05-14 17:26:34 +0900 | [diff] [blame] | 574 | unsigned short inst = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 575 | |
Stuart Menefy | f0bc814 | 2006-11-21 11:16:57 +0900 | [diff] [blame] | 576 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 577 | * Safe guard if DSP mode is already enabled or we're lacking |
| 578 | * the DSP altogether. |
| 579 | */ |
Paul Mundt | 11c1965 | 2006-12-25 10:19:56 +0900 | [diff] [blame] | 580 | if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 581 | return 0; |
| 582 | |
| 583 | get_user(inst, ((unsigned short *) regs->pc)); |
| 584 | |
| 585 | inst &= 0xf000; |
| 586 | |
| 587 | /* Check for any type of DSP or support instruction */ |
| 588 | if ((inst == 0xf000) || (inst == 0x4000)) |
| 589 | return 1; |
| 590 | |
| 591 | return 0; |
| 592 | } |
| 593 | #else |
Geert Uytterhoeven | fdb2dd7 | 2024-03-04 20:10:44 +0100 | [diff] [blame] | 594 | static inline int is_dsp_inst(struct pt_regs *regs) { return 0; } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 595 | #endif /* CONFIG_SH_DSP */ |
| 596 | |
Yoshinori Sato | 0983b31 | 2006-11-05 15:58:47 +0900 | [diff] [blame] | 597 | #ifdef CONFIG_CPU_SH2A |
Bobby Bingham | a3c1951 | 2014-04-03 14:46:41 -0700 | [diff] [blame] | 598 | asmlinkage void do_divide_error(unsigned long r4) |
Yoshinori Sato | 0983b31 | 2006-11-05 15:58:47 +0900 | [diff] [blame] | 599 | { |
Eric W. Biederman | c65626c | 2018-04-15 19:56:33 -0500 | [diff] [blame] | 600 | int code; |
Yoshinori Sato | 0983b31 | 2006-11-05 15:58:47 +0900 | [diff] [blame] | 601 | |
Yoshinori Sato | 0983b31 | 2006-11-05 15:58:47 +0900 | [diff] [blame] | 602 | switch (r4) { |
| 603 | case TRAP_DIVZERO_ERROR: |
Eric W. Biederman | c65626c | 2018-04-15 19:56:33 -0500 | [diff] [blame] | 604 | code = FPE_INTDIV; |
Yoshinori Sato | 0983b31 | 2006-11-05 15:58:47 +0900 | [diff] [blame] | 605 | break; |
| 606 | case TRAP_DIVOVF_ERROR: |
Eric W. Biederman | c65626c | 2018-04-15 19:56:33 -0500 | [diff] [blame] | 607 | code = FPE_INTOVF; |
Yoshinori Sato | 0983b31 | 2006-11-05 15:58:47 +0900 | [diff] [blame] | 608 | break; |
Eric W. Biederman | 26da350 | 2018-05-29 09:40:11 -0500 | [diff] [blame] | 609 | default: |
| 610 | /* Let gcc know unhandled cases don't make it past here */ |
| 611 | return; |
Yoshinori Sato | 0983b31 | 2006-11-05 15:58:47 +0900 | [diff] [blame] | 612 | } |
Eric W. Biederman | 2e1661d2 | 2019-05-23 11:04:24 -0500 | [diff] [blame] | 613 | force_sig_fault(SIGFPE, code, NULL); |
Yoshinori Sato | 0983b31 | 2006-11-05 15:58:47 +0900 | [diff] [blame] | 614 | } |
| 615 | #endif |
| 616 | |
Bobby Bingham | a3c1951 | 2014-04-03 14:46:41 -0700 | [diff] [blame] | 617 | asmlinkage void do_reserved_inst(void) |
Takashi YOSHII | 4b56568 | 2006-09-27 17:15:32 +0900 | [diff] [blame] | 618 | { |
Bobby Bingham | a3c1951 | 2014-04-03 14:46:41 -0700 | [diff] [blame] | 619 | struct pt_regs *regs = current_pt_regs(); |
Takashi YOSHII | 4b56568 | 2006-09-27 17:15:32 +0900 | [diff] [blame] | 620 | unsigned long error_code; |
Takashi YOSHII | 4b56568 | 2006-09-27 17:15:32 +0900 | [diff] [blame] | 621 | |
| 622 | #ifdef CONFIG_SH_FPU_EMU |
Yoshinori Sato | 0983b31 | 2006-11-05 15:58:47 +0900 | [diff] [blame] | 623 | unsigned short inst = 0; |
Takashi YOSHII | 4b56568 | 2006-09-27 17:15:32 +0900 | [diff] [blame] | 624 | int err; |
| 625 | |
Al Viro | ca42bc4 | 2020-12-31 23:23:01 +0000 | [diff] [blame] | 626 | get_user(inst, (unsigned short __user *)regs->pc); |
Takashi YOSHII | 4b56568 | 2006-09-27 17:15:32 +0900 | [diff] [blame] | 627 | |
Stuart Menefy | f0bc814 | 2006-11-21 11:16:57 +0900 | [diff] [blame] | 628 | err = do_fpu_inst(inst, regs); |
Takashi YOSHII | 4b56568 | 2006-09-27 17:15:32 +0900 | [diff] [blame] | 629 | if (!err) { |
Paul Mundt | 53f983a | 2007-05-08 15:31:48 +0900 | [diff] [blame] | 630 | regs->pc += instruction_size(inst); |
Takashi YOSHII | 4b56568 | 2006-09-27 17:15:32 +0900 | [diff] [blame] | 631 | return; |
| 632 | } |
| 633 | /* not a FPU inst. */ |
| 634 | #endif |
| 635 | |
| 636 | #ifdef CONFIG_SH_DSP |
| 637 | /* Check if it's a DSP instruction */ |
Stuart Menefy | b5a1bcb | 2006-11-21 13:34:04 +0900 | [diff] [blame] | 638 | if (is_dsp_inst(regs)) { |
Takashi YOSHII | 4b56568 | 2006-09-27 17:15:32 +0900 | [diff] [blame] | 639 | /* Enable DSP mode, and restart instruction. */ |
Stuart Menefy | f0bc814 | 2006-11-21 11:16:57 +0900 | [diff] [blame] | 640 | regs->sr |= SR_DSP; |
Michael Trimarchi | 01ab103 | 2009-04-03 17:32:33 +0000 | [diff] [blame] | 641 | /* Save DSP mode */ |
Eric W. Biederman | 3cf5d07 | 2019-05-23 10:17:27 -0500 | [diff] [blame] | 642 | current->thread.dsp_status.status |= SR_DSP; |
Takashi YOSHII | 4b56568 | 2006-09-27 17:15:32 +0900 | [diff] [blame] | 643 | return; |
| 644 | } |
| 645 | #endif |
| 646 | |
Paul Mundt | 4c59e29 | 2008-09-21 12:00:23 +0900 | [diff] [blame] | 647 | error_code = lookup_exception_vector(); |
Yoshinori Sato | 0983b31 | 2006-11-05 15:58:47 +0900 | [diff] [blame] | 648 | |
Takashi YOSHII | 4b56568 | 2006-09-27 17:15:32 +0900 | [diff] [blame] | 649 | local_irq_enable(); |
Eric W. Biederman | 3cf5d07 | 2019-05-23 10:17:27 -0500 | [diff] [blame] | 650 | force_sig(SIGILL); |
Stuart Menefy | f0bc814 | 2006-11-21 11:16:57 +0900 | [diff] [blame] | 651 | die_if_no_fixup("reserved instruction", regs, error_code); |
Takashi YOSHII | 4b56568 | 2006-09-27 17:15:32 +0900 | [diff] [blame] | 652 | } |
| 653 | |
| 654 | #ifdef CONFIG_SH_FPU_EMU |
Paul Mundt | edfd6da | 2008-11-26 13:06:04 +0900 | [diff] [blame] | 655 | static int emulate_branch(unsigned short inst, struct pt_regs *regs) |
Takashi YOSHII | 4b56568 | 2006-09-27 17:15:32 +0900 | [diff] [blame] | 656 | { |
| 657 | /* |
| 658 | * bfs: 8fxx: PC+=d*2+4; |
| 659 | * bts: 8dxx: PC+=d*2+4; |
| 660 | * bra: axxx: PC+=D*2+4; |
| 661 | * bsr: bxxx: PC+=D*2+4 after PR=PC+4; |
| 662 | * braf:0x23: PC+=Rn*2+4; |
| 663 | * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4; |
| 664 | * jmp: 4x2b: PC=Rn; |
| 665 | * jsr: 4x0b: PC=Rn after PR=PC+4; |
| 666 | * rts: 000b: PC=PR; |
| 667 | */ |
Paul Mundt | edfd6da | 2008-11-26 13:06:04 +0900 | [diff] [blame] | 668 | if (((inst & 0xf000) == 0xb000) || /* bsr */ |
| 669 | ((inst & 0xf0ff) == 0x0003) || /* bsrf */ |
| 670 | ((inst & 0xf0ff) == 0x400b)) /* jsr */ |
| 671 | regs->pr = regs->pc + 4; |
| 672 | |
| 673 | if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */ |
Takashi YOSHII | 4b56568 | 2006-09-27 17:15:32 +0900 | [diff] [blame] | 674 | regs->pc += SH_PC_8BIT_OFFSET(inst); |
| 675 | return 0; |
| 676 | } |
| 677 | |
Paul Mundt | edfd6da | 2008-11-26 13:06:04 +0900 | [diff] [blame] | 678 | if ((inst & 0xe000) == 0xa000) { /* bra, bsr */ |
Takashi YOSHII | 4b56568 | 2006-09-27 17:15:32 +0900 | [diff] [blame] | 679 | regs->pc += SH_PC_12BIT_OFFSET(inst); |
| 680 | return 0; |
| 681 | } |
| 682 | |
Paul Mundt | edfd6da | 2008-11-26 13:06:04 +0900 | [diff] [blame] | 683 | if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */ |
Takashi YOSHII | 4b56568 | 2006-09-27 17:15:32 +0900 | [diff] [blame] | 684 | regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4; |
| 685 | return 0; |
| 686 | } |
| 687 | |
Paul Mundt | edfd6da | 2008-11-26 13:06:04 +0900 | [diff] [blame] | 688 | if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */ |
Takashi YOSHII | 4b56568 | 2006-09-27 17:15:32 +0900 | [diff] [blame] | 689 | regs->pc = regs->regs[(inst & 0x0f00) >> 8]; |
| 690 | return 0; |
| 691 | } |
| 692 | |
Paul Mundt | edfd6da | 2008-11-26 13:06:04 +0900 | [diff] [blame] | 693 | if ((inst & 0xffff) == 0x000b) { /* rts */ |
Takashi YOSHII | 4b56568 | 2006-09-27 17:15:32 +0900 | [diff] [blame] | 694 | regs->pc = regs->pr; |
| 695 | return 0; |
| 696 | } |
| 697 | |
| 698 | return 1; |
| 699 | } |
| 700 | #endif |
| 701 | |
Bobby Bingham | a3c1951 | 2014-04-03 14:46:41 -0700 | [diff] [blame] | 702 | asmlinkage void do_illegal_slot_inst(void) |
Takashi YOSHII | 4b56568 | 2006-09-27 17:15:32 +0900 | [diff] [blame] | 703 | { |
Bobby Bingham | a3c1951 | 2014-04-03 14:46:41 -0700 | [diff] [blame] | 704 | struct pt_regs *regs = current_pt_regs(); |
Paul Mundt | b3d765f | 2008-09-17 23:12:11 +0900 | [diff] [blame] | 705 | unsigned long inst; |
Chris Smith | d39f545 | 2008-09-05 17:15:39 +0900 | [diff] [blame] | 706 | |
| 707 | if (kprobe_handle_illslot(regs->pc) == 0) |
| 708 | return; |
| 709 | |
Takashi YOSHII | 4b56568 | 2006-09-27 17:15:32 +0900 | [diff] [blame] | 710 | #ifdef CONFIG_SH_FPU_EMU |
Al Viro | ca42bc4 | 2020-12-31 23:23:01 +0000 | [diff] [blame] | 711 | get_user(inst, (unsigned short __user *)regs->pc + 1); |
Stuart Menefy | f0bc814 | 2006-11-21 11:16:57 +0900 | [diff] [blame] | 712 | if (!do_fpu_inst(inst, regs)) { |
Al Viro | ca42bc4 | 2020-12-31 23:23:01 +0000 | [diff] [blame] | 713 | get_user(inst, (unsigned short __user *)regs->pc); |
Stuart Menefy | f0bc814 | 2006-11-21 11:16:57 +0900 | [diff] [blame] | 714 | if (!emulate_branch(inst, regs)) |
Takashi YOSHII | 4b56568 | 2006-09-27 17:15:32 +0900 | [diff] [blame] | 715 | return; |
| 716 | /* fault in branch.*/ |
| 717 | } |
| 718 | /* not a FPU inst. */ |
| 719 | #endif |
| 720 | |
Paul Mundt | 4c59e29 | 2008-09-21 12:00:23 +0900 | [diff] [blame] | 721 | inst = lookup_exception_vector(); |
Yoshinori Sato | 0983b31 | 2006-11-05 15:58:47 +0900 | [diff] [blame] | 722 | |
Takashi YOSHII | 4b56568 | 2006-09-27 17:15:32 +0900 | [diff] [blame] | 723 | local_irq_enable(); |
Eric W. Biederman | 3cf5d07 | 2019-05-23 10:17:27 -0500 | [diff] [blame] | 724 | force_sig(SIGILL); |
Paul Mundt | b3d765f | 2008-09-17 23:12:11 +0900 | [diff] [blame] | 725 | die_if_no_fixup("illegal slot instruction", regs, inst); |
Takashi YOSHII | 4b56568 | 2006-09-27 17:15:32 +0900 | [diff] [blame] | 726 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 727 | |
Bobby Bingham | a3c1951 | 2014-04-03 14:46:41 -0700 | [diff] [blame] | 728 | asmlinkage void do_exception_error(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 729 | { |
| 730 | long ex; |
Yoshinori Sato | 0983b31 | 2006-11-05 15:58:47 +0900 | [diff] [blame] | 731 | |
Paul Mundt | 4c59e29 | 2008-09-21 12:00:23 +0900 | [diff] [blame] | 732 | ex = lookup_exception_vector(); |
Bobby Bingham | a3c1951 | 2014-04-03 14:46:41 -0700 | [diff] [blame] | 733 | die_if_kernel("exception", current_pt_regs(), ex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 734 | } |
| 735 | |
Paul Gortmaker | 4603f53 | 2013-06-18 17:10:12 -0400 | [diff] [blame] | 736 | void per_cpu_trap_init(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 737 | { |
| 738 | extern void *vbr_base; |
| 739 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 740 | /* NOTE: The VBR value should be at P1 |
| 741 | (or P2, virtural "fixed" address space). |
| 742 | It's definitely should not in physical address. */ |
| 743 | |
| 744 | asm volatile("ldc %0, vbr" |
| 745 | : /* no output */ |
| 746 | : "r" (&vbr_base) |
| 747 | : "memory"); |
Magnus Damm | 68a1aed | 2010-09-24 09:05:38 +0000 | [diff] [blame] | 748 | |
| 749 | /* disable exception blocking now when the vbr has been setup */ |
| 750 | clear_bl_bit(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 751 | } |
| 752 | |
Paul Mundt | 1f66658 | 2006-10-19 16:20:25 +0900 | [diff] [blame] | 753 | void *set_exception_table_vec(unsigned int vec, void *handler) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 754 | { |
| 755 | extern void *exception_handling_table[]; |
Paul Mundt | 1f66658 | 2006-10-19 16:20:25 +0900 | [diff] [blame] | 756 | void *old_handler; |
Stuart Menefy | b5a1bcb | 2006-11-21 13:34:04 +0900 | [diff] [blame] | 757 | |
Paul Mundt | 1f66658 | 2006-10-19 16:20:25 +0900 | [diff] [blame] | 758 | old_handler = exception_handling_table[vec]; |
| 759 | exception_handling_table[vec] = handler; |
| 760 | return old_handler; |
| 761 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 762 | |
Paul Mundt | 1f66658 | 2006-10-19 16:20:25 +0900 | [diff] [blame] | 763 | void __init trap_init(void) |
| 764 | { |
| 765 | set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst); |
| 766 | set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 767 | |
Takashi YOSHII | 4b56568 | 2006-09-27 17:15:32 +0900 | [diff] [blame] | 768 | #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \ |
| 769 | defined(CONFIG_SH_FPU_EMU) |
| 770 | /* |
| 771 | * For SH-4 lacking an FPU, treat floating point instructions as |
| 772 | * reserved. They'll be handled in the math-emu case, or faulted on |
| 773 | * otherwise. |
| 774 | */ |
Paul Mundt | 1f66658 | 2006-10-19 16:20:25 +0900 | [diff] [blame] | 775 | set_exception_table_evt(0x800, do_reserved_inst); |
| 776 | set_exception_table_evt(0x820, do_illegal_slot_inst); |
| 777 | #elif defined(CONFIG_SH_FPU) |
Paul Mundt | 74d99a5 | 2007-11-26 20:38:36 +0900 | [diff] [blame] | 778 | set_exception_table_evt(0x800, fpu_state_restore_trap_handler); |
| 779 | set_exception_table_evt(0x820, fpu_state_restore_trap_handler); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 780 | #endif |
Yoshinori Sato | 0983b31 | 2006-11-05 15:58:47 +0900 | [diff] [blame] | 781 | |
| 782 | #ifdef CONFIG_CPU_SH2 |
Paul Mundt | 5a4f7c6 | 2007-11-20 18:08:06 +0900 | [diff] [blame] | 783 | set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler); |
Yoshinori Sato | 0983b31 | 2006-11-05 15:58:47 +0900 | [diff] [blame] | 784 | #endif |
| 785 | #ifdef CONFIG_CPU_SH2A |
| 786 | set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error); |
| 787 | set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error); |
Yoshinori Sato | 6e80f5e | 2008-07-10 01:20:03 +0900 | [diff] [blame] | 788 | #ifdef CONFIG_SH_FPU |
| 789 | set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler); |
| 790 | #endif |
Yoshinori Sato | 0983b31 | 2006-11-05 15:58:47 +0900 | [diff] [blame] | 791 | #endif |
Stuart Menefy | b5a1bcb | 2006-11-21 13:34:04 +0900 | [diff] [blame] | 792 | |
Peter Griffin | cd89436 | 2009-05-08 15:51:51 +0100 | [diff] [blame] | 793 | #ifdef TRAP_UBC |
Paul Mundt | c476181 | 2010-01-05 12:44:02 +0900 | [diff] [blame] | 794 | set_exception_table_vec(TRAP_UBC, breakpoint_trap_handler); |
Peter Griffin | cd89436 | 2009-05-08 15:51:51 +0100 | [diff] [blame] | 795 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 796 | } |