blob: 4cfdd3dfbd42acfdcd4c63721f609e309298385e [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Detlev Casanova0f2ce162011-04-05 09:06:21 -03002/*
Philipp Zabeld8dde6c2014-06-03 06:35:54 -03003 * Driver for MT9V022, MT9V024, MT9V032, and MT9V034 CMOS Image Sensors
Detlev Casanova0f2ce162011-04-05 09:06:21 -03004 *
5 * Copyright (C) 2010, Laurent Pinchart <laurent.pinchart@ideasonboard.com>
6 *
7 * Based on the MT9M001 driver,
8 *
9 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
Detlev Casanova0f2ce162011-04-05 09:06:21 -030010 */
11
Laurent Pinchart3300a8f2013-07-05 07:16:02 -030012#include <linux/clk.h>
Detlev Casanova0f2ce162011-04-05 09:06:21 -030013#include <linux/delay.h>
Markus Pargmann28d5bdb2015-12-14 12:41:51 -020014#include <linux/gpio/consumer.h>
Detlev Casanova0f2ce162011-04-05 09:06:21 -030015#include <linux/i2c.h>
16#include <linux/log2.h>
17#include <linux/mutex.h>
Laurent Pinchartf2272e12014-01-01 14:40:35 -030018#include <linux/of.h>
Sakari Ailus859969b2016-08-26 20:17:25 -030019#include <linux/of_graph.h>
Philipp Zabel80b44ef2014-06-04 13:57:03 -030020#include <linux/regmap.h>
Detlev Casanova0f2ce162011-04-05 09:06:21 -030021#include <linux/slab.h>
22#include <linux/videodev2.h>
23#include <linux/v4l2-mediabus.h>
Paul Gortmaker7a707b82011-07-03 14:03:12 -040024#include <linux/module.h>
Detlev Casanova0f2ce162011-04-05 09:06:21 -030025
Mauro Carvalho Chehabb5dcee222015-11-10 12:01:44 -020026#include <media/i2c/mt9v032.h>
Detlev Casanova0f2ce162011-04-05 09:06:21 -030027#include <media/v4l2-ctrls.h>
28#include <media/v4l2-device.h>
Sakari Ailus859969b2016-08-26 20:17:25 -030029#include <media/v4l2-fwnode.h>
Detlev Casanova0f2ce162011-04-05 09:06:21 -030030#include <media/v4l2-subdev.h>
31
Laurent Pinchart2b9e9f72013-12-02 11:52:44 -030032/* The first four rows are black rows. The active area spans 753x481 pixels. */
33#define MT9V032_PIXEL_ARRAY_HEIGHT 485
34#define MT9V032_PIXEL_ARRAY_WIDTH 753
Detlev Casanova0f2ce162011-04-05 09:06:21 -030035
Laurent Pincharte9a50e42012-07-26 08:02:50 -030036#define MT9V032_SYSCLK_FREQ_DEF 26600000
37
Detlev Casanova0f2ce162011-04-05 09:06:21 -030038#define MT9V032_CHIP_VERSION 0x00
39#define MT9V032_CHIP_ID_REV1 0x1311
40#define MT9V032_CHIP_ID_REV3 0x1313
Laurent Pinchartdaecfeb2013-12-02 12:01:03 -030041#define MT9V034_CHIP_ID_REV1 0X1324
Laurent Pinchart86cf7862010-11-28 15:07:20 -030042#define MT9V032_COLUMN_START 0x01
Detlev Casanova0f2ce162011-04-05 09:06:21 -030043#define MT9V032_COLUMN_START_MIN 1
Laurent Pinchart86cf7862010-11-28 15:07:20 -030044#define MT9V032_COLUMN_START_DEF 1
Detlev Casanova0f2ce162011-04-05 09:06:21 -030045#define MT9V032_COLUMN_START_MAX 752
Laurent Pinchart86cf7862010-11-28 15:07:20 -030046#define MT9V032_ROW_START 0x02
47#define MT9V032_ROW_START_MIN 4
48#define MT9V032_ROW_START_DEF 5
49#define MT9V032_ROW_START_MAX 482
Detlev Casanova0f2ce162011-04-05 09:06:21 -030050#define MT9V032_WINDOW_HEIGHT 0x03
51#define MT9V032_WINDOW_HEIGHT_MIN 1
52#define MT9V032_WINDOW_HEIGHT_DEF 480
53#define MT9V032_WINDOW_HEIGHT_MAX 480
54#define MT9V032_WINDOW_WIDTH 0x04
55#define MT9V032_WINDOW_WIDTH_MIN 1
56#define MT9V032_WINDOW_WIDTH_DEF 752
57#define MT9V032_WINDOW_WIDTH_MAX 752
58#define MT9V032_HORIZONTAL_BLANKING 0x05
59#define MT9V032_HORIZONTAL_BLANKING_MIN 43
Laurent Pinchartdaecfeb2013-12-02 12:01:03 -030060#define MT9V034_HORIZONTAL_BLANKING_MIN 61
Laurent Pinchart9ec670e2012-07-23 15:03:34 -030061#define MT9V032_HORIZONTAL_BLANKING_DEF 94
Detlev Casanova0f2ce162011-04-05 09:06:21 -030062#define MT9V032_HORIZONTAL_BLANKING_MAX 1023
63#define MT9V032_VERTICAL_BLANKING 0x06
64#define MT9V032_VERTICAL_BLANKING_MIN 4
Laurent Pinchartdaecfeb2013-12-02 12:01:03 -030065#define MT9V034_VERTICAL_BLANKING_MIN 2
Laurent Pinchart9ec670e2012-07-23 15:03:34 -030066#define MT9V032_VERTICAL_BLANKING_DEF 45
Detlev Casanova0f2ce162011-04-05 09:06:21 -030067#define MT9V032_VERTICAL_BLANKING_MAX 3000
Laurent Pinchartdaecfeb2013-12-02 12:01:03 -030068#define MT9V034_VERTICAL_BLANKING_MAX 32288
Detlev Casanova0f2ce162011-04-05 09:06:21 -030069#define MT9V032_CHIP_CONTROL 0x07
70#define MT9V032_CHIP_CONTROL_MASTER_MODE (1 << 3)
71#define MT9V032_CHIP_CONTROL_DOUT_ENABLE (1 << 7)
72#define MT9V032_CHIP_CONTROL_SEQUENTIAL (1 << 8)
73#define MT9V032_SHUTTER_WIDTH1 0x08
74#define MT9V032_SHUTTER_WIDTH2 0x09
75#define MT9V032_SHUTTER_WIDTH_CONTROL 0x0a
76#define MT9V032_TOTAL_SHUTTER_WIDTH 0x0b
77#define MT9V032_TOTAL_SHUTTER_WIDTH_MIN 1
Laurent Pinchartdaecfeb2013-12-02 12:01:03 -030078#define MT9V034_TOTAL_SHUTTER_WIDTH_MIN 0
Detlev Casanova0f2ce162011-04-05 09:06:21 -030079#define MT9V032_TOTAL_SHUTTER_WIDTH_DEF 480
80#define MT9V032_TOTAL_SHUTTER_WIDTH_MAX 32767
Laurent Pinchartdaecfeb2013-12-02 12:01:03 -030081#define MT9V034_TOTAL_SHUTTER_WIDTH_MAX 32765
Detlev Casanova0f2ce162011-04-05 09:06:21 -030082#define MT9V032_RESET 0x0c
83#define MT9V032_READ_MODE 0x0d
84#define MT9V032_READ_MODE_ROW_BIN_MASK (3 << 0)
85#define MT9V032_READ_MODE_ROW_BIN_SHIFT 0
86#define MT9V032_READ_MODE_COLUMN_BIN_MASK (3 << 2)
87#define MT9V032_READ_MODE_COLUMN_BIN_SHIFT 2
88#define MT9V032_READ_MODE_ROW_FLIP (1 << 4)
89#define MT9V032_READ_MODE_COLUMN_FLIP (1 << 5)
90#define MT9V032_READ_MODE_DARK_COLUMNS (1 << 6)
91#define MT9V032_READ_MODE_DARK_ROWS (1 << 7)
Philipp Zabeld131e542014-06-03 06:35:53 -030092#define MT9V032_READ_MODE_RESERVED 0x0300
Detlev Casanova0f2ce162011-04-05 09:06:21 -030093#define MT9V032_PIXEL_OPERATION_MODE 0x0f
Laurent Pinchartdaecfeb2013-12-02 12:01:03 -030094#define MT9V034_PIXEL_OPERATION_MODE_HDR (1 << 0)
95#define MT9V034_PIXEL_OPERATION_MODE_COLOR (1 << 1)
Detlev Casanova0f2ce162011-04-05 09:06:21 -030096#define MT9V032_PIXEL_OPERATION_MODE_COLOR (1 << 2)
97#define MT9V032_PIXEL_OPERATION_MODE_HDR (1 << 6)
98#define MT9V032_ANALOG_GAIN 0x35
99#define MT9V032_ANALOG_GAIN_MIN 16
100#define MT9V032_ANALOG_GAIN_DEF 16
101#define MT9V032_ANALOG_GAIN_MAX 64
102#define MT9V032_MAX_ANALOG_GAIN 0x36
103#define MT9V032_MAX_ANALOG_GAIN_MAX 127
104#define MT9V032_FRAME_DARK_AVERAGE 0x42
105#define MT9V032_DARK_AVG_THRESH 0x46
106#define MT9V032_DARK_AVG_LOW_THRESH_MASK (255 << 0)
107#define MT9V032_DARK_AVG_LOW_THRESH_SHIFT 0
108#define MT9V032_DARK_AVG_HIGH_THRESH_MASK (255 << 8)
109#define MT9V032_DARK_AVG_HIGH_THRESH_SHIFT 8
110#define MT9V032_ROW_NOISE_CORR_CONTROL 0x70
Laurent Pinchartdaecfeb2013-12-02 12:01:03 -0300111#define MT9V034_ROW_NOISE_CORR_ENABLE (1 << 0)
112#define MT9V034_ROW_NOISE_CORR_USE_BLK_AVG (1 << 1)
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300113#define MT9V032_ROW_NOISE_CORR_ENABLE (1 << 5)
114#define MT9V032_ROW_NOISE_CORR_USE_BLK_AVG (1 << 7)
115#define MT9V032_PIXEL_CLOCK 0x74
Laurent Pinchartdaecfeb2013-12-02 12:01:03 -0300116#define MT9V034_PIXEL_CLOCK 0x72
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300117#define MT9V032_PIXEL_CLOCK_INV_LINE (1 << 0)
118#define MT9V032_PIXEL_CLOCK_INV_FRAME (1 << 1)
119#define MT9V032_PIXEL_CLOCK_XOR_LINE (1 << 2)
120#define MT9V032_PIXEL_CLOCK_CONT_LINE (1 << 3)
121#define MT9V032_PIXEL_CLOCK_INV_PXL_CLK (1 << 4)
122#define MT9V032_TEST_PATTERN 0x7f
123#define MT9V032_TEST_PATTERN_DATA_MASK (1023 << 0)
124#define MT9V032_TEST_PATTERN_DATA_SHIFT 0
125#define MT9V032_TEST_PATTERN_USE_DATA (1 << 10)
126#define MT9V032_TEST_PATTERN_GRAY_MASK (3 << 11)
127#define MT9V032_TEST_PATTERN_GRAY_NONE (0 << 11)
128#define MT9V032_TEST_PATTERN_GRAY_VERTICAL (1 << 11)
129#define MT9V032_TEST_PATTERN_GRAY_HORIZONTAL (2 << 11)
130#define MT9V032_TEST_PATTERN_GRAY_DIAGONAL (3 << 11)
131#define MT9V032_TEST_PATTERN_ENABLE (1 << 13)
132#define MT9V032_TEST_PATTERN_FLIP (1 << 14)
Markus Pargmann81ea4822015-12-14 12:41:53 -0200133#define MT9V032_AEGC_DESIRED_BIN 0xa5
134#define MT9V032_AEC_UPDATE_FREQUENCY 0xa6
135#define MT9V032_AEC_LPF 0xa8
136#define MT9V032_AGC_UPDATE_FREQUENCY 0xa9
137#define MT9V032_AGC_LPF 0xaa
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300138#define MT9V032_AEC_AGC_ENABLE 0xaf
139#define MT9V032_AEC_ENABLE (1 << 0)
140#define MT9V032_AGC_ENABLE (1 << 1)
Markus Pargmann81ea4822015-12-14 12:41:53 -0200141#define MT9V034_AEC_MAX_SHUTTER_WIDTH 0xad
142#define MT9V032_AEC_MAX_SHUTTER_WIDTH 0xbd
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300143#define MT9V032_THERMAL_INFO 0xc1
144
Laurent Pinchart220ddc72013-12-04 15:31:13 -0300145enum mt9v032_model {
Philipp Zabeld8dde6c2014-06-03 06:35:54 -0300146 MT9V032_MODEL_V022_COLOR, /* MT9V022IX7ATC */
147 MT9V032_MODEL_V022_MONO, /* MT9V022IX7ATM */
148 MT9V032_MODEL_V024_COLOR, /* MT9V024IA7XTC */
149 MT9V032_MODEL_V024_MONO, /* MT9V024IA7XTM */
150 MT9V032_MODEL_V032_COLOR, /* MT9V032C12STM */
151 MT9V032_MODEL_V032_MONO, /* MT9V032C12STC */
Laurent Pinchartdaecfeb2013-12-02 12:01:03 -0300152 MT9V032_MODEL_V034_COLOR,
153 MT9V032_MODEL_V034_MONO,
Laurent Pinchart220ddc72013-12-04 15:31:13 -0300154};
155
Laurent Pinchart0a466b62013-12-02 11:59:52 -0300156struct mt9v032_model_version {
157 unsigned int version;
158 const char *name;
159};
160
161struct mt9v032_model_data {
162 unsigned int min_row_time;
163 unsigned int min_hblank;
164 unsigned int min_vblank;
165 unsigned int max_vblank;
166 unsigned int min_shutter;
167 unsigned int max_shutter;
168 unsigned int pclk_reg;
Markus Pargmann81ea4822015-12-14 12:41:53 -0200169 unsigned int aec_max_shutter_reg;
170 const struct v4l2_ctrl_config * const aec_max_shutter_v4l2_ctrl;
Laurent Pinchart0a466b62013-12-02 11:59:52 -0300171};
172
Laurent Pinchart220ddc72013-12-04 15:31:13 -0300173struct mt9v032_model_info {
Laurent Pinchart0a466b62013-12-02 11:59:52 -0300174 const struct mt9v032_model_data *data;
Laurent Pinchart220ddc72013-12-04 15:31:13 -0300175 bool color;
176};
177
Laurent Pinchart0a466b62013-12-02 11:59:52 -0300178static const struct mt9v032_model_version mt9v032_versions[] = {
Philipp Zabeld8dde6c2014-06-03 06:35:54 -0300179 { MT9V032_CHIP_ID_REV1, "MT9V022/MT9V032 rev1/2" },
180 { MT9V032_CHIP_ID_REV3, "MT9V022/MT9V032 rev3" },
181 { MT9V034_CHIP_ID_REV1, "MT9V024/MT9V034 rev1" },
Laurent Pinchart0a466b62013-12-02 11:59:52 -0300182};
183
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300184struct mt9v032 {
185 struct v4l2_subdev subdev;
186 struct media_pad pad;
187
188 struct v4l2_mbus_framefmt format;
189 struct v4l2_rect crop;
Laurent Pinchart637f0052013-12-02 16:39:18 -0300190 unsigned int hratio;
191 unsigned int vratio;
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300192
193 struct v4l2_ctrl_handler ctrls;
Laurent Pincharte9a50e42012-07-26 08:02:50 -0300194 struct {
195 struct v4l2_ctrl *link_freq;
196 struct v4l2_ctrl *pixel_rate;
197 };
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300198
199 struct mutex power_lock;
200 int power_count;
201
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300202 struct regmap *regmap;
Laurent Pinchart3300a8f2013-07-05 07:16:02 -0300203 struct clk *clk;
Markus Pargmann28d5bdb2015-12-14 12:41:51 -0200204 struct gpio_desc *reset_gpio;
205 struct gpio_desc *standby_gpio;
Laurent Pinchart3300a8f2013-07-05 07:16:02 -0300206
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300207 struct mt9v032_platform_data *pdata;
Laurent Pinchart220ddc72013-12-04 15:31:13 -0300208 const struct mt9v032_model_info *model;
Laurent Pinchart0a466b62013-12-02 11:59:52 -0300209 const struct mt9v032_model_version *version;
Laurent Pincharte9a50e42012-07-26 08:02:50 -0300210
211 u32 sysclk;
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300212 u16 aec_agc;
Laurent Pinchart9ec670e2012-07-23 15:03:34 -0300213 u16 hblank;
Lad, Prabhakarb28d7012012-09-25 09:35:43 -0300214 struct {
215 struct v4l2_ctrl *test_pattern;
216 struct v4l2_ctrl *test_pattern_color;
217 };
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300218};
219
220static struct mt9v032 *to_mt9v032(struct v4l2_subdev *sd)
221{
222 return container_of(sd, struct mt9v032, subdev);
223}
224
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300225static int
226mt9v032_update_aec_agc(struct mt9v032 *mt9v032, u16 which, int enable)
227{
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300228 struct regmap *map = mt9v032->regmap;
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300229 u16 value = mt9v032->aec_agc;
230 int ret;
231
232 if (enable)
233 value |= which;
234 else
235 value &= ~which;
236
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300237 ret = regmap_write(map, MT9V032_AEC_AGC_ENABLE, value);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300238 if (ret < 0)
239 return ret;
240
241 mt9v032->aec_agc = value;
242 return 0;
243}
244
Laurent Pinchart9ec670e2012-07-23 15:03:34 -0300245static int
246mt9v032_update_hblank(struct mt9v032 *mt9v032)
247{
Laurent Pinchart9ec670e2012-07-23 15:03:34 -0300248 struct v4l2_rect *crop = &mt9v032->crop;
Laurent Pinchartdaecfeb2013-12-02 12:01:03 -0300249 unsigned int min_hblank = mt9v032->model->data->min_hblank;
Laurent Pinchart0a466b62013-12-02 11:59:52 -0300250 unsigned int hblank;
Laurent Pinchart9ec670e2012-07-23 15:03:34 -0300251
Laurent Pinchartdaecfeb2013-12-02 12:01:03 -0300252 if (mt9v032->version->version == MT9V034_CHIP_ID_REV1)
253 min_hblank += (mt9v032->hratio - 1) * 10;
Philipp Zabelf17bc3f2014-05-26 10:55:51 -0300254 min_hblank = max_t(int, mt9v032->model->data->min_row_time - crop->width,
255 min_hblank);
Laurent Pinchartdaecfeb2013-12-02 12:01:03 -0300256 hblank = max_t(unsigned int, mt9v032->hblank, min_hblank);
257
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300258 return regmap_write(mt9v032->regmap, MT9V032_HORIZONTAL_BLANKING,
259 hblank);
Laurent Pinchart9ec670e2012-07-23 15:03:34 -0300260}
261
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300262static int mt9v032_power_on(struct mt9v032 *mt9v032)
263{
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300264 struct regmap *map = mt9v032->regmap;
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300265 int ret;
266
Laurent Pinchart70829032016-01-26 16:11:51 -0200267 gpiod_set_value_cansleep(mt9v032->reset_gpio, 1);
Markus Pargmann28d5bdb2015-12-14 12:41:51 -0200268
Lad, Prabhakar79019192014-01-17 06:22:47 -0300269 ret = clk_set_rate(mt9v032->clk, mt9v032->sysclk);
270 if (ret < 0)
271 return ret;
272
Markus Pargmann28d5bdb2015-12-14 12:41:51 -0200273 /* System clock has to be enabled before releasing the reset */
Lad, Prabhakar79019192014-01-17 06:22:47 -0300274 ret = clk_prepare_enable(mt9v032->clk);
275 if (ret)
276 return ret;
277
Laurent Pinchart3300a8f2013-07-05 07:16:02 -0300278 udelay(1);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300279
Markus Pargmann28d5bdb2015-12-14 12:41:51 -0200280 if (mt9v032->reset_gpio) {
281 gpiod_set_value_cansleep(mt9v032->reset_gpio, 0);
282
283 /* After releasing reset we need to wait 10 clock cycles
284 * before accessing the sensor over I2C. As the minimum SYSCLK
285 * frequency is 13MHz, waiting 1µs will be enough in the worst
286 * case.
287 */
288 udelay(1);
289 }
290
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300291 /* Reset the chip and stop data read out */
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300292 ret = regmap_write(map, MT9V032_RESET, 1);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300293 if (ret < 0)
Alexey Khoroshilov7df66d72017-11-24 17:04:37 -0500294 goto err;
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300295
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300296 ret = regmap_write(map, MT9V032_RESET, 0);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300297 if (ret < 0)
Alexey Khoroshilov7df66d72017-11-24 17:04:37 -0500298 goto err;
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300299
Alexey Khoroshilov7df66d72017-11-24 17:04:37 -0500300 ret = regmap_write(map, MT9V032_CHIP_CONTROL,
301 MT9V032_CHIP_CONTROL_MASTER_MODE);
302 if (ret < 0)
303 goto err;
304
305 return 0;
306
307err:
308 clk_disable_unprepare(mt9v032->clk);
309 return ret;
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300310}
311
312static void mt9v032_power_off(struct mt9v032 *mt9v032)
313{
Laurent Pinchart3300a8f2013-07-05 07:16:02 -0300314 clk_disable_unprepare(mt9v032->clk);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300315}
316
317static int __mt9v032_set_power(struct mt9v032 *mt9v032, bool on)
318{
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300319 struct regmap *map = mt9v032->regmap;
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300320 int ret;
321
322 if (!on) {
323 mt9v032_power_off(mt9v032);
324 return 0;
325 }
326
327 ret = mt9v032_power_on(mt9v032);
328 if (ret < 0)
329 return ret;
330
331 /* Configure the pixel clock polarity */
332 if (mt9v032->pdata && mt9v032->pdata->clk_pol) {
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300333 ret = regmap_write(map, mt9v032->model->data->pclk_reg,
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300334 MT9V032_PIXEL_CLOCK_INV_PXL_CLK);
335 if (ret < 0)
336 return ret;
337 }
338
339 /* Disable the noise correction algorithm and restore the controls. */
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300340 ret = regmap_write(map, MT9V032_ROW_NOISE_CORR_CONTROL, 0);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300341 if (ret < 0)
342 return ret;
343
344 return v4l2_ctrl_handler_setup(&mt9v032->ctrls);
345}
346
347/* -----------------------------------------------------------------------------
348 * V4L2 subdev video operations
349 */
350
351static struct v4l2_mbus_framefmt *
Tomi Valkeinen0d346d22021-06-10 17:55:58 +0300352__mt9v032_get_pad_format(struct mt9v032 *mt9v032,
353 struct v4l2_subdev_state *sd_state,
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300354 unsigned int pad, enum v4l2_subdev_format_whence which)
355{
356 switch (which) {
357 case V4L2_SUBDEV_FORMAT_TRY:
Tomi Valkeinen0d346d22021-06-10 17:55:58 +0300358 return v4l2_subdev_get_try_format(&mt9v032->subdev, sd_state,
359 pad);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300360 case V4L2_SUBDEV_FORMAT_ACTIVE:
361 return &mt9v032->format;
362 default:
363 return NULL;
364 }
365}
366
367static struct v4l2_rect *
Tomi Valkeinen0d346d22021-06-10 17:55:58 +0300368__mt9v032_get_pad_crop(struct mt9v032 *mt9v032,
369 struct v4l2_subdev_state *sd_state,
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300370 unsigned int pad, enum v4l2_subdev_format_whence which)
371{
372 switch (which) {
373 case V4L2_SUBDEV_FORMAT_TRY:
Tomi Valkeinen0d346d22021-06-10 17:55:58 +0300374 return v4l2_subdev_get_try_crop(&mt9v032->subdev, sd_state,
375 pad);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300376 case V4L2_SUBDEV_FORMAT_ACTIVE:
377 return &mt9v032->crop;
378 default:
379 return NULL;
380 }
381}
382
383static int mt9v032_s_stream(struct v4l2_subdev *subdev, int enable)
384{
Markus Pargmann78060d52015-12-14 12:41:52 -0200385 const u16 mode = MT9V032_CHIP_CONTROL_DOUT_ENABLE
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300386 | MT9V032_CHIP_CONTROL_SEQUENTIAL;
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300387 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300388 struct v4l2_rect *crop = &mt9v032->crop;
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300389 struct regmap *map = mt9v032->regmap;
Laurent Pinchart637f0052013-12-02 16:39:18 -0300390 unsigned int hbin;
391 unsigned int vbin;
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300392 int ret;
393
394 if (!enable)
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300395 return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, 0);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300396
397 /* Configure the window size and row/column bin */
Laurent Pinchart637f0052013-12-02 16:39:18 -0300398 hbin = fls(mt9v032->hratio) - 1;
399 vbin = fls(mt9v032->vratio) - 1;
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300400 ret = regmap_update_bits(map, MT9V032_READ_MODE,
401 ~MT9V032_READ_MODE_RESERVED,
402 hbin << MT9V032_READ_MODE_COLUMN_BIN_SHIFT |
403 vbin << MT9V032_READ_MODE_ROW_BIN_SHIFT);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300404 if (ret < 0)
405 return ret;
406
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300407 ret = regmap_write(map, MT9V032_COLUMN_START, crop->left);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300408 if (ret < 0)
409 return ret;
410
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300411 ret = regmap_write(map, MT9V032_ROW_START, crop->top);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300412 if (ret < 0)
413 return ret;
414
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300415 ret = regmap_write(map, MT9V032_WINDOW_WIDTH, crop->width);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300416 if (ret < 0)
417 return ret;
418
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300419 ret = regmap_write(map, MT9V032_WINDOW_HEIGHT, crop->height);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300420 if (ret < 0)
421 return ret;
422
Laurent Pinchart9ec670e2012-07-23 15:03:34 -0300423 ret = mt9v032_update_hblank(mt9v032);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300424 if (ret < 0)
425 return ret;
426
427 /* Switch to master "normal" mode */
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300428 return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, mode);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300429}
430
431static int mt9v032_enum_mbus_code(struct v4l2_subdev *subdev,
Tomi Valkeinen0d346d22021-06-10 17:55:58 +0300432 struct v4l2_subdev_state *sd_state,
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300433 struct v4l2_subdev_mbus_code_enum *code)
434{
Eugen Hristev1451d5a2019-11-21 08:55:24 +0100435 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
436
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300437 if (code->index > 0)
438 return -EINVAL;
439
Eugen Hristev1451d5a2019-11-21 08:55:24 +0100440 code->code = mt9v032->format.code;
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300441 return 0;
442}
443
444static int mt9v032_enum_frame_size(struct v4l2_subdev *subdev,
Tomi Valkeinen0d346d22021-06-10 17:55:58 +0300445 struct v4l2_subdev_state *sd_state,
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300446 struct v4l2_subdev_frame_size_enum *fse)
447{
Eugen Hristev1451d5a2019-11-21 08:55:24 +0100448 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
449
450 if (fse->index >= 3)
451 return -EINVAL;
452 if (mt9v032->format.code != fse->code)
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300453 return -EINVAL;
454
Laurent Pinchart637f0052013-12-02 16:39:18 -0300455 fse->min_width = MT9V032_WINDOW_WIDTH_DEF / (1 << fse->index);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300456 fse->max_width = fse->min_width;
Laurent Pinchart637f0052013-12-02 16:39:18 -0300457 fse->min_height = MT9V032_WINDOW_HEIGHT_DEF / (1 << fse->index);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300458 fse->max_height = fse->min_height;
459
460 return 0;
461}
462
463static int mt9v032_get_format(struct v4l2_subdev *subdev,
Tomi Valkeinen0d346d22021-06-10 17:55:58 +0300464 struct v4l2_subdev_state *sd_state,
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300465 struct v4l2_subdev_format *format)
466{
467 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
468
Tomi Valkeinen0d346d22021-06-10 17:55:58 +0300469 format->format = *__mt9v032_get_pad_format(mt9v032, sd_state,
470 format->pad,
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300471 format->which);
472 return 0;
473}
474
Laurent Pinchart637f0052013-12-02 16:39:18 -0300475static void mt9v032_configure_pixel_rate(struct mt9v032 *mt9v032)
Sakari Ailus41a33a02012-03-15 18:01:39 -0300476{
477 struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
478 int ret;
479
Laurent Pincharte9a50e42012-07-26 08:02:50 -0300480 ret = v4l2_ctrl_s_ctrl_int64(mt9v032->pixel_rate,
Laurent Pinchart637f0052013-12-02 16:39:18 -0300481 mt9v032->sysclk / mt9v032->hratio);
Sakari Ailus41a33a02012-03-15 18:01:39 -0300482 if (ret < 0)
483 dev_warn(&client->dev, "failed to set pixel rate (%d)\n", ret);
484}
485
Laurent Pinchart637f0052013-12-02 16:39:18 -0300486static unsigned int mt9v032_calc_ratio(unsigned int input, unsigned int output)
487{
488 /* Compute the power-of-two binning factor closest to the input size to
489 * output size ratio. Given that the output size is bounded by input/4
490 * and input, a generic implementation would be an ineffective luxury.
491 */
492 if (output * 3 > input * 2)
493 return 1;
494 if (output * 3 > input)
495 return 2;
496 return 4;
497}
498
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300499static int mt9v032_set_format(struct v4l2_subdev *subdev,
Tomi Valkeinen0d346d22021-06-10 17:55:58 +0300500 struct v4l2_subdev_state *sd_state,
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300501 struct v4l2_subdev_format *format)
502{
503 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
504 struct v4l2_mbus_framefmt *__format;
505 struct v4l2_rect *__crop;
506 unsigned int width;
507 unsigned int height;
508 unsigned int hratio;
509 unsigned int vratio;
510
Tomi Valkeinen0d346d22021-06-10 17:55:58 +0300511 __crop = __mt9v032_get_pad_crop(mt9v032, sd_state, format->pad,
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300512 format->which);
513
514 /* Clamp the width and height to avoid dividing by zero. */
Ricardo Ribaldaf90580c2013-11-26 05:31:42 -0300515 width = clamp(ALIGN(format->format.width, 2),
516 max_t(unsigned int, __crop->width / 4,
517 MT9V032_WINDOW_WIDTH_MIN),
518 __crop->width);
519 height = clamp(ALIGN(format->format.height, 2),
520 max_t(unsigned int, __crop->height / 4,
521 MT9V032_WINDOW_HEIGHT_MIN),
522 __crop->height);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300523
Laurent Pinchart637f0052013-12-02 16:39:18 -0300524 hratio = mt9v032_calc_ratio(__crop->width, width);
525 vratio = mt9v032_calc_ratio(__crop->height, height);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300526
Tomi Valkeinen0d346d22021-06-10 17:55:58 +0300527 __format = __mt9v032_get_pad_format(mt9v032, sd_state, format->pad,
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300528 format->which);
529 __format->width = __crop->width / hratio;
530 __format->height = __crop->height / vratio;
Laurent Pinchart637f0052013-12-02 16:39:18 -0300531
532 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
533 mt9v032->hratio = hratio;
534 mt9v032->vratio = vratio;
535 mt9v032_configure_pixel_rate(mt9v032);
536 }
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300537
538 format->format = *__format;
539
540 return 0;
541}
542
Hans Verkuil1a023fe2014-12-04 06:54:52 -0300543static int mt9v032_get_selection(struct v4l2_subdev *subdev,
Tomi Valkeinen0d346d22021-06-10 17:55:58 +0300544 struct v4l2_subdev_state *sd_state,
Hans Verkuil1a023fe2014-12-04 06:54:52 -0300545 struct v4l2_subdev_selection *sel)
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300546{
547 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
548
Hans Verkuil1a023fe2014-12-04 06:54:52 -0300549 if (sel->target != V4L2_SEL_TGT_CROP)
550 return -EINVAL;
551
Tomi Valkeinen0d346d22021-06-10 17:55:58 +0300552 sel->r = *__mt9v032_get_pad_crop(mt9v032, sd_state, sel->pad,
553 sel->which);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300554 return 0;
555}
556
Hans Verkuil1a023fe2014-12-04 06:54:52 -0300557static int mt9v032_set_selection(struct v4l2_subdev *subdev,
Tomi Valkeinen0d346d22021-06-10 17:55:58 +0300558 struct v4l2_subdev_state *sd_state,
Hans Verkuil1a023fe2014-12-04 06:54:52 -0300559 struct v4l2_subdev_selection *sel)
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300560{
561 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
562 struct v4l2_mbus_framefmt *__format;
563 struct v4l2_rect *__crop;
564 struct v4l2_rect rect;
565
Hans Verkuil1a023fe2014-12-04 06:54:52 -0300566 if (sel->target != V4L2_SEL_TGT_CROP)
567 return -EINVAL;
568
Laurent Pinchart86cf7862010-11-28 15:07:20 -0300569 /* Clamp the crop rectangle boundaries and align them to a non multiple
570 * of 2 pixels to ensure a GRBG Bayer pattern.
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300571 */
Hans Verkuil1a023fe2014-12-04 06:54:52 -0300572 rect.left = clamp(ALIGN(sel->r.left + 1, 2) - 1,
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300573 MT9V032_COLUMN_START_MIN,
574 MT9V032_COLUMN_START_MAX);
Hans Verkuil1a023fe2014-12-04 06:54:52 -0300575 rect.top = clamp(ALIGN(sel->r.top + 1, 2) - 1,
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300576 MT9V032_ROW_START_MIN,
577 MT9V032_ROW_START_MAX);
Hans Verkuil1a023fe2014-12-04 06:54:52 -0300578 rect.width = clamp_t(unsigned int, ALIGN(sel->r.width, 2),
Ricardo Ribaldaf90580c2013-11-26 05:31:42 -0300579 MT9V032_WINDOW_WIDTH_MIN,
580 MT9V032_WINDOW_WIDTH_MAX);
Hans Verkuil1a023fe2014-12-04 06:54:52 -0300581 rect.height = clamp_t(unsigned int, ALIGN(sel->r.height, 2),
Ricardo Ribaldaf90580c2013-11-26 05:31:42 -0300582 MT9V032_WINDOW_HEIGHT_MIN,
583 MT9V032_WINDOW_HEIGHT_MAX);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300584
Ricardo Ribaldaf90580c2013-11-26 05:31:42 -0300585 rect.width = min_t(unsigned int,
586 rect.width, MT9V032_PIXEL_ARRAY_WIDTH - rect.left);
587 rect.height = min_t(unsigned int,
588 rect.height, MT9V032_PIXEL_ARRAY_HEIGHT - rect.top);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300589
Tomi Valkeinen0d346d22021-06-10 17:55:58 +0300590 __crop = __mt9v032_get_pad_crop(mt9v032, sd_state, sel->pad,
591 sel->which);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300592
593 if (rect.width != __crop->width || rect.height != __crop->height) {
594 /* Reset the output image size if the crop rectangle size has
595 * been modified.
596 */
Tomi Valkeinen0d346d22021-06-10 17:55:58 +0300597 __format = __mt9v032_get_pad_format(mt9v032, sd_state,
598 sel->pad,
Hans Verkuil1a023fe2014-12-04 06:54:52 -0300599 sel->which);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300600 __format->width = rect.width;
601 __format->height = rect.height;
Hans Verkuil1a023fe2014-12-04 06:54:52 -0300602 if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
Laurent Pinchart637f0052013-12-02 16:39:18 -0300603 mt9v032->hratio = 1;
604 mt9v032->vratio = 1;
605 mt9v032_configure_pixel_rate(mt9v032);
606 }
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300607 }
608
609 *__crop = rect;
Hans Verkuil1a023fe2014-12-04 06:54:52 -0300610 sel->r = rect;
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300611
612 return 0;
613}
614
615/* -----------------------------------------------------------------------------
616 * V4L2 subdev control operations
617 */
618
Lad, Prabhakarb28d7012012-09-25 09:35:43 -0300619#define V4L2_CID_TEST_PATTERN_COLOR (V4L2_CID_USER_BASE | 0x1001)
Markus Pargmann81ea4822015-12-14 12:41:53 -0200620/*
621 * Value between 1 and 64 to set the desired bin. This is effectively a measure
622 * of how bright the image is supposed to be. Both AGC and AEC try to reach
623 * this.
624 */
625#define V4L2_CID_AEGC_DESIRED_BIN (V4L2_CID_USER_BASE | 0x1002)
626/*
627 * LPF is the low pass filter capability of the chip. Both AEC and AGC have
628 * this setting. This limits the speed in which AGC/AEC adjust their settings.
629 * Possible values are 0-2. 0 means no LPF. For 1 and 2 this equation is used:
630 *
631 * if |(calculated new exp - current exp)| > (current exp / 4)
632 * next exp = calculated new exp
633 * else
634 * next exp = current exp + ((calculated new exp - current exp) / 2^LPF)
635 */
636#define V4L2_CID_AEC_LPF (V4L2_CID_USER_BASE | 0x1003)
637#define V4L2_CID_AGC_LPF (V4L2_CID_USER_BASE | 0x1004)
638/*
639 * Value between 0 and 15. This is the number of frames being skipped before
640 * updating the auto exposure/gain.
641 */
642#define V4L2_CID_AEC_UPDATE_INTERVAL (V4L2_CID_USER_BASE | 0x1005)
643#define V4L2_CID_AGC_UPDATE_INTERVAL (V4L2_CID_USER_BASE | 0x1006)
644/*
645 * Maximum shutter width used for AEC.
646 */
647#define V4L2_CID_AEC_MAX_SHUTTER_WIDTH (V4L2_CID_USER_BASE | 0x1007)
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300648
649static int mt9v032_s_ctrl(struct v4l2_ctrl *ctrl)
650{
651 struct mt9v032 *mt9v032 =
652 container_of(ctrl->handler, struct mt9v032, ctrls);
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300653 struct regmap *map = mt9v032->regmap;
Laurent Pincharte9a50e42012-07-26 08:02:50 -0300654 u32 freq;
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300655 u16 data;
656
657 switch (ctrl->id) {
658 case V4L2_CID_AUTOGAIN:
659 return mt9v032_update_aec_agc(mt9v032, MT9V032_AGC_ENABLE,
660 ctrl->val);
661
662 case V4L2_CID_GAIN:
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300663 return regmap_write(map, MT9V032_ANALOG_GAIN, ctrl->val);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300664
665 case V4L2_CID_EXPOSURE_AUTO:
666 return mt9v032_update_aec_agc(mt9v032, MT9V032_AEC_ENABLE,
Kartik Mohta5c375982012-05-02 19:19:08 -0300667 !ctrl->val);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300668
669 case V4L2_CID_EXPOSURE:
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300670 return regmap_write(map, MT9V032_TOTAL_SHUTTER_WIDTH,
671 ctrl->val);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300672
Laurent Pinchart9ec670e2012-07-23 15:03:34 -0300673 case V4L2_CID_HBLANK:
674 mt9v032->hblank = ctrl->val;
675 return mt9v032_update_hblank(mt9v032);
676
677 case V4L2_CID_VBLANK:
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300678 return regmap_write(map, MT9V032_VERTICAL_BLANKING,
679 ctrl->val);
Laurent Pinchart9ec670e2012-07-23 15:03:34 -0300680
Laurent Pincharte9a50e42012-07-26 08:02:50 -0300681 case V4L2_CID_PIXEL_RATE:
682 case V4L2_CID_LINK_FREQ:
683 if (mt9v032->link_freq == NULL)
684 break;
685
686 freq = mt9v032->pdata->link_freqs[mt9v032->link_freq->val];
Hans Verkuil2a9ec372014-04-27 03:38:13 -0300687 *mt9v032->pixel_rate->p_new.p_s64 = freq;
Laurent Pincharte9a50e42012-07-26 08:02:50 -0300688 mt9v032->sysclk = freq;
689 break;
690
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300691 case V4L2_CID_TEST_PATTERN:
Lad, Prabhakarb28d7012012-09-25 09:35:43 -0300692 switch (mt9v032->test_pattern->val) {
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300693 case 0:
694 data = 0;
695 break;
696 case 1:
697 data = MT9V032_TEST_PATTERN_GRAY_VERTICAL
698 | MT9V032_TEST_PATTERN_ENABLE;
699 break;
700 case 2:
701 data = MT9V032_TEST_PATTERN_GRAY_HORIZONTAL
702 | MT9V032_TEST_PATTERN_ENABLE;
703 break;
704 case 3:
705 data = MT9V032_TEST_PATTERN_GRAY_DIAGONAL
706 | MT9V032_TEST_PATTERN_ENABLE;
707 break;
708 default:
Lad, Prabhakarb28d7012012-09-25 09:35:43 -0300709 data = (mt9v032->test_pattern_color->val <<
710 MT9V032_TEST_PATTERN_DATA_SHIFT)
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300711 | MT9V032_TEST_PATTERN_USE_DATA
712 | MT9V032_TEST_PATTERN_ENABLE
713 | MT9V032_TEST_PATTERN_FLIP;
714 break;
715 }
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300716 return regmap_write(map, MT9V032_TEST_PATTERN, data);
Markus Pargmann81ea4822015-12-14 12:41:53 -0200717
718 case V4L2_CID_AEGC_DESIRED_BIN:
719 return regmap_write(map, MT9V032_AEGC_DESIRED_BIN, ctrl->val);
720
721 case V4L2_CID_AEC_LPF:
722 return regmap_write(map, MT9V032_AEC_LPF, ctrl->val);
723
724 case V4L2_CID_AGC_LPF:
725 return regmap_write(map, MT9V032_AGC_LPF, ctrl->val);
726
727 case V4L2_CID_AEC_UPDATE_INTERVAL:
728 return regmap_write(map, MT9V032_AEC_UPDATE_FREQUENCY,
729 ctrl->val);
730
731 case V4L2_CID_AGC_UPDATE_INTERVAL:
732 return regmap_write(map, MT9V032_AGC_UPDATE_FREQUENCY,
733 ctrl->val);
734
735 case V4L2_CID_AEC_MAX_SHUTTER_WIDTH:
736 return regmap_write(map,
737 mt9v032->model->data->aec_max_shutter_reg,
738 ctrl->val);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300739 }
740
741 return 0;
742}
743
Julia Lawall217bdb02015-11-13 20:05:17 -0200744static const struct v4l2_ctrl_ops mt9v032_ctrl_ops = {
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300745 .s_ctrl = mt9v032_s_ctrl,
746};
747
Lad, Prabhakarb28d7012012-09-25 09:35:43 -0300748static const char * const mt9v032_test_pattern_menu[] = {
749 "Disabled",
750 "Gray Vertical Shade",
751 "Gray Horizontal Shade",
752 "Gray Diagonal Shade",
753 "Plain",
754};
755
756static const struct v4l2_ctrl_config mt9v032_test_pattern_color = {
757 .ops = &mt9v032_ctrl_ops,
758 .id = V4L2_CID_TEST_PATTERN_COLOR,
759 .type = V4L2_CTRL_TYPE_INTEGER,
760 .name = "Test Pattern Color",
761 .min = 0,
762 .max = 1023,
763 .step = 1,
764 .def = 0,
765 .flags = 0,
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300766};
767
Markus Pargmann81ea4822015-12-14 12:41:53 -0200768static const struct v4l2_ctrl_config mt9v032_aegc_controls[] = {
769 {
770 .ops = &mt9v032_ctrl_ops,
771 .id = V4L2_CID_AEGC_DESIRED_BIN,
772 .type = V4L2_CTRL_TYPE_INTEGER,
773 .name = "AEC/AGC Desired Bin",
774 .min = 1,
775 .max = 64,
776 .step = 1,
777 .def = 58,
778 .flags = 0,
779 }, {
780 .ops = &mt9v032_ctrl_ops,
781 .id = V4L2_CID_AEC_LPF,
782 .type = V4L2_CTRL_TYPE_INTEGER,
783 .name = "AEC Low Pass Filter",
784 .min = 0,
785 .max = 2,
786 .step = 1,
787 .def = 0,
788 .flags = 0,
789 }, {
790 .ops = &mt9v032_ctrl_ops,
791 .id = V4L2_CID_AGC_LPF,
792 .type = V4L2_CTRL_TYPE_INTEGER,
793 .name = "AGC Low Pass Filter",
794 .min = 0,
795 .max = 2,
796 .step = 1,
797 .def = 2,
798 .flags = 0,
799 }, {
800 .ops = &mt9v032_ctrl_ops,
801 .id = V4L2_CID_AEC_UPDATE_INTERVAL,
802 .type = V4L2_CTRL_TYPE_INTEGER,
803 .name = "AEC Update Interval",
804 .min = 0,
805 .max = 16,
806 .step = 1,
807 .def = 2,
808 .flags = 0,
809 }, {
810 .ops = &mt9v032_ctrl_ops,
811 .id = V4L2_CID_AGC_UPDATE_INTERVAL,
812 .type = V4L2_CTRL_TYPE_INTEGER,
813 .name = "AGC Update Interval",
814 .min = 0,
815 .max = 16,
816 .step = 1,
817 .def = 2,
818 .flags = 0,
819 }
820};
821
822static const struct v4l2_ctrl_config mt9v032_aec_max_shutter_width = {
823 .ops = &mt9v032_ctrl_ops,
824 .id = V4L2_CID_AEC_MAX_SHUTTER_WIDTH,
825 .type = V4L2_CTRL_TYPE_INTEGER,
826 .name = "AEC Max Shutter Width",
827 .min = 1,
828 .max = 2047,
829 .step = 1,
830 .def = 480,
831 .flags = 0,
832};
833
834static const struct v4l2_ctrl_config mt9v034_aec_max_shutter_width = {
835 .ops = &mt9v032_ctrl_ops,
836 .id = V4L2_CID_AEC_MAX_SHUTTER_WIDTH,
837 .type = V4L2_CTRL_TYPE_INTEGER,
838 .name = "AEC Max Shutter Width",
839 .min = 1,
840 .max = 32765,
841 .step = 1,
842 .def = 480,
843 .flags = 0,
844};
845
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300846/* -----------------------------------------------------------------------------
847 * V4L2 subdev core operations
848 */
849
850static int mt9v032_set_power(struct v4l2_subdev *subdev, int on)
851{
852 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
853 int ret = 0;
854
855 mutex_lock(&mt9v032->power_lock);
856
857 /* If the power count is modified from 0 to != 0 or from != 0 to 0,
858 * update the power state.
859 */
860 if (mt9v032->power_count == !on) {
861 ret = __mt9v032_set_power(mt9v032, !!on);
862 if (ret < 0)
863 goto done;
864 }
865
866 /* Update the power count. */
867 mt9v032->power_count += on ? 1 : -1;
868 WARN_ON(mt9v032->power_count < 0);
869
870done:
871 mutex_unlock(&mt9v032->power_lock);
872 return ret;
873}
874
875/* -----------------------------------------------------------------------------
876 * V4L2 subdev internal operations
877 */
878
879static int mt9v032_registered(struct v4l2_subdev *subdev)
880{
881 struct i2c_client *client = v4l2_get_subdevdata(subdev);
882 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
Laurent Pinchart0a466b62013-12-02 11:59:52 -0300883 unsigned int i;
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300884 u32 version;
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300885 int ret;
886
887 dev_info(&client->dev, "Probing MT9V032 at address 0x%02x\n",
888 client->addr);
889
890 ret = mt9v032_power_on(mt9v032);
891 if (ret < 0) {
892 dev_err(&client->dev, "MT9V032 power up failed\n");
893 return ret;
894 }
895
896 /* Read and check the sensor version */
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300897 ret = regmap_read(mt9v032->regmap, MT9V032_CHIP_VERSION, &version);
Alexey Khoroshilov7df66d72017-11-24 17:04:37 -0500898
899 mt9v032_power_off(mt9v032);
900
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300901 if (ret < 0) {
Laurent Pinchart0a466b62013-12-02 11:59:52 -0300902 dev_err(&client->dev, "Failed reading chip version\n");
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300903 return ret;
Laurent Pinchart0a466b62013-12-02 11:59:52 -0300904 }
905
906 for (i = 0; i < ARRAY_SIZE(mt9v032_versions); ++i) {
907 if (mt9v032_versions[i].version == version) {
908 mt9v032->version = &mt9v032_versions[i];
909 break;
910 }
911 }
912
913 if (mt9v032->version == NULL) {
914 dev_err(&client->dev, "Unsupported chip version 0x%04x\n",
915 version);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300916 return -ENODEV;
917 }
918
Laurent Pinchart0a466b62013-12-02 11:59:52 -0300919 dev_info(&client->dev, "%s detected at address 0x%02x\n",
920 mt9v032->version->name, client->addr);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300921
Laurent Pinchart637f0052013-12-02 16:39:18 -0300922 mt9v032_configure_pixel_rate(mt9v032);
Sakari Ailus41a33a02012-03-15 18:01:39 -0300923
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300924 return ret;
925}
926
927static int mt9v032_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
928{
Laurent Pinchart220ddc72013-12-04 15:31:13 -0300929 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300930 struct v4l2_mbus_framefmt *format;
931 struct v4l2_rect *crop;
932
Tomi Valkeinen0d346d22021-06-10 17:55:58 +0300933 crop = v4l2_subdev_get_try_crop(subdev, fh->state, 0);
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300934 crop->left = MT9V032_COLUMN_START_DEF;
935 crop->top = MT9V032_ROW_START_DEF;
936 crop->width = MT9V032_WINDOW_WIDTH_DEF;
937 crop->height = MT9V032_WINDOW_HEIGHT_DEF;
938
Tomi Valkeinen0d346d22021-06-10 17:55:58 +0300939 format = v4l2_subdev_get_try_format(subdev, fh->state, 0);
Laurent Pinchart220ddc72013-12-04 15:31:13 -0300940
941 if (mt9v032->model->color)
Boris BREZILLONf5fe58f2014-11-10 14:28:29 -0300942 format->code = MEDIA_BUS_FMT_SGRBG10_1X10;
Laurent Pinchart220ddc72013-12-04 15:31:13 -0300943 else
Boris BREZILLONf5fe58f2014-11-10 14:28:29 -0300944 format->code = MEDIA_BUS_FMT_Y10_1X10;
Laurent Pinchart220ddc72013-12-04 15:31:13 -0300945
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300946 format->width = MT9V032_WINDOW_WIDTH_DEF;
947 format->height = MT9V032_WINDOW_HEIGHT_DEF;
948 format->field = V4L2_FIELD_NONE;
949 format->colorspace = V4L2_COLORSPACE_SRGB;
950
951 return mt9v032_set_power(subdev, 1);
952}
953
954static int mt9v032_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
955{
956 return mt9v032_set_power(subdev, 0);
957}
958
Bhumika Goyal7c137c62016-12-12 05:45:32 -0200959static const struct v4l2_subdev_core_ops mt9v032_subdev_core_ops = {
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300960 .s_power = mt9v032_set_power,
961};
962
Bhumika Goyal7c137c62016-12-12 05:45:32 -0200963static const struct v4l2_subdev_video_ops mt9v032_subdev_video_ops = {
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300964 .s_stream = mt9v032_s_stream,
965};
966
Bhumika Goyal7c137c62016-12-12 05:45:32 -0200967static const struct v4l2_subdev_pad_ops mt9v032_subdev_pad_ops = {
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300968 .enum_mbus_code = mt9v032_enum_mbus_code,
969 .enum_frame_size = mt9v032_enum_frame_size,
970 .get_fmt = mt9v032_get_format,
971 .set_fmt = mt9v032_set_format,
Hans Verkuil1a023fe2014-12-04 06:54:52 -0300972 .get_selection = mt9v032_get_selection,
973 .set_selection = mt9v032_set_selection,
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300974};
975
Bhumika Goyal7c137c62016-12-12 05:45:32 -0200976static const struct v4l2_subdev_ops mt9v032_subdev_ops = {
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300977 .core = &mt9v032_subdev_core_ops,
978 .video = &mt9v032_subdev_video_ops,
979 .pad = &mt9v032_subdev_pad_ops,
980};
981
982static const struct v4l2_subdev_internal_ops mt9v032_subdev_internal_ops = {
983 .registered = mt9v032_registered,
984 .open = mt9v032_open,
985 .close = mt9v032_close,
986};
987
Philipp Zabel80b44ef2014-06-04 13:57:03 -0300988static const struct regmap_config mt9v032_regmap_config = {
989 .reg_bits = 8,
990 .val_bits = 16,
991 .max_register = 0xff,
992 .cache_type = REGCACHE_RBTREE,
993};
994
Detlev Casanova0f2ce162011-04-05 09:06:21 -0300995/* -----------------------------------------------------------------------------
996 * Driver initialization and probing
997 */
998
Laurent Pinchartf2272e12014-01-01 14:40:35 -0300999static struct mt9v032_platform_data *
1000mt9v032_get_pdata(struct i2c_client *client)
1001{
Hans Verkuil8e8a6b22015-07-28 05:33:55 -03001002 struct mt9v032_platform_data *pdata = NULL;
Sakari Ailus60359a22018-07-31 05:15:50 -04001003 struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 };
Laurent Pinchartf2272e12014-01-01 14:40:35 -03001004 struct device_node *np;
1005 struct property *prop;
1006
1007 if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
1008 return client->dev.platform_data;
1009
1010 np = of_graph_get_next_endpoint(client->dev.of_node, NULL);
1011 if (!np)
1012 return NULL;
1013
Sakari Ailus859969b2016-08-26 20:17:25 -03001014 if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &endpoint) < 0)
Laurent Pinchartf2272e12014-01-01 14:40:35 -03001015 goto done;
1016
1017 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
1018 if (!pdata)
1019 goto done;
1020
1021 prop = of_find_property(np, "link-frequencies", NULL);
1022 if (prop) {
1023 u64 *link_freqs;
1024 size_t size = prop->length / sizeof(*link_freqs);
1025
1026 link_freqs = devm_kcalloc(&client->dev, size,
1027 sizeof(*link_freqs), GFP_KERNEL);
1028 if (!link_freqs)
1029 goto done;
1030
1031 if (of_property_read_u64_array(np, "link-frequencies",
1032 link_freqs, size) < 0)
1033 goto done;
1034
1035 pdata->link_freqs = link_freqs;
1036 pdata->link_def_freq = link_freqs[0];
1037 }
1038
1039 pdata->clk_pol = !!(endpoint.bus.parallel.flags &
1040 V4L2_MBUS_PCLK_SAMPLE_RISING);
1041
1042done:
1043 of_node_put(np);
1044 return pdata;
1045}
1046
Detlev Casanova0f2ce162011-04-05 09:06:21 -03001047static int mt9v032_probe(struct i2c_client *client,
1048 const struct i2c_device_id *did)
1049{
Laurent Pinchartf2272e12014-01-01 14:40:35 -03001050 struct mt9v032_platform_data *pdata = mt9v032_get_pdata(client);
Detlev Casanova0f2ce162011-04-05 09:06:21 -03001051 struct mt9v032 *mt9v032;
1052 unsigned int i;
1053 int ret;
1054
Laurent Pinchartc02b2112013-05-02 08:29:43 -03001055 mt9v032 = devm_kzalloc(&client->dev, sizeof(*mt9v032), GFP_KERNEL);
Detlev Casanova0f2ce162011-04-05 09:06:21 -03001056 if (!mt9v032)
1057 return -ENOMEM;
1058
Philipp Zabel80b44ef2014-06-04 13:57:03 -03001059 mt9v032->regmap = devm_regmap_init_i2c(client, &mt9v032_regmap_config);
1060 if (IS_ERR(mt9v032->regmap))
1061 return PTR_ERR(mt9v032->regmap);
1062
Laurent Pinchart3300a8f2013-07-05 07:16:02 -03001063 mt9v032->clk = devm_clk_get(&client->dev, NULL);
1064 if (IS_ERR(mt9v032->clk))
1065 return PTR_ERR(mt9v032->clk);
1066
Markus Pargmann28d5bdb2015-12-14 12:41:51 -02001067 mt9v032->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1068 GPIOD_OUT_HIGH);
1069 if (IS_ERR(mt9v032->reset_gpio))
1070 return PTR_ERR(mt9v032->reset_gpio);
1071
1072 mt9v032->standby_gpio = devm_gpiod_get_optional(&client->dev, "standby",
1073 GPIOD_OUT_LOW);
1074 if (IS_ERR(mt9v032->standby_gpio))
1075 return PTR_ERR(mt9v032->standby_gpio);
1076
Detlev Casanova0f2ce162011-04-05 09:06:21 -03001077 mutex_init(&mt9v032->power_lock);
Laurent Pincharte9a50e42012-07-26 08:02:50 -03001078 mt9v032->pdata = pdata;
Laurent Pinchart220ddc72013-12-04 15:31:13 -03001079 mt9v032->model = (const void *)did->driver_data;
Detlev Casanova0f2ce162011-04-05 09:06:21 -03001080
Markus Pargmann81ea4822015-12-14 12:41:53 -02001081 v4l2_ctrl_handler_init(&mt9v032->ctrls, 11 +
1082 ARRAY_SIZE(mt9v032_aegc_controls));
Detlev Casanova0f2ce162011-04-05 09:06:21 -03001083
1084 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1085 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1086 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1087 V4L2_CID_GAIN, MT9V032_ANALOG_GAIN_MIN,
1088 MT9V032_ANALOG_GAIN_MAX, 1, MT9V032_ANALOG_GAIN_DEF);
1089 v4l2_ctrl_new_std_menu(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1090 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0,
1091 V4L2_EXPOSURE_AUTO);
1092 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
Laurent Pinchart0a466b62013-12-02 11:59:52 -03001093 V4L2_CID_EXPOSURE, mt9v032->model->data->min_shutter,
1094 mt9v032->model->data->max_shutter, 1,
Detlev Casanova0f2ce162011-04-05 09:06:21 -03001095 MT9V032_TOTAL_SHUTTER_WIDTH_DEF);
Laurent Pinchart9ec670e2012-07-23 15:03:34 -03001096 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
Laurent Pinchart0a466b62013-12-02 11:59:52 -03001097 V4L2_CID_HBLANK, mt9v032->model->data->min_hblank,
Laurent Pinchart9ec670e2012-07-23 15:03:34 -03001098 MT9V032_HORIZONTAL_BLANKING_MAX, 1,
1099 MT9V032_HORIZONTAL_BLANKING_DEF);
1100 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
Laurent Pinchart0a466b62013-12-02 11:59:52 -03001101 V4L2_CID_VBLANK, mt9v032->model->data->min_vblank,
1102 mt9v032->model->data->max_vblank, 1,
Laurent Pinchart9ec670e2012-07-23 15:03:34 -03001103 MT9V032_VERTICAL_BLANKING_DEF);
Lad, Prabhakarb28d7012012-09-25 09:35:43 -03001104 mt9v032->test_pattern = v4l2_ctrl_new_std_menu_items(&mt9v032->ctrls,
1105 &mt9v032_ctrl_ops, V4L2_CID_TEST_PATTERN,
1106 ARRAY_SIZE(mt9v032_test_pattern_menu) - 1, 0, 0,
1107 mt9v032_test_pattern_menu);
1108 mt9v032->test_pattern_color = v4l2_ctrl_new_custom(&mt9v032->ctrls,
1109 &mt9v032_test_pattern_color, NULL);
1110
Markus Pargmann81ea4822015-12-14 12:41:53 -02001111 v4l2_ctrl_new_custom(&mt9v032->ctrls,
1112 mt9v032->model->data->aec_max_shutter_v4l2_ctrl,
1113 NULL);
1114 for (i = 0; i < ARRAY_SIZE(mt9v032_aegc_controls); ++i)
1115 v4l2_ctrl_new_custom(&mt9v032->ctrls, &mt9v032_aegc_controls[i],
1116 NULL);
1117
Lad, Prabhakarb28d7012012-09-25 09:35:43 -03001118 v4l2_ctrl_cluster(2, &mt9v032->test_pattern);
Laurent Pincharte9a50e42012-07-26 08:02:50 -03001119
Sakari Ailus41a33a02012-03-15 18:01:39 -03001120 mt9v032->pixel_rate =
1121 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
Hans Verkuil0ba2aeb2014-04-16 09:41:25 -03001122 V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1);
Detlev Casanova0f2ce162011-04-05 09:06:21 -03001123
Laurent Pincharte9a50e42012-07-26 08:02:50 -03001124 if (pdata && pdata->link_freqs) {
1125 unsigned int def = 0;
1126
1127 for (i = 0; pdata->link_freqs[i]; ++i) {
1128 if (pdata->link_freqs[i] == pdata->link_def_freq)
1129 def = i;
1130 }
1131
1132 mt9v032->link_freq =
1133 v4l2_ctrl_new_int_menu(&mt9v032->ctrls,
1134 &mt9v032_ctrl_ops,
1135 V4L2_CID_LINK_FREQ, i - 1, def,
1136 pdata->link_freqs);
1137 v4l2_ctrl_cluster(2, &mt9v032->link_freq);
1138 }
1139
Detlev Casanova0f2ce162011-04-05 09:06:21 -03001140
1141 mt9v032->subdev.ctrl_handler = &mt9v032->ctrls;
1142
Laurent Pinchart2d012092014-01-01 14:40:35 -03001143 if (mt9v032->ctrls.error) {
1144 dev_err(&client->dev, "control initialization error %d\n",
1145 mt9v032->ctrls.error);
1146 ret = mt9v032->ctrls.error;
1147 goto err;
1148 }
Detlev Casanova0f2ce162011-04-05 09:06:21 -03001149
1150 mt9v032->crop.left = MT9V032_COLUMN_START_DEF;
1151 mt9v032->crop.top = MT9V032_ROW_START_DEF;
1152 mt9v032->crop.width = MT9V032_WINDOW_WIDTH_DEF;
1153 mt9v032->crop.height = MT9V032_WINDOW_HEIGHT_DEF;
1154
Laurent Pinchart220ddc72013-12-04 15:31:13 -03001155 if (mt9v032->model->color)
Boris BREZILLONf5fe58f2014-11-10 14:28:29 -03001156 mt9v032->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
Laurent Pinchart220ddc72013-12-04 15:31:13 -03001157 else
Boris BREZILLONf5fe58f2014-11-10 14:28:29 -03001158 mt9v032->format.code = MEDIA_BUS_FMT_Y10_1X10;
Laurent Pinchart220ddc72013-12-04 15:31:13 -03001159
Detlev Casanova0f2ce162011-04-05 09:06:21 -03001160 mt9v032->format.width = MT9V032_WINDOW_WIDTH_DEF;
1161 mt9v032->format.height = MT9V032_WINDOW_HEIGHT_DEF;
1162 mt9v032->format.field = V4L2_FIELD_NONE;
1163 mt9v032->format.colorspace = V4L2_COLORSPACE_SRGB;
1164
Laurent Pinchart637f0052013-12-02 16:39:18 -03001165 mt9v032->hratio = 1;
1166 mt9v032->vratio = 1;
1167
Detlev Casanova0f2ce162011-04-05 09:06:21 -03001168 mt9v032->aec_agc = MT9V032_AEC_ENABLE | MT9V032_AGC_ENABLE;
Laurent Pinchart9ec670e2012-07-23 15:03:34 -03001169 mt9v032->hblank = MT9V032_HORIZONTAL_BLANKING_DEF;
Laurent Pincharte9a50e42012-07-26 08:02:50 -03001170 mt9v032->sysclk = MT9V032_SYSCLK_FREQ_DEF;
Detlev Casanova0f2ce162011-04-05 09:06:21 -03001171
1172 v4l2_i2c_subdev_init(&mt9v032->subdev, client, &mt9v032_subdev_ops);
1173 mt9v032->subdev.internal_ops = &mt9v032_subdev_internal_ops;
1174 mt9v032->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1175
Hans Verkuil173bf6e2018-06-18 05:10:28 -04001176 mt9v032->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
Detlev Casanova0f2ce162011-04-05 09:06:21 -03001177 mt9v032->pad.flags = MEDIA_PAD_FL_SOURCE;
Mauro Carvalho Chehabab22e772015-12-11 07:44:40 -02001178 ret = media_entity_pads_init(&mt9v032->subdev.entity, 1, &mt9v032->pad);
Laurent Pinchartc02b2112013-05-02 08:29:43 -03001179 if (ret < 0)
Philipp Zabel94b76ce2014-06-04 13:57:02 -03001180 goto err;
Detlev Casanova0f2ce162011-04-05 09:06:21 -03001181
Philipp Zabel94b76ce2014-06-04 13:57:02 -03001182 mt9v032->subdev.dev = &client->dev;
1183 ret = v4l2_async_register_subdev(&mt9v032->subdev);
1184 if (ret < 0)
1185 goto err;
1186
1187 return 0;
1188
1189err:
1190 media_entity_cleanup(&mt9v032->subdev.entity);
1191 v4l2_ctrl_handler_free(&mt9v032->ctrls);
Detlev Casanova0f2ce162011-04-05 09:06:21 -03001192 return ret;
1193}
1194
1195static int mt9v032_remove(struct i2c_client *client)
1196{
1197 struct v4l2_subdev *subdev = i2c_get_clientdata(client);
1198 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
1199
Philipp Zabel94b76ce2014-06-04 13:57:02 -03001200 v4l2_async_unregister_subdev(subdev);
Laurent Pinchart94625502013-05-02 08:34:30 -03001201 v4l2_ctrl_handler_free(&mt9v032->ctrls);
Detlev Casanova0f2ce162011-04-05 09:06:21 -03001202 media_entity_cleanup(&subdev->entity);
Laurent Pinchart94625502013-05-02 08:34:30 -03001203
Detlev Casanova0f2ce162011-04-05 09:06:21 -03001204 return 0;
1205}
1206
Markus Pargmann81ea4822015-12-14 12:41:53 -02001207static const struct mt9v032_model_data mt9v032_model_data[] = {
1208 {
1209 /* MT9V022, MT9V032 revisions 1/2/3 */
1210 .min_row_time = 660,
1211 .min_hblank = MT9V032_HORIZONTAL_BLANKING_MIN,
1212 .min_vblank = MT9V032_VERTICAL_BLANKING_MIN,
1213 .max_vblank = MT9V032_VERTICAL_BLANKING_MAX,
1214 .min_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MIN,
1215 .max_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MAX,
1216 .pclk_reg = MT9V032_PIXEL_CLOCK,
1217 .aec_max_shutter_reg = MT9V032_AEC_MAX_SHUTTER_WIDTH,
1218 .aec_max_shutter_v4l2_ctrl = &mt9v032_aec_max_shutter_width,
1219 }, {
1220 /* MT9V024, MT9V034 */
1221 .min_row_time = 690,
1222 .min_hblank = MT9V034_HORIZONTAL_BLANKING_MIN,
1223 .min_vblank = MT9V034_VERTICAL_BLANKING_MIN,
1224 .max_vblank = MT9V034_VERTICAL_BLANKING_MAX,
1225 .min_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MIN,
1226 .max_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MAX,
1227 .pclk_reg = MT9V034_PIXEL_CLOCK,
1228 .aec_max_shutter_reg = MT9V034_AEC_MAX_SHUTTER_WIDTH,
1229 .aec_max_shutter_v4l2_ctrl = &mt9v034_aec_max_shutter_width,
1230 },
1231};
1232
1233static const struct mt9v032_model_info mt9v032_models[] = {
1234 [MT9V032_MODEL_V022_COLOR] = {
1235 .data = &mt9v032_model_data[0],
1236 .color = true,
1237 },
1238 [MT9V032_MODEL_V022_MONO] = {
1239 .data = &mt9v032_model_data[0],
1240 .color = false,
1241 },
1242 [MT9V032_MODEL_V024_COLOR] = {
1243 .data = &mt9v032_model_data[1],
1244 .color = true,
1245 },
1246 [MT9V032_MODEL_V024_MONO] = {
1247 .data = &mt9v032_model_data[1],
1248 .color = false,
1249 },
1250 [MT9V032_MODEL_V032_COLOR] = {
1251 .data = &mt9v032_model_data[0],
1252 .color = true,
1253 },
1254 [MT9V032_MODEL_V032_MONO] = {
1255 .data = &mt9v032_model_data[0],
1256 .color = false,
1257 },
1258 [MT9V032_MODEL_V034_COLOR] = {
1259 .data = &mt9v032_model_data[1],
1260 .color = true,
1261 },
1262 [MT9V032_MODEL_V034_MONO] = {
1263 .data = &mt9v032_model_data[1],
1264 .color = false,
1265 },
1266};
1267
Detlev Casanova0f2ce162011-04-05 09:06:21 -03001268static const struct i2c_device_id mt9v032_id[] = {
Philipp Zabeld8dde6c2014-06-03 06:35:54 -03001269 { "mt9v022", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V022_COLOR] },
1270 { "mt9v022m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V022_MONO] },
1271 { "mt9v024", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V024_COLOR] },
1272 { "mt9v024m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V024_MONO] },
Laurent Pinchartdaecfeb2013-12-02 12:01:03 -03001273 { "mt9v032", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V032_COLOR] },
1274 { "mt9v032m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V032_MONO] },
1275 { "mt9v034", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V034_COLOR] },
1276 { "mt9v034m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V034_MONO] },
Detlev Casanova0f2ce162011-04-05 09:06:21 -03001277 { }
1278};
1279MODULE_DEVICE_TABLE(i2c, mt9v032_id);
1280
Laurent Pinchartf2272e12014-01-01 14:40:35 -03001281#if IS_ENABLED(CONFIG_OF)
1282static const struct of_device_id mt9v032_of_match[] = {
1283 { .compatible = "aptina,mt9v022" },
1284 { .compatible = "aptina,mt9v022m" },
1285 { .compatible = "aptina,mt9v024" },
1286 { .compatible = "aptina,mt9v024m" },
1287 { .compatible = "aptina,mt9v032" },
1288 { .compatible = "aptina,mt9v032m" },
1289 { .compatible = "aptina,mt9v034" },
1290 { .compatible = "aptina,mt9v034m" },
1291 { /* Sentinel */ }
1292};
1293MODULE_DEVICE_TABLE(of, mt9v032_of_match);
1294#endif
1295
Detlev Casanova0f2ce162011-04-05 09:06:21 -03001296static struct i2c_driver mt9v032_driver = {
1297 .driver = {
1298 .name = "mt9v032",
Laurent Pinchartf2272e12014-01-01 14:40:35 -03001299 .of_match_table = of_match_ptr(mt9v032_of_match),
Detlev Casanova0f2ce162011-04-05 09:06:21 -03001300 },
1301 .probe = mt9v032_probe,
1302 .remove = mt9v032_remove,
1303 .id_table = mt9v032_id,
1304};
1305
Axel Linc6e8d862012-02-12 06:56:32 -03001306module_i2c_driver(mt9v032_driver);
Detlev Casanova0f2ce162011-04-05 09:06:21 -03001307
1308MODULE_DESCRIPTION("Aptina MT9V032 Camera driver");
1309MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
1310MODULE_LICENSE("GPL");