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Rob Herringabe92132019-01-10 16:19:42 -06001# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/serial/pl011.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM AMBA Primecell PL011 serial UART
8
9maintainers:
10 - Rob Herring <robh@kernel.org>
11
12allOf:
Krzysztof Kozlowskic7a9a842023-01-24 10:19:07 +010013 - $ref: /schemas/arm/primecell.yaml#
Zhen Lei8f082dc2021-05-06 21:20:48 +080014 - $ref: serial.yaml#
Rob Herringabe92132019-01-10 16:19:42 -060015
16# Need a custom select here or 'arm,primecell' will match on lots of nodes
17select:
18 properties:
19 compatible:
20 contains:
21 enum:
22 - arm,pl011
Rob Herringabe92132019-01-10 16:19:42 -060023 required:
24 - compatible
25
26properties:
27 compatible:
Zhen Leif2b0fe42021-05-20 19:54:39 +080028 items:
29 - const: arm,pl011
30 - const: arm,primecell
Rob Herringabe92132019-01-10 16:19:42 -060031
32 reg:
33 maxItems: 1
34
35 interrupts:
36 maxItems: 1
37
38 pinctrl-0: true
39 pinctrl-1: true
40
41 pinctrl-names:
42 description:
43 When present, must have one state named "default",
44 and may contain a second name named "sleep". The former
45 state sets up pins for ordinary operation whereas
46 the latter state will put the associated pins to sleep
47 when the UART is unused
48 minItems: 1
49 items:
50 - const: default
51 - const: sleep
52
53 clocks:
54 description:
55 When present, the first clock listed must correspond to
56 the clock named UARTCLK on the IP block, i.e. the clock
57 to the external serial line, whereas the second clock
58 must correspond to the PCLK clocking the internal logic
59 of the block. Just listing one clock (the first one) is
60 deprecated.
61 maxItems: 2
62
63 clock-names:
64 items:
65 - const: uartclk
66 - const: apb_pclk
67
68 dmas:
69 minItems: 1
70 maxItems: 2
71
72 dma-names:
73 minItems: 1
74 items:
75 - const: rx
76 - const: tx
77
78 auto-poll:
79 description:
80 Enables polling when using RX DMA.
81 type: boolean
82
83 poll-rate-ms:
84 description:
85 Rate at which poll occurs when auto-poll is set.
86 default 100ms.
Rob Herring3d21a462020-04-15 19:55:49 -050087 default: 100
Rob Herringabe92132019-01-10 16:19:42 -060088
89 poll-timeout-ms:
90 description:
91 Poll timeout when auto-poll is set, default
92 3000ms.
Rob Herring3d21a462020-04-15 19:55:49 -050093 default: 3000
Rob Herringabe92132019-01-10 16:19:42 -060094
Linus Walleij180d5972021-11-20 02:14:18 +010095 resets:
96 maxItems: 1
97
Shubhrajyoti Datta8ed030de2022-08-26 17:35:58 +053098 reg-io-width:
99 description:
100 The size (in bytes) of the IO accesses that should be performed
101 on the device.
102 enum: [1, 4]
103
Rob Herringabe92132019-01-10 16:19:42 -0600104required:
105 - compatible
106 - reg
107 - interrupts
108
109dependencies:
110 poll-rate-ms: [ auto-poll ]
111 poll-timeout-ms: [ auto-poll ]
112
Zhen Lei8f082dc2021-05-06 21:20:48 +0800113unevaluatedProperties: false
Rob Herringabe92132019-01-10 16:19:42 -0600114
115examples:
116 - |
117 serial@80120000 {
118 compatible = "arm,pl011", "arm,primecell";
119 reg = <0x80120000 0x1000>;
120 interrupts = <0 11 4>;
121 dmas = <&dma 13 0 0x2>, <&dma 13 0 0x0>;
122 dma-names = "rx", "tx";
123 clocks = <&foo_clk>, <&bar_clk>;
124 clock-names = "uartclk", "apb_pclk";
125 };
126
127...