blob: 48e3768a830e7d322a61824b811e7ad004af6485 [file] [log] [blame]
Thomas Gleixner873e65b2019-05-27 08:55:15 +02001// SPDX-License-Identifier: GPL-2.0-only
Tomoya MORINAGA49a36792011-01-12 17:00:22 -08002/*
3 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
Tomoya MORINAGA49a36792011-01-12 17:00:22 -08004 */
Paul Gortmakerbb207ef2011-07-03 13:38:09 -04005#include <linux/module.h>
Tomoya MORINAGA49a36792011-01-12 17:00:22 -08006#include <linux/kernel.h>
Andrew Morton545554e2011-05-24 17:13:43 -07007#include <linux/slab.h>
Tomoya MORINAGA49a36792011-01-12 17:00:22 -08008#include <linux/pci.h>
Linus Walleij85320ab2018-04-13 15:17:11 +02009#include <linux/gpio/driver.h>
Tomoya MORINAGA54be5662011-08-05 13:04:21 +090010#include <linux/interrupt.h>
11#include <linux/irq.h>
12
13#define IOH_EDGE_FALLING 0
14#define IOH_EDGE_RISING BIT(0)
15#define IOH_LEVEL_L BIT(1)
16#define IOH_LEVEL_H (BIT(0) | BIT(1))
17#define IOH_EDGE_BOTH BIT(2)
18#define IOH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
19
20#define IOH_IRQ_BASE 0
Tomoya MORINAGA49a36792011-01-12 17:00:22 -080021
Tomoya MORINAGA49a36792011-01-12 17:00:22 -080022struct ioh_reg_comn {
23 u32 ien;
24 u32 istatus;
25 u32 idisp;
26 u32 iclr;
27 u32 imask;
28 u32 imaskclr;
29 u32 po;
30 u32 pi;
31 u32 pm;
32 u32 im_0;
33 u32 im_1;
34 u32 reserved;
35};
36
37struct ioh_regs {
38 struct ioh_reg_comn regs[8];
39 u32 reserve1[16];
40 u32 ioh_sel_reg[4];
41 u32 reserve2[11];
42 u32 srst;
43};
44
45/**
46 * struct ioh_gpio_reg_data - The register store data.
Lee Jones85b565c2020-06-30 14:33:38 +010047 * @ien_reg: To store contents of interrupt enable register.
Tomoya MORINAGA54be5662011-08-05 13:04:21 +090048 * @imask_reg: To store contents of interrupt mask regist
Tomoya MORINAGA49a36792011-01-12 17:00:22 -080049 * @po_reg: To store contents of PO register.
50 * @pm_reg: To store contents of PM register.
Tomoya MORINAGA54be5662011-08-05 13:04:21 +090051 * @im0_reg: To store contents of interrupt mode regist0
52 * @im1_reg: To store contents of interrupt mode regist1
Tomoya MORINAGAb490fa02011-08-05 13:04:22 +090053 * @use_sel_reg: To store contents of GPIO_USE_SEL0~3
Tomoya MORINAGA49a36792011-01-12 17:00:22 -080054 */
55struct ioh_gpio_reg_data {
Tomoya MORINAGA54be5662011-08-05 13:04:21 +090056 u32 ien_reg;
57 u32 imask_reg;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -080058 u32 po_reg;
59 u32 pm_reg;
Tomoya MORINAGA54be5662011-08-05 13:04:21 +090060 u32 im0_reg;
61 u32 im1_reg;
Tomoya MORINAGAb490fa02011-08-05 13:04:22 +090062 u32 use_sel_reg;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -080063};
64
65/**
66 * struct ioh_gpio - GPIO private data structure.
67 * @base: PCI base address of Memory mapped I/O register.
68 * @reg: Memory mapped IOH GPIO register list.
69 * @dev: Pointer to device structure.
70 * @gpio: Data for GPIO infrastructure.
71 * @ioh_gpio_reg: Memory mapped Register data is saved here
72 * when suspend.
Tomoya MORINAGAb490fa02011-08-05 13:04:22 +090073 * @gpio_use_sel: Save GPIO_USE_SEL1~4 register for PM
Tomoya MORINAGA49a36792011-01-12 17:00:22 -080074 * @ch: Indicate GPIO channel
Tomoya MORINAGA54be5662011-08-05 13:04:21 +090075 * @irq_base: Save base of IRQ number for interrupt
Axel Lin02a67942012-07-29 10:54:42 +080076 * @spinlock: Used for register access protection
Tomoya MORINAGA49a36792011-01-12 17:00:22 -080077 */
78struct ioh_gpio {
79 void __iomem *base;
80 struct ioh_regs __iomem *reg;
81 struct device *dev;
82 struct gpio_chip gpio;
83 struct ioh_gpio_reg_data ioh_gpio_reg;
Tomoya MORINAGAb490fa02011-08-05 13:04:22 +090084 u32 gpio_use_sel;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -080085 int ch;
Tomoya MORINAGA54be5662011-08-05 13:04:21 +090086 int irq_base;
87 spinlock_t spinlock;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -080088};
89
90static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
91
92static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
93{
94 u32 reg_val;
Linus Walleij47315572015-12-07 10:12:05 +010095 struct ioh_gpio *chip = gpiochip_get_data(gpio);
Axel Lin02a67942012-07-29 10:54:42 +080096 unsigned long flags;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -080097
Axel Lin02a67942012-07-29 10:54:42 +080098 spin_lock_irqsave(&chip->spinlock, flags);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -080099 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
100 if (val)
Bjorn Helgaas46155a02021-11-30 16:08:40 -0600101 reg_val |= BIT(nr);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800102 else
Bjorn Helgaas46155a02021-11-30 16:08:40 -0600103 reg_val &= ~BIT(nr);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800104
105 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
Axel Lin02a67942012-07-29 10:54:42 +0800106 spin_unlock_irqrestore(&chip->spinlock, flags);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800107}
108
109static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
110{
Linus Walleij47315572015-12-07 10:12:05 +0100111 struct ioh_gpio *chip = gpiochip_get_data(gpio);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800112
Bjorn Helgaas46155a02021-11-30 16:08:40 -0600113 return !!(ioread32(&chip->reg->regs[chip->ch].pi) & BIT(nr));
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800114}
115
116static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
117 int val)
118{
Linus Walleij47315572015-12-07 10:12:05 +0100119 struct ioh_gpio *chip = gpiochip_get_data(gpio);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800120 u32 pm;
121 u32 reg_val;
Axel Lin02a67942012-07-29 10:54:42 +0800122 unsigned long flags;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800123
Axel Lin02a67942012-07-29 10:54:42 +0800124 spin_lock_irqsave(&chip->spinlock, flags);
Bjorn Helgaas7bc14ff22021-11-30 16:08:41 -0600125 pm = ioread32(&chip->reg->regs[chip->ch].pm);
126 pm &= BIT(num_ports[chip->ch]) - 1;
Bjorn Helgaas46155a02021-11-30 16:08:40 -0600127 pm |= BIT(nr);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800128 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
129
130 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
131 if (val)
Bjorn Helgaas46155a02021-11-30 16:08:40 -0600132 reg_val |= BIT(nr);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800133 else
Bjorn Helgaas46155a02021-11-30 16:08:40 -0600134 reg_val &= ~BIT(nr);
Peter Tyserba438612011-03-24 18:17:14 -0500135 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800136
Axel Lin02a67942012-07-29 10:54:42 +0800137 spin_unlock_irqrestore(&chip->spinlock, flags);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800138
139 return 0;
140}
141
142static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
143{
Linus Walleij47315572015-12-07 10:12:05 +0100144 struct ioh_gpio *chip = gpiochip_get_data(gpio);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800145 u32 pm;
Axel Lin02a67942012-07-29 10:54:42 +0800146 unsigned long flags;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800147
Axel Lin02a67942012-07-29 10:54:42 +0800148 spin_lock_irqsave(&chip->spinlock, flags);
Bjorn Helgaas7bc14ff22021-11-30 16:08:41 -0600149 pm = ioread32(&chip->reg->regs[chip->ch].pm);
150 pm &= BIT(num_ports[chip->ch]) - 1;
Bjorn Helgaas46155a02021-11-30 16:08:40 -0600151 pm &= ~BIT(nr);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800152 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
Axel Lin02a67942012-07-29 10:54:42 +0800153 spin_unlock_irqrestore(&chip->spinlock, flags);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800154
155 return 0;
156}
157
158/*
159 * Save register configuration and disable interrupts.
160 */
Vaibhav Gupta40bb0e32020-04-02 21:20:58 +0530161static void __maybe_unused ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800162{
Tomoya MORINAGAb490fa02011-08-05 13:04:22 +0900163 int i;
164
165 for (i = 0; i < 8; i ++, chip++) {
166 chip->ioh_gpio_reg.po_reg =
167 ioread32(&chip->reg->regs[chip->ch].po);
168 chip->ioh_gpio_reg.pm_reg =
169 ioread32(&chip->reg->regs[chip->ch].pm);
170 chip->ioh_gpio_reg.ien_reg =
171 ioread32(&chip->reg->regs[chip->ch].ien);
172 chip->ioh_gpio_reg.imask_reg =
173 ioread32(&chip->reg->regs[chip->ch].imask);
174 chip->ioh_gpio_reg.im0_reg =
175 ioread32(&chip->reg->regs[chip->ch].im_0);
176 chip->ioh_gpio_reg.im1_reg =
177 ioread32(&chip->reg->regs[chip->ch].im_1);
178 if (i < 4)
179 chip->ioh_gpio_reg.use_sel_reg =
180 ioread32(&chip->reg->ioh_sel_reg[i]);
181 }
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800182}
183
184/*
185 * This function restores the register configuration of the GPIO device.
186 */
Vaibhav Gupta40bb0e32020-04-02 21:20:58 +0530187static void __maybe_unused ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800188{
Tomoya MORINAGAb490fa02011-08-05 13:04:22 +0900189 int i;
190
191 for (i = 0; i < 8; i ++, chip++) {
192 iowrite32(chip->ioh_gpio_reg.po_reg,
193 &chip->reg->regs[chip->ch].po);
194 iowrite32(chip->ioh_gpio_reg.pm_reg,
195 &chip->reg->regs[chip->ch].pm);
196 iowrite32(chip->ioh_gpio_reg.ien_reg,
197 &chip->reg->regs[chip->ch].ien);
198 iowrite32(chip->ioh_gpio_reg.imask_reg,
199 &chip->reg->regs[chip->ch].imask);
200 iowrite32(chip->ioh_gpio_reg.im0_reg,
201 &chip->reg->regs[chip->ch].im_0);
202 iowrite32(chip->ioh_gpio_reg.im1_reg,
203 &chip->reg->regs[chip->ch].im_1);
204 if (i < 4)
205 iowrite32(chip->ioh_gpio_reg.use_sel_reg,
206 &chip->reg->ioh_sel_reg[i]);
207 }
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800208}
209
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900210static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
211{
Linus Walleij47315572015-12-07 10:12:05 +0100212 struct ioh_gpio *chip = gpiochip_get_data(gpio);
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900213 return chip->irq_base + offset;
214}
215
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800216static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
217{
218 struct gpio_chip *gpio = &chip->gpio;
219
220 gpio->label = dev_name(chip->dev);
221 gpio->owner = THIS_MODULE;
222 gpio->direction_input = ioh_gpio_direction_input;
223 gpio->get = ioh_gpio_get;
224 gpio->direction_output = ioh_gpio_direction_output;
225 gpio->set = ioh_gpio_set;
226 gpio->dbg_show = NULL;
227 gpio->base = -1;
228 gpio->ngpio = num_port;
Linus Walleij9fb1f392013-12-04 14:42:46 +0100229 gpio->can_sleep = false;
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900230 gpio->to_irq = ioh_gpio_to_irq;
231}
232
233static int ioh_irq_type(struct irq_data *d, unsigned int type)
234{
235 u32 im;
Márton Némethdd9328a2012-01-15 10:57:34 +0100236 void __iomem *im_reg;
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900237 u32 ien;
238 u32 im_pos;
239 int ch;
240 unsigned long flags;
241 u32 val;
242 int irq = d->irq;
243 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
244 struct ioh_gpio *chip = gc->private;
245
246 ch = irq - chip->irq_base;
247 if (irq <= chip->irq_base + 7) {
248 im_reg = &chip->reg->regs[chip->ch].im_0;
249 im_pos = ch;
250 } else {
251 im_reg = &chip->reg->regs[chip->ch].im_1;
252 im_pos = ch - 8;
253 }
254 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
255 __func__, irq, type, ch, im_pos, type);
256
257 spin_lock_irqsave(&chip->spinlock, flags);
258
259 switch (type) {
260 case IRQ_TYPE_EDGE_RISING:
261 val = IOH_EDGE_RISING;
262 break;
263 case IRQ_TYPE_EDGE_FALLING:
264 val = IOH_EDGE_FALLING;
265 break;
266 case IRQ_TYPE_EDGE_BOTH:
267 val = IOH_EDGE_BOTH;
268 break;
269 case IRQ_TYPE_LEVEL_HIGH:
270 val = IOH_LEVEL_H;
271 break;
272 case IRQ_TYPE_LEVEL_LOW:
273 val = IOH_LEVEL_L;
274 break;
275 case IRQ_TYPE_PROBE:
276 goto end;
277 default:
278 dev_warn(chip->dev, "%s: unknown type(%dd)",
279 __func__, type);
280 goto end;
281 }
282
283 /* Set interrupt mode */
284 im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
285 iowrite32(im | (val << (im_pos * 4)), im_reg);
286
287 /* iclr */
288 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
289
290 /* IMASKCLR */
291 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
292
293 /* Enable interrupt */
294 ien = ioread32(&chip->reg->regs[chip->ch].ien);
295 iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
296end:
297 spin_unlock_irqrestore(&chip->spinlock, flags);
298
299 return 0;
300}
301
302static void ioh_irq_unmask(struct irq_data *d)
303{
304 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
305 struct ioh_gpio *chip = gc->private;
306
Bjorn Helgaas46155a02021-11-30 16:08:40 -0600307 iowrite32(BIT(d->irq - chip->irq_base),
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900308 &chip->reg->regs[chip->ch].imaskclr);
309}
310
311static void ioh_irq_mask(struct irq_data *d)
312{
313 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
314 struct ioh_gpio *chip = gc->private;
315
Bjorn Helgaas46155a02021-11-30 16:08:40 -0600316 iowrite32(BIT(d->irq - chip->irq_base),
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900317 &chip->reg->regs[chip->ch].imask);
318}
319
Feng Tang4d052212011-12-13 23:53:50 +0800320static void ioh_irq_disable(struct irq_data *d)
321{
322 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
323 struct ioh_gpio *chip = gc->private;
324 unsigned long flags;
325 u32 ien;
326
327 spin_lock_irqsave(&chip->spinlock, flags);
328 ien = ioread32(&chip->reg->regs[chip->ch].ien);
Bjorn Helgaas46155a02021-11-30 16:08:40 -0600329 ien &= ~BIT(d->irq - chip->irq_base);
Feng Tang4d052212011-12-13 23:53:50 +0800330 iowrite32(ien, &chip->reg->regs[chip->ch].ien);
331 spin_unlock_irqrestore(&chip->spinlock, flags);
332}
333
334static void ioh_irq_enable(struct irq_data *d)
335{
336 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
337 struct ioh_gpio *chip = gc->private;
338 unsigned long flags;
339 u32 ien;
340
341 spin_lock_irqsave(&chip->spinlock, flags);
342 ien = ioread32(&chip->reg->regs[chip->ch].ien);
Bjorn Helgaas46155a02021-11-30 16:08:40 -0600343 ien |= BIT(d->irq - chip->irq_base);
Feng Tang4d052212011-12-13 23:53:50 +0800344 iowrite32(ien, &chip->reg->regs[chip->ch].ien);
345 spin_unlock_irqrestore(&chip->spinlock, flags);
346}
347
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900348static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
349{
350 struct ioh_gpio *chip = dev_id;
351 u32 reg_val;
352 int i, j;
353 int ret = IRQ_NONE;
354
Feng Tangf9ea14e2011-12-13 23:53:49 +0800355 for (i = 0; i < 8; i++, chip++) {
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900356 reg_val = ioread32(&chip->reg->regs[i].istatus);
357 for (j = 0; j < num_ports[i]; j++) {
358 if (reg_val & BIT(j)) {
359 dev_dbg(chip->dev,
360 "%s:[%d]:irq=%d status=0x%x\n",
361 __func__, j, irq, reg_val);
362 iowrite32(BIT(j),
363 &chip->reg->regs[chip->ch].iclr);
364 generic_handle_irq(chip->irq_base + j);
365 ret = IRQ_HANDLED;
366 }
367 }
368 }
369 return ret;
370}
371
Bartosz Golaszewskie3fe07e2017-05-25 10:37:38 +0200372static int ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
373 unsigned int irq_start,
374 unsigned int num)
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900375{
376 struct irq_chip_generic *gc;
377 struct irq_chip_type *ct;
Bartosz Golaszewski469d5942017-08-09 14:25:04 +0200378 int rv;
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900379
Bartosz Golaszewski469d5942017-08-09 14:25:04 +0200380 gc = devm_irq_alloc_generic_chip(chip->dev, "ioh_gpio", 1, irq_start,
381 chip->base, handle_simple_irq);
Bartosz Golaszewskie3fe07e2017-05-25 10:37:38 +0200382 if (!gc)
383 return -ENOMEM;
384
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900385 gc->private = chip;
386 ct = gc->chip_types;
387
388 ct->chip.irq_mask = ioh_irq_mask;
389 ct->chip.irq_unmask = ioh_irq_unmask;
390 ct->chip.irq_set_type = ioh_irq_type;
Feng Tang4d052212011-12-13 23:53:50 +0800391 ct->chip.irq_disable = ioh_irq_disable;
392 ct->chip.irq_enable = ioh_irq_enable;
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900393
Bartosz Golaszewski469d5942017-08-09 14:25:04 +0200394 rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
395 IRQ_GC_INIT_MASK_CACHE,
396 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
Bartosz Golaszewskie3fe07e2017-05-25 10:37:38 +0200397
Bartosz Golaszewski469d5942017-08-09 14:25:04 +0200398 return rv;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800399}
400
Bill Pemberton38363092012-11-19 13:22:34 -0500401static int ioh_gpio_probe(struct pci_dev *pdev,
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800402 const struct pci_device_id *id)
403{
Bjorn Helgaas06939f22021-11-30 16:08:39 -0600404 struct device *dev = &pdev->dev;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800405 int ret;
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900406 int i, j;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800407 struct ioh_gpio *chip;
408 void __iomem *base;
Márton Némethdd9328a2012-01-15 10:57:34 +0100409 void *chip_save;
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900410 int irq_base;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800411
Zheyu Ma7869b482022-05-20 10:56:24 +0800412 ret = pcim_enable_device(pdev);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800413 if (ret) {
Zheyu Ma7869b482022-05-20 10:56:24 +0800414 dev_err(dev, "%s : pcim_enable_device failed", __func__);
415 return ret;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800416 }
417
Zheyu Ma7869b482022-05-20 10:56:24 +0800418 ret = pcim_iomap_regions(pdev, BIT(1), KBUILD_MODNAME);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800419 if (ret) {
Zheyu Ma7869b482022-05-20 10:56:24 +0800420 dev_err(dev, "pcim_iomap_regions failed-%d", ret);
421 return ret;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800422 }
423
Zheyu Ma7869b482022-05-20 10:56:24 +0800424 base = pcim_iomap_table(pdev)[1];
Márton Németh2bd1c852012-01-15 10:57:43 +0100425 if (!base) {
Zheyu Ma7869b482022-05-20 10:56:24 +0800426 dev_err(dev, "%s : pcim_iomap_table failed", __func__);
427 return -ENOMEM;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800428 }
429
Zheyu Ma7869b482022-05-20 10:56:24 +0800430 chip_save = devm_kcalloc(dev, 8, sizeof(*chip), GFP_KERNEL);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800431 if (chip_save == NULL) {
Zheyu Ma7869b482022-05-20 10:56:24 +0800432 return -ENOMEM;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800433 }
434
435 chip = chip_save;
436 for (i = 0; i < 8; i++, chip++) {
Bjorn Helgaas06939f22021-11-30 16:08:39 -0600437 chip->dev = dev;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800438 chip->base = base;
439 chip->reg = chip->base;
440 chip->ch = i;
Axel Lin7e3a70f2012-02-01 10:50:05 +0800441 spin_lock_init(&chip->spinlock);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800442 ioh_gpio_setup(chip, num_ports[i]);
Zheyu Ma7869b482022-05-20 10:56:24 +0800443 ret = devm_gpiochip_add_data(dev, &chip->gpio, chip);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800444 if (ret) {
Bjorn Helgaas06939f22021-11-30 16:08:39 -0600445 dev_err(dev, "IOH gpio: Failed to register GPIO\n");
Zheyu Ma7869b482022-05-20 10:56:24 +0800446 return ret;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800447 }
448 }
449
450 chip = chip_save;
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900451 for (j = 0; j < 8; j++, chip++) {
Bjorn Helgaas06939f22021-11-30 16:08:39 -0600452 irq_base = devm_irq_alloc_descs(dev, -1, IOH_IRQ_BASE,
Bartosz Golaszewskie971ac9a2017-03-04 17:23:33 +0100453 num_ports[j], NUMA_NO_NODE);
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900454 if (irq_base < 0) {
Bjorn Helgaas06939f22021-11-30 16:08:39 -0600455 dev_warn(dev,
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900456 "ml_ioh_gpio: Failed to get IRQ base num\n");
Zheyu Ma7869b482022-05-20 10:56:24 +0800457 return irq_base;
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900458 }
459 chip->irq_base = irq_base;
Bartosz Golaszewskie3fe07e2017-05-25 10:37:38 +0200460
461 ret = ioh_gpio_alloc_generic_chip(chip,
462 irq_base, num_ports[j]);
463 if (ret)
Zheyu Ma7869b482022-05-20 10:56:24 +0800464 return ret;
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900465 }
466
467 chip = chip_save;
Bjorn Helgaas06939f22021-11-30 16:08:39 -0600468 ret = devm_request_irq(dev, pdev->irq, ioh_gpio_handler,
Bartosz Golaszewskie971ac9a2017-03-04 17:23:33 +0100469 IRQF_SHARED, KBUILD_MODNAME, chip);
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900470 if (ret != 0) {
Bjorn Helgaas06939f22021-11-30 16:08:39 -0600471 dev_err(dev, "%s request_irq failed\n", __func__);
Zheyu Ma7869b482022-05-20 10:56:24 +0800472 return ret;
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900473 }
474
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800475 pci_set_drvdata(pdev, chip);
476
477 return 0;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800478}
479
Vaibhav Gupta40bb0e32020-04-02 21:20:58 +0530480static int __maybe_unused ioh_gpio_suspend(struct device *dev)
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800481{
Vaibhav Gupta40bb0e32020-04-02 21:20:58 +0530482 struct ioh_gpio *chip = dev_get_drvdata(dev);
Tomoya MORINAGAb490fa02011-08-05 13:04:22 +0900483 unsigned long flags;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800484
Tomoya MORINAGAb490fa02011-08-05 13:04:22 +0900485 spin_lock_irqsave(&chip->spinlock, flags);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800486 ioh_gpio_save_reg_conf(chip);
Tomoya MORINAGAb490fa02011-08-05 13:04:22 +0900487 spin_unlock_irqrestore(&chip->spinlock, flags);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800488
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800489 return 0;
490}
491
Vaibhav Gupta40bb0e32020-04-02 21:20:58 +0530492static int __maybe_unused ioh_gpio_resume(struct device *dev)
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800493{
Vaibhav Gupta40bb0e32020-04-02 21:20:58 +0530494 struct ioh_gpio *chip = dev_get_drvdata(dev);
Tomoya MORINAGAb490fa02011-08-05 13:04:22 +0900495 unsigned long flags;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800496
Tomoya MORINAGAb490fa02011-08-05 13:04:22 +0900497 spin_lock_irqsave(&chip->spinlock, flags);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800498 iowrite32(0x01, &chip->reg->srst);
499 iowrite32(0x00, &chip->reg->srst);
500 ioh_gpio_restore_reg_conf(chip);
Tomoya MORINAGAb490fa02011-08-05 13:04:22 +0900501 spin_unlock_irqrestore(&chip->spinlock, flags);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800502
503 return 0;
504}
Vaibhav Gupta40bb0e32020-04-02 21:20:58 +0530505
506static SIMPLE_DEV_PM_OPS(ioh_gpio_pm_ops, ioh_gpio_suspend, ioh_gpio_resume);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800507
Jingoo Han14f4a882013-12-03 08:08:45 +0900508static const struct pci_device_id ioh_gpio_pcidev_id[] = {
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800509 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
510 { 0, }
511};
Axel Lin19234cd2011-03-11 14:58:30 -0800512MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800513
514static struct pci_driver ioh_gpio_driver = {
515 .name = "ml_ioh_gpio",
516 .id_table = ioh_gpio_pcidev_id,
517 .probe = ioh_gpio_probe,
Vaibhav Gupta40bb0e32020-04-02 21:20:58 +0530518 .driver = {
519 .pm = &ioh_gpio_pm_ops,
520 },
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800521};
522
Axel Lin93baa652012-04-06 20:13:30 +0800523module_pci_driver(ioh_gpio_driver);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800524
525MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
526MODULE_LICENSE("GPL");