Thomas Gleixner | 2874c5f | 2019-05-27 08:55:01 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2012 - 2014 Allwinner Tech |
| 4 | * Pan Nan <pannan@allwinnertech.com> |
| 5 | * |
| 6 | * Copyright (C) 2014 Maxime Ripard |
| 7 | * Maxime Ripard <maxime.ripard@free-electrons.com> |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #include <linux/clk.h> |
| 11 | #include <linux/delay.h> |
| 12 | #include <linux/device.h> |
| 13 | #include <linux/interrupt.h> |
| 14 | #include <linux/io.h> |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/pm_runtime.h> |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 18 | |
| 19 | #include <linux/spi/spi.h> |
| 20 | |
| 21 | #define SUN4I_FIFO_DEPTH 64 |
| 22 | |
| 23 | #define SUN4I_RXDATA_REG 0x00 |
| 24 | |
| 25 | #define SUN4I_TXDATA_REG 0x04 |
| 26 | |
| 27 | #define SUN4I_CTL_REG 0x08 |
| 28 | #define SUN4I_CTL_ENABLE BIT(0) |
| 29 | #define SUN4I_CTL_MASTER BIT(1) |
| 30 | #define SUN4I_CTL_CPHA BIT(2) |
| 31 | #define SUN4I_CTL_CPOL BIT(3) |
| 32 | #define SUN4I_CTL_CS_ACTIVE_LOW BIT(4) |
| 33 | #define SUN4I_CTL_LMTF BIT(6) |
| 34 | #define SUN4I_CTL_TF_RST BIT(8) |
| 35 | #define SUN4I_CTL_RF_RST BIT(9) |
| 36 | #define SUN4I_CTL_XCH BIT(10) |
| 37 | #define SUN4I_CTL_CS_MASK 0x3000 |
| 38 | #define SUN4I_CTL_CS(cs) (((cs) << 12) & SUN4I_CTL_CS_MASK) |
| 39 | #define SUN4I_CTL_DHB BIT(15) |
| 40 | #define SUN4I_CTL_CS_MANUAL BIT(16) |
| 41 | #define SUN4I_CTL_CS_LEVEL BIT(17) |
| 42 | #define SUN4I_CTL_TP BIT(18) |
| 43 | |
| 44 | #define SUN4I_INT_CTL_REG 0x0c |
Alexandru Gagniuc | 1967379 | 2016-10-26 00:00:31 -0700 | [diff] [blame] | 45 | #define SUN4I_INT_CTL_RF_F34 BIT(4) |
| 46 | #define SUN4I_INT_CTL_TF_E34 BIT(12) |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 47 | #define SUN4I_INT_CTL_TC BIT(16) |
| 48 | |
| 49 | #define SUN4I_INT_STA_REG 0x10 |
| 50 | |
| 51 | #define SUN4I_DMA_CTL_REG 0x14 |
| 52 | |
| 53 | #define SUN4I_WAIT_REG 0x18 |
| 54 | |
| 55 | #define SUN4I_CLK_CTL_REG 0x1c |
| 56 | #define SUN4I_CLK_CTL_CDR2_MASK 0xff |
| 57 | #define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK) |
| 58 | #define SUN4I_CLK_CTL_CDR1_MASK 0xf |
| 59 | #define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8) |
| 60 | #define SUN4I_CLK_CTL_DRS BIT(12) |
| 61 | |
Alexandru Gagniuc | 1967379 | 2016-10-26 00:00:31 -0700 | [diff] [blame] | 62 | #define SUN4I_MAX_XFER_SIZE 0xffffff |
| 63 | |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 64 | #define SUN4I_BURST_CNT_REG 0x20 |
Alexandru Gagniuc | 1967379 | 2016-10-26 00:00:31 -0700 | [diff] [blame] | 65 | #define SUN4I_BURST_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE) |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 66 | |
| 67 | #define SUN4I_XMIT_CNT_REG 0x24 |
Alexandru Gagniuc | 1967379 | 2016-10-26 00:00:31 -0700 | [diff] [blame] | 68 | #define SUN4I_XMIT_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE) |
| 69 | |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 70 | |
| 71 | #define SUN4I_FIFO_STA_REG 0x28 |
| 72 | #define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f |
| 73 | #define SUN4I_FIFO_STA_RF_CNT_BITS 0 |
| 74 | #define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f |
| 75 | #define SUN4I_FIFO_STA_TF_CNT_BITS 16 |
| 76 | |
| 77 | struct sun4i_spi { |
| 78 | struct spi_master *master; |
| 79 | void __iomem *base_addr; |
| 80 | struct clk *hclk; |
| 81 | struct clk *mclk; |
| 82 | |
| 83 | struct completion done; |
| 84 | |
| 85 | const u8 *tx_buf; |
| 86 | u8 *rx_buf; |
| 87 | int len; |
| 88 | }; |
| 89 | |
| 90 | static inline u32 sun4i_spi_read(struct sun4i_spi *sspi, u32 reg) |
| 91 | { |
| 92 | return readl(sspi->base_addr + reg); |
| 93 | } |
| 94 | |
| 95 | static inline void sun4i_spi_write(struct sun4i_spi *sspi, u32 reg, u32 value) |
| 96 | { |
| 97 | writel(value, sspi->base_addr + reg); |
| 98 | } |
| 99 | |
Alexandru Gagniuc | 1967379 | 2016-10-26 00:00:31 -0700 | [diff] [blame] | 100 | static inline u32 sun4i_spi_get_tx_fifo_count(struct sun4i_spi *sspi) |
| 101 | { |
| 102 | u32 reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG); |
| 103 | |
| 104 | reg >>= SUN4I_FIFO_STA_TF_CNT_BITS; |
| 105 | |
| 106 | return reg & SUN4I_FIFO_STA_TF_CNT_MASK; |
| 107 | } |
| 108 | |
| 109 | static inline void sun4i_spi_enable_interrupt(struct sun4i_spi *sspi, u32 mask) |
| 110 | { |
| 111 | u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG); |
| 112 | |
| 113 | reg |= mask; |
| 114 | sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg); |
| 115 | } |
| 116 | |
| 117 | static inline void sun4i_spi_disable_interrupt(struct sun4i_spi *sspi, u32 mask) |
| 118 | { |
| 119 | u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG); |
| 120 | |
| 121 | reg &= ~mask; |
| 122 | sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg); |
| 123 | } |
| 124 | |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 125 | static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len) |
| 126 | { |
| 127 | u32 reg, cnt; |
| 128 | u8 byte; |
| 129 | |
| 130 | /* See how much data is available */ |
| 131 | reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG); |
| 132 | reg &= SUN4I_FIFO_STA_RF_CNT_MASK; |
| 133 | cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS; |
| 134 | |
| 135 | if (len > cnt) |
| 136 | len = cnt; |
| 137 | |
| 138 | while (len--) { |
| 139 | byte = readb(sspi->base_addr + SUN4I_RXDATA_REG); |
| 140 | if (sspi->rx_buf) |
| 141 | *sspi->rx_buf++ = byte; |
| 142 | } |
| 143 | } |
| 144 | |
| 145 | static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len) |
| 146 | { |
Alexandru Gagniuc | 1967379 | 2016-10-26 00:00:31 -0700 | [diff] [blame] | 147 | u32 cnt; |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 148 | u8 byte; |
| 149 | |
Alexandru Gagniuc | 1967379 | 2016-10-26 00:00:31 -0700 | [diff] [blame] | 150 | /* See how much data we can fit */ |
| 151 | cnt = SUN4I_FIFO_DEPTH - sun4i_spi_get_tx_fifo_count(sspi); |
| 152 | |
| 153 | len = min3(len, (int)cnt, sspi->len); |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 154 | |
| 155 | while (len--) { |
| 156 | byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; |
| 157 | writeb(byte, sspi->base_addr + SUN4I_TXDATA_REG); |
| 158 | sspi->len--; |
| 159 | } |
| 160 | } |
| 161 | |
| 162 | static void sun4i_spi_set_cs(struct spi_device *spi, bool enable) |
| 163 | { |
| 164 | struct sun4i_spi *sspi = spi_master_get_devdata(spi->master); |
| 165 | u32 reg; |
| 166 | |
| 167 | reg = sun4i_spi_read(sspi, SUN4I_CTL_REG); |
| 168 | |
| 169 | reg &= ~SUN4I_CTL_CS_MASK; |
| 170 | reg |= SUN4I_CTL_CS(spi->chip_select); |
| 171 | |
Marcus Weseloh | 218e0b5 | 2016-01-05 21:46:20 +0100 | [diff] [blame] | 172 | /* We want to control the chip select manually */ |
| 173 | reg |= SUN4I_CTL_CS_MANUAL; |
| 174 | |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 175 | if (enable) |
| 176 | reg |= SUN4I_CTL_CS_LEVEL; |
| 177 | else |
| 178 | reg &= ~SUN4I_CTL_CS_LEVEL; |
| 179 | |
| 180 | /* |
| 181 | * Even though this looks irrelevant since we are supposed to |
| 182 | * be controlling the chip select manually, this bit also |
| 183 | * controls the levels of the chip select for inactive |
| 184 | * devices. |
| 185 | * |
| 186 | * If we don't set it, the chip select level will go low by |
| 187 | * default when the device is idle, which is not really |
| 188 | * expected in the common case where the chip select is active |
| 189 | * low. |
| 190 | */ |
| 191 | if (spi->mode & SPI_CS_HIGH) |
| 192 | reg &= ~SUN4I_CTL_CS_ACTIVE_LOW; |
| 193 | else |
| 194 | reg |= SUN4I_CTL_CS_ACTIVE_LOW; |
| 195 | |
| 196 | sun4i_spi_write(sspi, SUN4I_CTL_REG, reg); |
| 197 | } |
| 198 | |
Michal Suchanek | 794912c | 2016-06-13 17:46:50 +0000 | [diff] [blame] | 199 | static size_t sun4i_spi_max_transfer_size(struct spi_device *spi) |
| 200 | { |
| 201 | return SUN4I_FIFO_DEPTH - 1; |
| 202 | } |
| 203 | |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 204 | static int sun4i_spi_transfer_one(struct spi_master *master, |
| 205 | struct spi_device *spi, |
| 206 | struct spi_transfer *tfr) |
| 207 | { |
| 208 | struct sun4i_spi *sspi = spi_master_get_devdata(master); |
| 209 | unsigned int mclk_rate, div, timeout; |
Michal Suchanek | 719bd65 | 2016-06-13 17:46:49 +0000 | [diff] [blame] | 210 | unsigned int start, end, tx_time; |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 211 | unsigned int tx_len = 0; |
| 212 | int ret = 0; |
| 213 | u32 reg; |
| 214 | |
| 215 | /* We don't support transfer larger than the FIFO */ |
Alexandru Gagniuc | 1967379 | 2016-10-26 00:00:31 -0700 | [diff] [blame] | 216 | if (tfr->len > SUN4I_MAX_XFER_SIZE) |
Michal Suchanek | 6d9fe44 | 2016-06-13 17:46:49 +0000 | [diff] [blame] | 217 | return -EMSGSIZE; |
| 218 | |
Alexandru Gagniuc | 1967379 | 2016-10-26 00:00:31 -0700 | [diff] [blame] | 219 | if (tfr->tx_buf && tfr->len >= SUN4I_MAX_XFER_SIZE) |
Michal Suchanek | 6d9fe44 | 2016-06-13 17:46:49 +0000 | [diff] [blame] | 220 | return -EMSGSIZE; |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 221 | |
| 222 | reinit_completion(&sspi->done); |
| 223 | sspi->tx_buf = tfr->tx_buf; |
| 224 | sspi->rx_buf = tfr->rx_buf; |
| 225 | sspi->len = tfr->len; |
| 226 | |
| 227 | /* Clear pending interrupts */ |
| 228 | sun4i_spi_write(sspi, SUN4I_INT_STA_REG, ~0); |
| 229 | |
| 230 | |
| 231 | reg = sun4i_spi_read(sspi, SUN4I_CTL_REG); |
| 232 | |
| 233 | /* Reset FIFOs */ |
| 234 | sun4i_spi_write(sspi, SUN4I_CTL_REG, |
| 235 | reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST); |
| 236 | |
| 237 | /* |
| 238 | * Setup the transfer control register: Chip Select, |
| 239 | * polarities, etc. |
| 240 | */ |
| 241 | if (spi->mode & SPI_CPOL) |
| 242 | reg |= SUN4I_CTL_CPOL; |
| 243 | else |
| 244 | reg &= ~SUN4I_CTL_CPOL; |
| 245 | |
| 246 | if (spi->mode & SPI_CPHA) |
| 247 | reg |= SUN4I_CTL_CPHA; |
| 248 | else |
| 249 | reg &= ~SUN4I_CTL_CPHA; |
| 250 | |
| 251 | if (spi->mode & SPI_LSB_FIRST) |
| 252 | reg |= SUN4I_CTL_LMTF; |
| 253 | else |
| 254 | reg &= ~SUN4I_CTL_LMTF; |
| 255 | |
| 256 | |
| 257 | /* |
| 258 | * If it's a TX only transfer, we don't want to fill the RX |
| 259 | * FIFO with bogus data |
| 260 | */ |
| 261 | if (sspi->rx_buf) |
| 262 | reg &= ~SUN4I_CTL_DHB; |
| 263 | else |
| 264 | reg |= SUN4I_CTL_DHB; |
| 265 | |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 266 | sun4i_spi_write(sspi, SUN4I_CTL_REG, reg); |
| 267 | |
| 268 | /* Ensure that we have a parent clock fast enough */ |
| 269 | mclk_rate = clk_get_rate(sspi->mclk); |
Marcus Weseloh | 47284e3 | 2015-11-08 12:03:23 +0100 | [diff] [blame] | 270 | if (mclk_rate < (2 * tfr->speed_hz)) { |
| 271 | clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 272 | mclk_rate = clk_get_rate(sspi->mclk); |
| 273 | } |
| 274 | |
| 275 | /* |
| 276 | * Setup clock divider. |
| 277 | * |
| 278 | * We have two choices there. Either we can use the clock |
| 279 | * divide rate 1, which is calculated thanks to this formula: |
| 280 | * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1)) |
| 281 | * Or we can use CDR2, which is calculated with the formula: |
| 282 | * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) |
| 283 | * Wether we use the former or the latter is set through the |
| 284 | * DRS bit. |
| 285 | * |
| 286 | * First try CDR2, and if we can't reach the expected |
| 287 | * frequency, fall back to CDR1. |
| 288 | */ |
Marcus Weseloh | 47284e3 | 2015-11-08 12:03:23 +0100 | [diff] [blame] | 289 | div = mclk_rate / (2 * tfr->speed_hz); |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 290 | if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) { |
| 291 | if (div > 0) |
| 292 | div--; |
| 293 | |
| 294 | reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS; |
| 295 | } else { |
Marcus Weseloh | 47284e3 | 2015-11-08 12:03:23 +0100 | [diff] [blame] | 296 | div = ilog2(mclk_rate) - ilog2(tfr->speed_hz); |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 297 | reg = SUN4I_CLK_CTL_CDR1(div); |
| 298 | } |
| 299 | |
| 300 | sun4i_spi_write(sspi, SUN4I_CLK_CTL_REG, reg); |
| 301 | |
| 302 | /* Setup the transfer now... */ |
| 303 | if (sspi->tx_buf) |
| 304 | tx_len = tfr->len; |
| 305 | |
| 306 | /* Setup the counters */ |
| 307 | sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len)); |
| 308 | sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len)); |
| 309 | |
Michal Suchanek | 6d9fe44 | 2016-06-13 17:46:49 +0000 | [diff] [blame] | 310 | /* |
| 311 | * Fill the TX FIFO |
| 312 | * Filling the FIFO fully causes timeout for some reason |
| 313 | * at least on spi2 on A10s |
| 314 | */ |
| 315 | sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1); |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 316 | |
| 317 | /* Enable the interrupts */ |
Alexandru Gagniuc | 1967379 | 2016-10-26 00:00:31 -0700 | [diff] [blame] | 318 | sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TC | |
| 319 | SUN4I_INT_CTL_RF_F34); |
| 320 | /* Only enable Tx FIFO interrupt if we really need it */ |
| 321 | if (tx_len > SUN4I_FIFO_DEPTH) |
| 322 | sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TF_E34); |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 323 | |
| 324 | /* Start the transfer */ |
| 325 | reg = sun4i_spi_read(sspi, SUN4I_CTL_REG); |
| 326 | sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH); |
| 327 | |
Michal Suchanek | 719bd65 | 2016-06-13 17:46:49 +0000 | [diff] [blame] | 328 | tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U); |
| 329 | start = jiffies; |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 330 | timeout = wait_for_completion_timeout(&sspi->done, |
Michal Suchanek | 719bd65 | 2016-06-13 17:46:49 +0000 | [diff] [blame] | 331 | msecs_to_jiffies(tx_time)); |
| 332 | end = jiffies; |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 333 | if (!timeout) { |
Michal Suchanek | 719bd65 | 2016-06-13 17:46:49 +0000 | [diff] [blame] | 334 | dev_warn(&master->dev, |
| 335 | "%s: timeout transferring %u bytes@%iHz for %i(%i)ms", |
| 336 | dev_name(&spi->dev), tfr->len, tfr->speed_hz, |
| 337 | jiffies_to_msecs(end - start), tx_time); |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 338 | ret = -ETIMEDOUT; |
| 339 | goto out; |
| 340 | } |
| 341 | |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 342 | |
| 343 | out: |
| 344 | sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0); |
| 345 | |
| 346 | return ret; |
| 347 | } |
| 348 | |
| 349 | static irqreturn_t sun4i_spi_handler(int irq, void *dev_id) |
| 350 | { |
| 351 | struct sun4i_spi *sspi = dev_id; |
| 352 | u32 status = sun4i_spi_read(sspi, SUN4I_INT_STA_REG); |
| 353 | |
| 354 | /* Transfer complete */ |
| 355 | if (status & SUN4I_INT_CTL_TC) { |
| 356 | sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TC); |
Alexandru Gagniuc | 1967379 | 2016-10-26 00:00:31 -0700 | [diff] [blame] | 357 | sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH); |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 358 | complete(&sspi->done); |
| 359 | return IRQ_HANDLED; |
| 360 | } |
| 361 | |
Alexandru Gagniuc | 1967379 | 2016-10-26 00:00:31 -0700 | [diff] [blame] | 362 | /* Receive FIFO 3/4 full */ |
| 363 | if (status & SUN4I_INT_CTL_RF_F34) { |
| 364 | sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH); |
| 365 | /* Only clear the interrupt _after_ draining the FIFO */ |
| 366 | sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_RF_F34); |
| 367 | return IRQ_HANDLED; |
| 368 | } |
| 369 | |
| 370 | /* Transmit FIFO 3/4 empty */ |
| 371 | if (status & SUN4I_INT_CTL_TF_E34) { |
| 372 | sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH); |
| 373 | |
| 374 | if (!sspi->len) |
| 375 | /* nothing left to transmit */ |
| 376 | sun4i_spi_disable_interrupt(sspi, SUN4I_INT_CTL_TF_E34); |
| 377 | |
| 378 | /* Only clear the interrupt _after_ re-seeding the FIFO */ |
| 379 | sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TF_E34); |
| 380 | |
| 381 | return IRQ_HANDLED; |
| 382 | } |
| 383 | |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 384 | return IRQ_NONE; |
| 385 | } |
| 386 | |
| 387 | static int sun4i_spi_runtime_resume(struct device *dev) |
| 388 | { |
| 389 | struct spi_master *master = dev_get_drvdata(dev); |
| 390 | struct sun4i_spi *sspi = spi_master_get_devdata(master); |
| 391 | int ret; |
| 392 | |
| 393 | ret = clk_prepare_enable(sspi->hclk); |
| 394 | if (ret) { |
| 395 | dev_err(dev, "Couldn't enable AHB clock\n"); |
| 396 | goto out; |
| 397 | } |
| 398 | |
| 399 | ret = clk_prepare_enable(sspi->mclk); |
| 400 | if (ret) { |
| 401 | dev_err(dev, "Couldn't enable module clock\n"); |
| 402 | goto err; |
| 403 | } |
| 404 | |
| 405 | sun4i_spi_write(sspi, SUN4I_CTL_REG, |
| 406 | SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP); |
| 407 | |
| 408 | return 0; |
| 409 | |
| 410 | err: |
| 411 | clk_disable_unprepare(sspi->hclk); |
| 412 | out: |
| 413 | return ret; |
| 414 | } |
| 415 | |
| 416 | static int sun4i_spi_runtime_suspend(struct device *dev) |
| 417 | { |
| 418 | struct spi_master *master = dev_get_drvdata(dev); |
| 419 | struct sun4i_spi *sspi = spi_master_get_devdata(master); |
| 420 | |
| 421 | clk_disable_unprepare(sspi->mclk); |
| 422 | clk_disable_unprepare(sspi->hclk); |
| 423 | |
| 424 | return 0; |
| 425 | } |
| 426 | |
| 427 | static int sun4i_spi_probe(struct platform_device *pdev) |
| 428 | { |
| 429 | struct spi_master *master; |
| 430 | struct sun4i_spi *sspi; |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 431 | int ret = 0, irq; |
| 432 | |
| 433 | master = spi_alloc_master(&pdev->dev, sizeof(struct sun4i_spi)); |
| 434 | if (!master) { |
| 435 | dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); |
| 436 | return -ENOMEM; |
| 437 | } |
| 438 | |
| 439 | platform_set_drvdata(pdev, master); |
| 440 | sspi = spi_master_get_devdata(master); |
| 441 | |
YueHaibing | 8c649f4 | 2019-09-04 21:59:11 +0800 | [diff] [blame] | 442 | sspi->base_addr = devm_platform_ioremap_resource(pdev, 0); |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 443 | if (IS_ERR(sspi->base_addr)) { |
| 444 | ret = PTR_ERR(sspi->base_addr); |
| 445 | goto err_free_master; |
| 446 | } |
| 447 | |
| 448 | irq = platform_get_irq(pdev, 0); |
| 449 | if (irq < 0) { |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 450 | ret = -ENXIO; |
| 451 | goto err_free_master; |
| 452 | } |
| 453 | |
| 454 | ret = devm_request_irq(&pdev->dev, irq, sun4i_spi_handler, |
| 455 | 0, "sun4i-spi", sspi); |
| 456 | if (ret) { |
| 457 | dev_err(&pdev->dev, "Cannot request IRQ\n"); |
| 458 | goto err_free_master; |
| 459 | } |
| 460 | |
| 461 | sspi->master = master; |
Michal Suchanek | 0b06d8c | 2016-06-14 12:10:04 +0000 | [diff] [blame] | 462 | master->max_speed_hz = 100 * 1000 * 1000; |
| 463 | master->min_speed_hz = 3 * 1000; |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 464 | master->set_cs = sun4i_spi_set_cs; |
| 465 | master->transfer_one = sun4i_spi_transfer_one; |
| 466 | master->num_chipselect = 4; |
| 467 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; |
Axel Lin | ba47644 | 2014-03-02 22:25:10 +0800 | [diff] [blame] | 468 | master->bits_per_word_mask = SPI_BPW_MASK(8); |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 469 | master->dev.of_node = pdev->dev.of_node; |
| 470 | master->auto_runtime_pm = true; |
Michal Suchanek | 794912c | 2016-06-13 17:46:50 +0000 | [diff] [blame] | 471 | master->max_transfer_size = sun4i_spi_max_transfer_size; |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 472 | |
| 473 | sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); |
| 474 | if (IS_ERR(sspi->hclk)) { |
| 475 | dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); |
| 476 | ret = PTR_ERR(sspi->hclk); |
| 477 | goto err_free_master; |
| 478 | } |
| 479 | |
| 480 | sspi->mclk = devm_clk_get(&pdev->dev, "mod"); |
| 481 | if (IS_ERR(sspi->mclk)) { |
| 482 | dev_err(&pdev->dev, "Unable to acquire module clock\n"); |
| 483 | ret = PTR_ERR(sspi->mclk); |
| 484 | goto err_free_master; |
| 485 | } |
| 486 | |
| 487 | init_completion(&sspi->done); |
| 488 | |
| 489 | /* |
| 490 | * This wake-up/shutdown pattern is to be able to have the |
| 491 | * device woken up, even if runtime_pm is disabled |
| 492 | */ |
| 493 | ret = sun4i_spi_runtime_resume(&pdev->dev); |
| 494 | if (ret) { |
| 495 | dev_err(&pdev->dev, "Couldn't resume the device\n"); |
| 496 | goto err_free_master; |
| 497 | } |
| 498 | |
| 499 | pm_runtime_set_active(&pdev->dev); |
| 500 | pm_runtime_enable(&pdev->dev); |
| 501 | pm_runtime_idle(&pdev->dev); |
| 502 | |
| 503 | ret = devm_spi_register_master(&pdev->dev, master); |
| 504 | if (ret) { |
| 505 | dev_err(&pdev->dev, "cannot register SPI master\n"); |
| 506 | goto err_pm_disable; |
| 507 | } |
| 508 | |
| 509 | return 0; |
| 510 | |
| 511 | err_pm_disable: |
| 512 | pm_runtime_disable(&pdev->dev); |
| 513 | sun4i_spi_runtime_suspend(&pdev->dev); |
| 514 | err_free_master: |
| 515 | spi_master_put(master); |
| 516 | return ret; |
| 517 | } |
| 518 | |
| 519 | static int sun4i_spi_remove(struct platform_device *pdev) |
| 520 | { |
Takuo Koguchi | c810dab | 2017-12-07 16:20:14 +0900 | [diff] [blame] | 521 | pm_runtime_force_suspend(&pdev->dev); |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 522 | |
| 523 | return 0; |
| 524 | } |
| 525 | |
| 526 | static const struct of_device_id sun4i_spi_match[] = { |
| 527 | { .compatible = "allwinner,sun4i-a10-spi", }, |
| 528 | {} |
| 529 | }; |
| 530 | MODULE_DEVICE_TABLE(of, sun4i_spi_match); |
| 531 | |
| 532 | static const struct dev_pm_ops sun4i_spi_pm_ops = { |
| 533 | .runtime_resume = sun4i_spi_runtime_resume, |
| 534 | .runtime_suspend = sun4i_spi_runtime_suspend, |
| 535 | }; |
| 536 | |
| 537 | static struct platform_driver sun4i_spi_driver = { |
| 538 | .probe = sun4i_spi_probe, |
| 539 | .remove = sun4i_spi_remove, |
| 540 | .driver = { |
| 541 | .name = "sun4i-spi", |
Maxime Ripard | b5f6517 | 2014-02-22 22:35:53 +0100 | [diff] [blame] | 542 | .of_match_table = sun4i_spi_match, |
| 543 | .pm = &sun4i_spi_pm_ops, |
| 544 | }, |
| 545 | }; |
| 546 | module_platform_driver(sun4i_spi_driver); |
| 547 | |
| 548 | MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>"); |
| 549 | MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); |
| 550 | MODULE_DESCRIPTION("Allwinner A1X/A20 SPI controller driver"); |
| 551 | MODULE_LICENSE("GPL"); |