Ralf Baechle | 73b4390 | 2008-07-16 16:12:25 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2002 Integrated Device Technology, Inc. |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * DMA register definition. |
| 6 | * |
| 7 | * Author : ryan.holmQVist@idt.com |
| 8 | * Date : 20011005 |
| 9 | */ |
| 10 | |
| 11 | #ifndef _ASM_RC32434_DMA_V_H_ |
| 12 | #define _ASM_RC32434_DMA_V_H_ |
| 13 | |
| 14 | #include <asm/mach-rc32434/dma.h> |
| 15 | #include <asm/mach-rc32434/rc32434.h> |
| 16 | |
| 17 | #define DMA_CHAN_OFFSET 0x14 |
| 18 | #define IS_DMA_USED(X) (((X) & \ |
| 19 | (DMA_DESC_FINI | DMA_DESC_DONE | DMA_DESC_TERM)) \ |
| 20 | != 0) |
| 21 | #define DMA_COUNT(count) ((count) & DMA_DESC_COUNT_MSK) |
| 22 | |
| 23 | #define DMA_HALT_TIMEOUT 500 |
| 24 | |
| 25 | static inline int rc32434_halt_dma(struct dma_reg *ch) |
| 26 | { |
| 27 | int timeout = 1; |
| 28 | if (__raw_readl(&ch->dmac) & DMA_CHAN_RUN_BIT) { |
| 29 | __raw_writel(0, &ch->dmac); |
| 30 | for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) { |
| 31 | if (__raw_readl(&ch->dmas) & DMA_STAT_HALT) { |
| 32 | __raw_writel(0, &ch->dmas); |
| 33 | break; |
| 34 | } |
| 35 | } |
| 36 | } |
| 37 | |
| 38 | return timeout ? 0 : 1; |
| 39 | } |
| 40 | |
| 41 | static inline void rc32434_start_dma(struct dma_reg *ch, u32 dma_addr) |
| 42 | { |
| 43 | __raw_writel(0, &ch->dmandptr); |
| 44 | __raw_writel(dma_addr, &ch->dmadptr); |
| 45 | } |
| 46 | |
| 47 | static inline void rc32434_chain_dma(struct dma_reg *ch, u32 dma_addr) |
| 48 | { |
| 49 | __raw_writel(dma_addr, &ch->dmandptr); |
| 50 | } |
| 51 | |
| 52 | #endif /* _ASM_RC32434_DMA_V_H_ */ |