blob: c4207cf9bb17ffb28147c51ce6a38ed54c01c4ff [file] [log] [blame]
Thomas Gleixnerec8f24b2019-05-19 13:07:45 +01001# SPDX-License-Identifier: GPL-2.0-only
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01002config ARM64
3 def_bool y
Suthikulpanit, Suraveeb6197b92015-06-10 11:08:53 -05004 select ACPI_CCA_REQUIRED if ACPI
Lorenzo Pieralisid8f4f162015-03-24 17:58:51 +00005 select ACPI_GENERIC_GSI if ACPI
Fu Wei5f1ae4e2017-04-01 01:51:01 +08006 select ACPI_GTDT if ACPI
Lorenzo Pieralisic6bb8f892017-06-14 17:37:12 +01007 select ACPI_IORT if ACPI
Al Stone6933de02015-03-24 14:02:51 +00008 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
Sinan Kaya521461732018-12-19 22:46:57 +00009 select ACPI_MCFG if (ACPI && PCI)
Aleksey Makarov888125a2016-09-27 23:54:14 +030010 select ACPI_SPCR_TABLE if ACPI
Jeremy Linton0ce82232018-05-11 18:58:01 -050011 select ACPI_PPTT if ACPI
Zong Li09587a02020-06-03 16:04:02 -070012 select ARCH_HAS_DEBUG_WX
Dave Martinab7876a2020-03-16 16:50:47 +000013 select ARCH_BINFMT_ELF_STATE
Masami Hiramatsucd9bc2c2021-10-21 09:55:09 +090014 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
Anshuman Khandual1e866972021-05-04 18:38:21 -070015 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
Anshuman Khandual91024b32021-05-04 18:38:17 -070016 select ARCH_ENABLE_MEMORY_HOTPLUG
17 select ARCH_ENABLE_MEMORY_HOTREMOVE
Anshuman Khandual66f24fa2021-05-04 18:38:25 -070018 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
Anshuman Khandual1e866972021-05-04 18:38:21 -070019 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
Anshuman Khandualc2280be2021-05-04 18:38:09 -070020 select ARCH_HAS_CACHE_LINE_SIZE
Laura Abbottec6d06e2017-01-10 13:35:50 -080021 select ARCH_HAS_DEBUG_VIRTUAL
Anshuman Khandual399145f2020-06-04 16:47:15 -070022 select ARCH_HAS_DEBUG_VM_PGTABLE
Christoph Hellwig13bf5ce2019-03-25 15:44:06 +010023 select ARCH_HAS_DMA_PREP_COHERENT
Jon Masters38b04a72016-06-20 13:56:13 +030024 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
Robin Murphye75bef22018-04-24 16:25:47 +010025 select ARCH_HAS_FAST_MULTIPLIER
Daniel Micay6974f0c2017-07-12 14:36:10 -070026 select ARCH_HAS_FORTIFY_SOURCE
Riku Voipio957e3fa2014-12-12 16:57:44 -080027 select ARCH_HAS_GCOV_PROFILE_ALL
Alexandre Ghiti4eb07162019-05-13 17:19:04 -070028 select ARCH_HAS_GIGANTIC_PAGE
Alexander Potapenko5e4c7542016-06-16 18:39:52 +020029 select ARCH_HAS_KCOV
Christoph Hellwigd8ae8a32019-05-13 17:18:30 -070030 select ARCH_HAS_KEEPINITRD
Mathieu Desnoyersf1e3a122018-01-29 15:20:19 -050031 select ARCH_HAS_MEMBARRIER_SYNC_CORE
Daniel Borkmann0ebeea82020-05-15 12:11:16 +020032 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
Robin Murphy73b20c82019-07-16 16:30:51 -070033 select ARCH_HAS_PTE_DEVMAP
Laurent Dufour3010a5e2018-06-07 17:06:08 -070034 select ARCH_HAS_PTE_SPECIAL
Christoph Hellwig347cb6a2019-01-07 13:36:20 -050035 select ARCH_HAS_SETUP_DMA_OPS
Ard Biesheuvel4739d532019-05-23 11:22:54 +010036 select ARCH_HAS_SET_DIRECT_MAP
Daniel Borkmannd2852a22017-02-21 16:09:33 +010037 select ARCH_HAS_SET_MEMORY
Mark Brown5fc57df2020-09-14 16:34:09 +010038 select ARCH_STACKWALK
Laura Abbottad21fc42017-02-06 16:31:57 -080039 select ARCH_HAS_STRICT_KERNEL_RWX
40 select ARCH_HAS_STRICT_MODULE_RWX
Christoph Hellwig886643b2018-10-08 09:12:01 +020041 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
42 select ARCH_HAS_SYNC_DMA_FOR_CPU
Mark Rutland4378a7d2018-07-11 14:56:56 +010043 select ARCH_HAS_SYSCALL_WRAPPER
Christoph Hellwigdc2acde2018-12-21 22:14:44 +010044 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +010045 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
Kefeng Wang63703f32021-06-30 18:52:20 -070046 select ARCH_HAS_ZONE_DMA_SET if EXPERT
Dave Martinab7876a2020-03-16 16:50:47 +000047 select ARCH_HAVE_ELF_PROT
Stephen Boyd396a5d42017-09-27 08:51:30 -070048 select ARCH_HAVE_NMI_SAFE_CMPXCHG
Thomas Gleixner7ef858d2019-10-15 21:17:49 +020049 select ARCH_INLINE_READ_LOCK if !PREEMPTION
50 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
51 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
52 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
53 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
54 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
55 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
56 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
57 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
58 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
59 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
60 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
61 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
62 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
63 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
64 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
65 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
66 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
67 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
68 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
69 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
70 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
71 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
72 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
73 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
74 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
Mike Rapoport350e88b2019-05-13 17:22:59 -070075 select ARCH_KEEP_MEMBLOCK
Sudeep Hollac63c8702014-05-09 10:33:01 +010076 select ARCH_USE_CMPXCHG_LOCKREF
Will Deaconbf7f15c2020-03-18 08:28:31 +000077 select ARCH_USE_GNU_PROPERTY
Anshuman Khandualdce44562021-04-29 22:55:15 -070078 select ARCH_USE_MEMTEST
Will Deacon087133a2017-10-12 13:20:50 +010079 select ARCH_USE_QUEUED_RWLOCKS
Will Deaconc1109042018-03-13 20:45:45 +000080 select ARCH_USE_QUEUED_SPINLOCKS
Mark Brown50479d52020-05-01 12:54:30 +010081 select ARCH_USE_SYM_ANNOTATIONS
Mike Rapoport5d6ad662020-12-14 19:10:30 -080082 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
Anshuman Khandual855f9a82021-05-04 18:38:13 -070083 select ARCH_SUPPORTS_HUGETLBFS
Jonathan (Zhixiong) Zhangc484f252017-06-08 18:25:29 +010084 select ARCH_SUPPORTS_MEMORY_FAILURE
Sami Tolvanen52875692020-04-27 09:00:16 -070085 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
Sami Tolvanen112b6a82020-12-11 10:46:33 -080086 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
87 select ARCH_SUPPORTS_LTO_CLANG_THIN
Sami Tolvanen9186ad82021-04-08 11:28:43 -070088 select ARCH_SUPPORTS_CFI_CLANG
Peter Zijlstra4badad32014-06-06 19:53:16 +020089 select ARCH_SUPPORTS_ATOMIC_RMW
Nick Desaulniers42a7ba12021-09-10 16:40:44 -070090 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
Ganapatrao Kulkarni56166232016-04-08 15:50:28 -070091 select ARCH_SUPPORTS_NUMA_BALANCING
Yury Norov84c187a2019-05-07 13:52:28 -070092 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
Daniel Borkmann81c22042019-12-09 16:08:03 +010093 select ARCH_WANT_DEFAULT_BPF_JIT
Alexandre Ghiti67f39772019-09-23 15:38:47 -070094 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
Catalin Marinasb6f35982013-01-29 18:25:41 +000095 select ARCH_WANT_FRAME_POINTERS
Alexandre Ghiti3876d4a2019-06-27 15:00:11 -070096 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
Nathan Chancellor59612b22020-11-19 13:46:56 -070097 select ARCH_WANT_LD_ORPHAN_WARN
Nick Desaulniers51c2ee62021-06-21 16:18:22 -070098 select ARCH_WANTS_NO_INSTR
Yang Shif0b7f8a42016-02-05 15:50:18 -080099 select ARCH_HAS_UBSAN_SANITIZE_ALL
Catalin Marinas25c92a32012-12-18 15:26:13 +0000100 select ARM_AMBA
Mark Rutland1aee5d72012-11-20 10:06:00 +0000101 select ARM_ARCH_TIMER
Catalin Marinasc4188ed2013-01-14 12:39:31 +0000102 select ARM_GIC
AKASHI Takahiro875cbf32014-07-04 08:28:30 +0100103 select AUDIT_ARCH_COMPAT_GENERIC
Arnd Bergmann3ee803642016-06-15 15:47:33 -0500104 select ARM_GIC_V2M if PCI
Marc Zyngier021f6532014-06-30 16:01:31 +0100105 select ARM_GIC_V3
Arnd Bergmann3ee803642016-06-15 15:47:33 -0500106 select ARM_GIC_V3_ITS if PCI
Mark Rutlandbff607922015-07-31 15:46:16 +0100107 select ARM_PSCI_FW
Shile Zhang10916702019-12-04 08:46:31 +0800108 select BUILDTIME_TABLE_SORT
Catalin Marinasdb2789b2012-12-18 15:27:25 +0000109 select CLONE_BACKWARDS
Deepak Saxena7ca2ef33e2012-09-22 10:33:36 -0700110 select COMMON_CLK
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000111 select CPU_PM if (SUSPEND || CPU_IDLE)
Ard Biesheuvel7481cdd2018-08-27 13:02:44 +0200112 select CRC32
Will Deacon7bc13fd2013-11-06 19:32:13 +0000113 select DCACHE_WORD_ACCESS
Christoph Hellwig0c3b3172018-11-04 20:29:28 +0100114 select DMA_DIRECT_REMAP
Catalin Marinasef375662015-07-07 17:15:39 +0100115 select EDAC_SUPPORT
Yang Shi2f34f172015-11-09 10:09:55 -0800116 select FRAME_POINTER
Laura Abbottd4932f92014-10-09 15:26:44 -0700117 select GENERIC_ALLOCATOR
Juri Lelli2ef7a292017-05-31 17:59:28 +0100118 select GENERIC_ARCH_TOPOLOGY
Will Deacon4b3dc962015-05-29 18:28:44 +0100119 select GENERIC_CLOCKEVENTS_BROADCAST
Ard Biesheuvel3be1a5c2014-03-04 01:10:04 +0000120 select GENERIC_CPU_AUTOPROBE
Mian Yousaf Kaukab61ae1322019-04-15 16:21:29 -0500121 select GENERIC_CPU_VULNERABILITIES
Mark Salterbf4b5582014-04-07 15:39:52 -0700122 select GENERIC_EARLY_IOREMAP
Yury Norov98c5ec72021-02-25 05:56:59 -0800123 select GENERIC_FIND_FIRST_BIT
Leo Yan2314ee42015-08-21 04:40:22 +0100124 select GENERIC_IDLE_POLL_SETUP
Marc Zyngierd3afc7f2020-04-25 15:03:47 +0100125 select GENERIC_IRQ_IPI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100126 select GENERIC_IRQ_PROBE
127 select GENERIC_IRQ_SHOW
Sudeep Holla6544e672015-04-22 18:16:33 +0100128 select GENERIC_IRQ_SHOW_LEVEL
Palmer Dabbelt6585bd82020-07-09 12:05:36 -0700129 select GENERIC_LIB_DEVMEM_IS_ALLOWED
Arnd Bergmanncb61f672014-11-19 14:09:07 +0100130 select GENERIC_PCI_IOMAP
Steven Price102f45f2020-02-03 17:36:29 -0800131 select GENERIC_PTDUMP
Stephen Boyd65cd4f62013-07-18 16:21:18 -0700132 select GENERIC_SCHED_CLOCK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100133 select GENERIC_SMP_IDLE_THREAD
134 select GENERIC_TIME_VSYSCALL
Vincenzo Frascino28b1a822019-06-21 10:52:31 +0100135 select GENERIC_GETTIMEOFDAY
Andrei Vagin9614cc52020-06-24 01:33:21 -0700136 select GENERIC_VDSO_TIME_NS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100137 select HARDIRQS_SW_RESEND
Kalesh Singh45544ee2020-10-14 00:53:07 +0000138 select HAVE_MOVE_PMD
Kalesh Singhf5308c82020-12-14 19:07:35 -0800139 select HAVE_MOVE_PUD
Christoph Hellwigeb01d422018-11-15 20:05:32 +0100140 select HAVE_PCI
Tomasz Nowicki9f9a35a2016-12-01 21:51:12 +0800141 select HAVE_ACPI_APEI if (ACPI && EFI)
Steve Capper5284e1b2014-10-24 13:22:20 +0100142 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
AKASHI Takahiro875cbf32014-07-04 08:28:30 +0100143 select HAVE_ARCH_AUDITSYSCALL
Yalin Wang8e7a4ce2014-11-03 03:02:23 +0100144 select HAVE_ARCH_BITREVERSE
Amit Daniel Kachhap689eae422020-03-13 14:34:58 +0530145 select HAVE_ARCH_COMPILER_H
Ard Biesheuvel324420b2016-02-16 13:52:35 +0100146 select HAVE_ARCH_HUGE_VMAP
Jiang Liu9732caf2014-01-07 22:17:13 +0800147 select HAVE_ARCH_JUMP_LABEL
Ard Biesheuvelc2961462018-09-18 23:51:38 -0700148 select HAVE_ARCH_JUMP_LABEL_RELATIVE
Will Deacone17d8022017-11-15 17:36:40 -0800149 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
Lecopzer Chen71b613f2021-03-24 12:05:20 +0800150 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
Andrey Konovalov2d4acb92018-12-28 00:31:07 -0800151 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
Andrey Konovalov94ab5b62020-12-22 12:02:20 -0800152 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
Marco Elver840b2392021-02-25 17:19:03 -0800153 select HAVE_ARCH_KFENCE
Vijaya Kumar K95292472014-01-28 11:20:22 +0000154 select HAVE_ARCH_KGDB
Daniel Cashman8f0d3aa2016-01-14 15:20:01 -0800155 select HAVE_ARCH_MMAP_RND_BITS
156 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
Ard Biesheuvel271ca782018-08-21 21:56:00 -0700157 select HAVE_ARCH_PREL32_RELOCATIONS
Kees Cook70918772021-04-01 16:23:46 -0700158 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +0000159 select HAVE_ARCH_SECCOMP_FILTER
Laura Abbott0b3e3362018-07-20 14:41:54 -0700160 select HAVE_ARCH_STACKLEAK
Kees Cook9e8084d2017-08-16 14:05:09 -0700161 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100162 select HAVE_ARCH_TRACEHOOK
Yang Shi8ee70872016-04-18 11:16:14 -0700163 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
Mark Rutlande3067862017-07-21 14:25:33 +0100164 select HAVE_ARCH_VMAP_STACK
Yang Shi8ee70872016-04-18 11:16:14 -0700165 select HAVE_ARM_SMCCC
Masahiro Yamada2ff2b7e2019-08-19 14:54:20 +0900166 select HAVE_ASM_MODVERSIONS
Daniel Borkmann60777762016-05-13 19:08:28 +0200167 select HAVE_EBPF_JIT
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +0100168 select HAVE_C_RECORDMCOUNT
Steve Capper5284e1b2014-10-24 13:22:20 +0100169 select HAVE_CMPXCHG_DOUBLE
Will Deacon95eff6b2015-05-29 14:57:47 +0100170 select HAVE_CMPXCHG_LOCAL
Yang Shi8ee70872016-04-18 11:16:14 -0700171 select HAVE_CONTEXT_TRACKING
Catalin Marinasb69ec422012-10-08 16:28:11 -0700172 select HAVE_DEBUG_KMEMLEAK
Laura Abbott6ac21042013-12-12 19:28:33 +0000173 select HAVE_DMA_CONTIGUOUS
AKASHI Takahirobd7d38d2014-04-30 10:54:34 +0100174 select HAVE_DYNAMIC_FTRACE
Torsten Duwe3b23e4992019-02-08 16:10:19 +0100175 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
176 if $(cc-option,-fpatchable-function-entry=2)
Sami Tolvanena31d7932020-12-11 10:46:32 -0800177 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
178 if DYNAMIC_FTRACE_WITH_REGS
Will Deacon50afc332013-12-16 17:50:08 +0000179 select HAVE_EFFICIENT_UNALIGNED_ACCESS
Christoph Hellwig67a929e2019-07-11 20:57:14 -0700180 select HAVE_FAST_GUP
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +0100181 select HAVE_FTRACE_MCOUNT_RECORD
AKASHI Takahiro819e50e2014-04-30 18:54:33 +0900182 select HAVE_FUNCTION_TRACER
Leo Yan42d038c2019-08-06 18:00:14 +0800183 select HAVE_FUNCTION_ERROR_INJECTION
AKASHI Takahiro819e50e2014-04-30 18:54:33 +0900184 select HAVE_FUNCTION_GRAPH_TRACER
Emese Revfy6b90bd42016-05-24 00:09:38 +0200185 select HAVE_GCC_PLUGINS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100186 select HAVE_HW_BREAKPOINT if PERF_EVENTS
Will Deacon24da2082015-11-23 15:12:59 +0000187 select HAVE_IRQ_TIME_ACCOUNTING
Sean Christophersone26bb752021-09-21 15:22:31 -0700188 select HAVE_KVM
Stephen Boyd396a5d42017-09-27 08:51:30 -0700189 select HAVE_NMI
Mark Rutland55834a72014-02-07 17:12:45 +0000190 select HAVE_PATA_PLATFORM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100191 select HAVE_PERF_EVENTS
Jean Pihet2ee0d7f2014-02-03 19:18:27 +0100192 select HAVE_PERF_REGS
193 select HAVE_PERF_USER_STACK_DUMP
David A. Long0a8ea522016-07-08 12:35:45 -0400194 select HAVE_REGS_AND_STACK_ACCESS_API
Nicolas Saenz Juliennea68773b2021-10-18 16:47:13 +0200195 select HAVE_POSIX_CPU_TIMERS_TASK_WORK
Masami Hiramatsua823c352019-04-12 23:22:01 +0900196 select HAVE_FUNCTION_ARG_ACCESS_API
Vladimir Murzin98346022020-01-20 10:36:02 +0000197 select HAVE_FUTEX_CMPXCHG if FUTEX
Peter Zijlstraff2e6d722020-02-03 17:37:02 -0800198 select MMU_GATHER_RCU_TABLE_FREE
Will Deacon409d5db2018-06-20 14:46:50 +0100199 select HAVE_RSEQ
Masahiro Yamadad148eac2018-06-14 19:36:45 +0900200 select HAVE_STACKPROTECTOR
AKASHI Takahiro055b1212014-04-30 10:54:36 +0100201 select HAVE_SYSCALL_TRACEPOINTS
Sandeepa Prabhu2dd0e8d2016-07-08 12:35:48 -0400202 select HAVE_KPROBES
Masami Hiramatsucd1ee3b2017-02-06 18:54:33 +0900203 select HAVE_KRETPROBES
Vincenzo Frascino28b1a822019-06-21 10:52:31 +0100204 select HAVE_GENERIC_VDSO
Robin Murphy876945d2015-10-01 20:14:00 +0100205 select IOMMU_DMA if IOMMU_SUPPORT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100206 select IRQ_DOMAIN
Anders Roxelle8557d12015-04-27 22:53:09 +0200207 select IRQ_FORCED_THREADING
Lecopzer Chenacc30422021-03-24 12:05:22 +0800208 select KASAN_VMALLOC if KASAN_GENERIC
Catalin Marinasfea2aca2012-10-16 11:26:57 +0100209 select MODULES_USE_ELF_RELA
Christoph Hellwigf616ab52018-05-09 06:53:49 +0200210 select NEED_DMA_MAP_STATE
Christoph Hellwig86596f02018-04-05 09:44:52 +0200211 select NEED_SG_DMA_LENGTH
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100212 select OF
213 select OF_EARLY_FLATTREE
Christoph Hellwig2eac9c22018-11-15 20:05:33 +0100214 select PCI_DOMAINS_GENERIC if PCI
Sinan Kaya521461732018-12-19 22:46:57 +0000215 select PCI_ECAM if (ACPI && PCI)
Christoph Hellwig20f1b792018-11-15 20:05:34 +0100216 select PCI_SYSCALL if PCI
Catalin Marinasaa1e8ec12013-02-28 18:14:37 +0000217 select POWER_RESET
218 select POWER_SUPPLY
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100219 select SPARSE_IRQ
Christoph Hellwig09230cb2018-04-24 09:00:54 +0200220 select SWIOTLB
Catalin Marinas7ac57a82012-10-08 16:28:16 -0700221 select SYSCTL_EXCEPTION_TRACE
Mark Rutlandc02433d2016-11-03 20:23:13 +0000222 select THREAD_INFO_IN_TASK
Axel Rasmussen7677f7f2021-05-04 18:35:36 -0700223 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
Masahiro Yamada4aae6832021-07-31 14:22:32 +0900224 select TRACE_IRQFLAGS_SUPPORT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100225 help
226 ARM 64-bit (AArch64) Linux support.
227
228config 64BIT
229 def_bool y
230
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100231config MMU
232 def_bool y
233
Mark Rutland030c4d22016-05-31 15:57:59 +0100234config ARM64_PAGE_SHIFT
235 int
236 default 16 if ARM64_64K_PAGES
237 default 14 if ARM64_16K_PAGES
238 default 12
239
Gavin Shanc0d6de32020-09-10 19:59:35 +1000240config ARM64_CONT_PTE_SHIFT
Mark Rutland030c4d22016-05-31 15:57:59 +0100241 int
242 default 5 if ARM64_64K_PAGES
243 default 7 if ARM64_16K_PAGES
244 default 4
245
Gavin Shane6765942020-09-10 19:59:36 +1000246config ARM64_CONT_PMD_SHIFT
247 int
248 default 5 if ARM64_64K_PAGES
249 default 5 if ARM64_16K_PAGES
250 default 4
251
Daniel Cashman8f0d3aa2016-01-14 15:20:01 -0800252config ARCH_MMAP_RND_BITS_MIN
253 default 14 if ARM64_64K_PAGES
254 default 16 if ARM64_16K_PAGES
255 default 18
256
257# max bits determined by the following formula:
258# VA_BITS - PAGE_SHIFT - 3
259config ARCH_MMAP_RND_BITS_MAX
260 default 19 if ARM64_VA_BITS=36
261 default 24 if ARM64_VA_BITS=39
262 default 27 if ARM64_VA_BITS=42
263 default 30 if ARM64_VA_BITS=47
264 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
265 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
266 default 33 if ARM64_VA_BITS=48
267 default 14 if ARM64_64K_PAGES
268 default 16 if ARM64_16K_PAGES
269 default 18
270
271config ARCH_MMAP_RND_COMPAT_BITS_MIN
272 default 7 if ARM64_64K_PAGES
273 default 9 if ARM64_16K_PAGES
274 default 11
275
276config ARCH_MMAP_RND_COMPAT_BITS_MAX
277 default 16
278
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -0700279config NO_IOPORT_MAP
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100280 def_bool y if !PCI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100281
282config STACKTRACE_SUPPORT
283 def_bool y
284
Jeff Vander Stoepbf0c4e02015-08-18 20:50:10 +0100285config ILLEGAL_POINTER_VALUE
286 hex
287 default 0xdead000000000000
288
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100289config LOCKDEP_SUPPORT
290 def_bool y
291
Dave P Martin9fb74102015-07-24 16:37:48 +0100292config GENERIC_BUG
293 def_bool y
294 depends on BUG
295
296config GENERIC_BUG_RELATIVE_POINTERS
297 def_bool y
298 depends on GENERIC_BUG
299
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100300config GENERIC_HWEIGHT
301 def_bool y
302
303config GENERIC_CSUM
304 def_bool y
305
306config GENERIC_CALIBRATE_DELAY
307 def_bool y
308
Oscar Salvadorca6e51d2021-05-04 18:39:54 -0700309config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
310 def_bool y
311
Will Deacon4b3dc962015-05-29 18:28:44 +0100312config SMP
313 def_bool y
314
Ard Biesheuvel4cfb3612013-07-09 14:18:12 +0100315config KERNEL_MODE_NEON
316 def_bool y
317
Rob Herring92cc15f2014-04-18 17:19:59 -0500318config FIX_EARLYCON_MEM
319 def_bool y
320
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700321config PGTABLE_LEVELS
322 int
Suzuki K. Poulose21539932015-10-19 14:19:38 +0100323 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700324 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
Steve Capperb6d00d42019-08-07 16:55:22 +0100325 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700326 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100327 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
328 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700329
Pratyush Anand9842cea2016-11-02 14:40:46 +0530330config ARCH_SUPPORTS_UPROBES
331 def_bool y
332
Ard Biesheuvel8f360942017-06-14 12:43:55 +0200333config ARCH_PROC_KCORE_TEXT
334 def_bool y
335
Vladimir Murzin8bf92842020-01-15 14:18:25 +0000336config BROKEN_GAS_INST
337 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
338
Steve Capper6bd1d0b2019-08-07 16:55:15 +0100339config KASAN_SHADOW_OFFSET
340 hex
Andrey Konovalov0fea6e92020-12-22 12:02:06 -0800341 depends on KASAN_GENERIC || KASAN_SW_TAGS
Ard Biesheuvelf4693c22020-10-08 17:36:00 +0200342 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
343 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
344 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
345 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
346 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
347 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
348 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
349 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
350 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
351 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
Steve Capper6bd1d0b2019-08-07 16:55:15 +0100352 default 0xffffffffffffffff
353
Olof Johansson6a377492015-07-20 12:09:16 -0700354source "arch/arm64/Kconfig.platforms"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100355
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100356menu "Kernel Features"
357
Andre Przywarac0a01b82014-11-14 15:54:12 +0000358menu "ARM errata workarounds via the alternatives framework"
359
Suzuki K Poulosec9460dc2018-11-30 17:18:00 +0000360config ARM64_WORKAROUND_CLEAN_CACHE
Will Deaconbc15cf72019-04-29 14:21:11 +0100361 bool
Suzuki K Poulosec9460dc2018-11-30 17:18:00 +0000362
Andre Przywarac0a01b82014-11-14 15:54:12 +0000363config ARM64_ERRATUM_826319
364 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
365 default y
Suzuki K Poulosec9460dc2018-11-30 17:18:00 +0000366 select ARM64_WORKAROUND_CLEAN_CACHE
Andre Przywarac0a01b82014-11-14 15:54:12 +0000367 help
368 This option adds an alternative code sequence to work around ARM
369 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
370 AXI master interface and an L2 cache.
371
372 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
373 and is unable to accept a certain write via this interface, it will
374 not progress on read data presented on the read data channel and the
375 system can deadlock.
376
377 The workaround promotes data cache clean instructions to
378 data cache clean-and-invalidate.
379 Please note that this does not necessarily enable the workaround,
380 as it depends on the alternative framework, which will only patch
381 the kernel if an affected CPU is detected.
382
383 If unsure, say Y.
384
385config ARM64_ERRATUM_827319
386 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
387 default y
Suzuki K Poulosec9460dc2018-11-30 17:18:00 +0000388 select ARM64_WORKAROUND_CLEAN_CACHE
Andre Przywarac0a01b82014-11-14 15:54:12 +0000389 help
390 This option adds an alternative code sequence to work around ARM
391 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
392 master interface and an L2 cache.
393
394 Under certain conditions this erratum can cause a clean line eviction
395 to occur at the same time as another transaction to the same address
396 on the AMBA 5 CHI interface, which can cause data corruption if the
397 interconnect reorders the two transactions.
398
399 The workaround promotes data cache clean instructions to
400 data cache clean-and-invalidate.
401 Please note that this does not necessarily enable the workaround,
402 as it depends on the alternative framework, which will only patch
403 the kernel if an affected CPU is detected.
404
405 If unsure, say Y.
406
407config ARM64_ERRATUM_824069
408 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
409 default y
Suzuki K Poulosec9460dc2018-11-30 17:18:00 +0000410 select ARM64_WORKAROUND_CLEAN_CACHE
Andre Przywarac0a01b82014-11-14 15:54:12 +0000411 help
412 This option adds an alternative code sequence to work around ARM
413 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
414 to a coherent interconnect.
415
416 If a Cortex-A53 processor is executing a store or prefetch for
417 write instruction at the same time as a processor in another
418 cluster is executing a cache maintenance operation to the same
419 address, then this erratum might cause a clean cache line to be
420 incorrectly marked as dirty.
421
422 The workaround promotes data cache clean instructions to
423 data cache clean-and-invalidate.
424 Please note that this option does not necessarily enable the
425 workaround, as it depends on the alternative framework, which will
426 only patch the kernel if an affected CPU is detected.
427
428 If unsure, say Y.
429
430config ARM64_ERRATUM_819472
431 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
432 default y
Suzuki K Poulosec9460dc2018-11-30 17:18:00 +0000433 select ARM64_WORKAROUND_CLEAN_CACHE
Andre Przywarac0a01b82014-11-14 15:54:12 +0000434 help
435 This option adds an alternative code sequence to work around ARM
436 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
437 present when it is connected to a coherent interconnect.
438
439 If the processor is executing a load and store exclusive sequence at
440 the same time as a processor in another cluster is executing a cache
441 maintenance operation to the same address, then this erratum might
442 cause data corruption.
443
444 The workaround promotes data cache clean instructions to
445 data cache clean-and-invalidate.
446 Please note that this does not necessarily enable the workaround,
447 as it depends on the alternative framework, which will only patch
448 the kernel if an affected CPU is detected.
449
450 If unsure, say Y.
451
452config ARM64_ERRATUM_832075
453 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
454 default y
455 help
456 This option adds an alternative code sequence to work around ARM
457 erratum 832075 on Cortex-A57 parts up to r1p2.
458
459 Affected Cortex-A57 parts might deadlock when exclusive load/store
460 instructions to Write-Back memory are mixed with Device loads.
461
462 The workaround is to promote device loads to use Load-Acquire
463 semantics.
464 Please note that this does not necessarily enable the workaround,
465 as it depends on the alternative framework, which will only patch
466 the kernel if an affected CPU is detected.
467
468 If unsure, say Y.
469
Marc Zyngier498cd5c2015-11-16 10:28:18 +0000470config ARM64_ERRATUM_834220
471 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
472 depends on KVM
473 default y
474 help
475 This option adds an alternative code sequence to work around ARM
476 erratum 834220 on Cortex-A57 parts up to r1p2.
477
478 Affected Cortex-A57 parts might report a Stage 2 translation
479 fault as the result of a Stage 1 fault for load crossing a
480 page boundary when there is a permission or device memory
481 alignment fault at Stage 1 and a translation fault at Stage 2.
482
483 The workaround is to verify that the Stage 1 translation
484 doesn't generate a fault before handling the Stage 2 fault.
485 Please note that this does not necessarily enable the workaround,
486 as it depends on the alternative framework, which will only patch
487 the kernel if an affected CPU is detected.
488
489 If unsure, say Y.
490
Will Deacon905e8c52015-03-23 19:07:02 +0000491config ARM64_ERRATUM_845719
492 bool "Cortex-A53: 845719: a load might read incorrect data"
493 depends on COMPAT
494 default y
495 help
496 This option adds an alternative code sequence to work around ARM
497 erratum 845719 on Cortex-A53 parts up to r0p4.
498
499 When running a compat (AArch32) userspace on an affected Cortex-A53
500 part, a load at EL0 from a virtual address that matches the bottom 32
501 bits of the virtual address used by a recent load at (AArch64) EL1
502 might return incorrect data.
503
504 The workaround is to write the contextidr_el1 register on exception
505 return to a 32-bit task.
506 Please note that this does not necessarily enable the workaround,
507 as it depends on the alternative framework, which will only patch
508 the kernel if an affected CPU is detected.
509
510 If unsure, say Y.
511
Will Deacondf057cc2015-03-17 12:15:02 +0000512config ARM64_ERRATUM_843419
513 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
Will Deacondf057cc2015-03-17 12:15:02 +0000514 default y
Ard Biesheuvela257e022018-03-06 17:15:33 +0000515 select ARM64_MODULE_PLTS if MODULES
Will Deacondf057cc2015-03-17 12:15:02 +0000516 help
Will Deacon6ffe9922016-08-22 11:58:36 +0100517 This option links the kernel with '--fix-cortex-a53-843419' and
Ard Biesheuvela257e022018-03-06 17:15:33 +0000518 enables PLT support to replace certain ADRP instructions, which can
519 cause subsequent memory accesses to use an incorrect address on
520 Cortex-A53 parts up to r0p4.
Will Deacondf057cc2015-03-17 12:15:02 +0000521
522 If unsure, say Y.
523
Masahiro Yamada987fdfe2021-03-24 16:11:28 +0900524config ARM64_LD_HAS_FIX_ERRATUM_843419
525 def_bool $(ld-option,--fix-cortex-a53-843419)
526
Suzuki K Pouloseece13972018-03-26 15:12:49 +0100527config ARM64_ERRATUM_1024718
528 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
529 default y
530 help
Will Deaconbc15cf72019-04-29 14:21:11 +0100531 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
Suzuki K Pouloseece13972018-03-26 15:12:49 +0100532
Suzuki K Poulosec0b15c22021-02-03 23:00:57 +0000533 Affected Cortex-A55 cores (all revisions) could cause incorrect
Suzuki K Pouloseece13972018-03-26 15:12:49 +0100534 update of the hardware dirty bit when the DBM/AP bits are updated
Will Deaconbc15cf72019-04-29 14:21:11 +0100535 without a break-before-make. The workaround is to disable the usage
Suzuki K Pouloseece13972018-03-26 15:12:49 +0100536 of hardware DBM locally on the affected cores. CPUs not affected by
Will Deaconbc15cf72019-04-29 14:21:11 +0100537 this erratum will continue to use the feature.
Jungseok Leee41ceed2014-05-12 10:40:38 +0100538
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100539 If unsure, say Y.
Jungseok Leee41ceed2014-05-12 10:40:38 +0100540
Marc Zyngiera5325082019-05-23 11:24:50 +0100541config ARM64_ERRATUM_1418040
Marc Zyngier69893032019-04-15 13:03:54 +0100542 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
Marc Zyngier95b861a42018-09-27 17:15:34 +0100543 default y
Marc Zyngierc2b5bba2019-04-15 13:03:52 +0100544 depends on COMPAT
Marc Zyngier95b861a42018-09-27 17:15:34 +0100545 help
Will Deacon24cf2622019-05-01 15:45:36 +0100546 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
Marc Zyngiera5325082019-05-23 11:24:50 +0100547 errata 1188873 and 1418040.
Marc Zyngier95b861a42018-09-27 17:15:34 +0100548
Marc Zyngiera5325082019-05-23 11:24:50 +0100549 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
Marc Zyngier69893032019-04-15 13:03:54 +0100550 cause register corruption when accessing the timer registers
551 from AArch32 userspace.
Marc Zyngier95b861a42018-09-27 17:15:34 +0100552
553 If unsure, say Y.
554
Andrew Scull02ab1f52020-05-04 10:48:58 +0100555config ARM64_WORKAROUND_SPECULATIVE_AT
Steven Pricee85d68f2019-12-16 11:56:29 +0000556 bool
557
Marc Zyngiera457b0f2018-12-06 17:31:26 +0000558config ARM64_ERRATUM_1165522
Andrew Scull02ab1f52020-05-04 10:48:58 +0100559 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
Marc Zyngiera457b0f2018-12-06 17:31:26 +0000560 default y
Andrew Scull02ab1f52020-05-04 10:48:58 +0100561 select ARM64_WORKAROUND_SPECULATIVE_AT
Marc Zyngiera457b0f2018-12-06 17:31:26 +0000562 help
Will Deaconbc15cf72019-04-29 14:21:11 +0100563 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
Marc Zyngiera457b0f2018-12-06 17:31:26 +0000564
565 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
566 corrupted TLBs by speculating an AT instruction during a guest
567 context switch.
568
569 If unsure, say Y.
570
Andrew Scull02ab1f52020-05-04 10:48:58 +0100571config ARM64_ERRATUM_1319367
572 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
Steven Price275fa0e2019-12-16 11:56:31 +0000573 default y
Andrew Scull02ab1f52020-05-04 10:48:58 +0100574 select ARM64_WORKAROUND_SPECULATIVE_AT
575 help
576 This option adds work arounds for ARM Cortex-A57 erratum 1319537
577 and A72 erratum 1319367
578
579 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
580 speculating an AT instruction during a guest context switch.
581
582 If unsure, say Y.
583
584config ARM64_ERRATUM_1530923
585 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
586 default y
587 select ARM64_WORKAROUND_SPECULATIVE_AT
Steven Price275fa0e2019-12-16 11:56:31 +0000588 help
589 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
590
591 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
592 corrupted TLBs by speculating an AT instruction during a guest
593 context switch.
594
595 If unsure, say Y.
596
Geert Uytterhoevenebcea692020-04-16 13:56:57 +0200597config ARM64_WORKAROUND_REPEAT_TLBI
598 bool
599
Catalin Marinasce8c80c2018-11-19 11:27:28 +0000600config ARM64_ERRATUM_1286807
601 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
602 default y
603 select ARM64_WORKAROUND_REPEAT_TLBI
604 help
Will Deaconbc15cf72019-04-29 14:21:11 +0100605 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
Catalin Marinasce8c80c2018-11-19 11:27:28 +0000606
607 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
608 address for a cacheable mapping of a location is being
609 accessed by a core while another core is remapping the virtual
610 address to a new physical page using the recommended
611 break-before-make sequence, then under very rare circumstances
612 TLBI+DSB completes before a read using the translation being
613 invalidated has been observed by other observers. The
614 workaround repeats the TLBI+DSB operation.
615
Will Deacon969f5ea2019-04-29 13:03:57 +0100616config ARM64_ERRATUM_1463225
617 bool "Cortex-A76: Software Step might prevent interrupt recognition"
618 default y
619 help
620 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
621
622 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
623 of a system call instruction (SVC) can prevent recognition of
624 subsequent interrupts when software stepping is disabled in the
625 exception handler of the system call and either kernel debugging
626 is enabled or VHE is in use.
627
628 Work around the erratum by triggering a dummy step exception
629 when handling a system call from a task that is being stepped
630 in a VHE configuration of the kernel.
631
632 If unsure, say Y.
633
James Morse05460842019-10-17 18:42:58 +0100634config ARM64_ERRATUM_1542419
635 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
636 default y
637 help
638 This option adds a workaround for ARM Neoverse-N1 erratum
639 1542419.
640
641 Affected Neoverse-N1 cores could execute a stale instruction when
642 modified by another CPU. The workaround depends on a firmware
643 counterpart.
644
645 Workaround the issue by hiding the DIC feature from EL0. This
646 forces user-space to perform cache maintenance.
647
648 If unsure, say Y.
649
Rob Herring96d389ca2020-10-28 13:28:39 -0500650config ARM64_ERRATUM_1508412
651 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
652 default y
653 help
654 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
655
656 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
657 of a store-exclusive or read of PAR_EL1 and a load with device or
658 non-cacheable memory attributes. The workaround depends on a firmware
659 counterpart.
660
661 KVM guests must also have the workaround implemented or they can
662 deadlock the system.
663
664 Work around the issue by inserting DMB SY barriers around PAR_EL1
665 register reads and warning KVM users. The DMB barrier is sufficient
666 to prevent a speculative PAR_EL1 read.
667
668 If unsure, say Y.
669
Suzuki K Pouloseb9d216f2021-10-19 17:31:40 +0100670config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
671 bool
672
673config ARM64_ERRATUM_2119858
674 bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode"
675 default y
Suzuki K Pouloseb9d216f2021-10-19 17:31:40 +0100676 depends on CORESIGHT_TRBE
677 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
678 help
679 This option adds the workaround for ARM Cortex-A710 erratum 2119858.
680
681 Affected Cortex-A710 cores could overwrite up to 3 cache lines of trace
682 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
683 the event of a WRAP event.
684
685 Work around the issue by always making sure we move the TRBPTR_EL1 by
686 256 bytes before enabling the buffer and filling the first 256 bytes of
687 the buffer with ETM ignore packets upon disabling.
688
689 If unsure, say Y.
690
691config ARM64_ERRATUM_2139208
692 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
693 default y
Suzuki K Pouloseb9d216f2021-10-19 17:31:40 +0100694 depends on CORESIGHT_TRBE
695 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
696 help
697 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
698
699 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
700 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
701 the event of a WRAP event.
702
703 Work around the issue by always making sure we move the TRBPTR_EL1 by
704 256 bytes before enabling the buffer and filling the first 256 bytes of
705 the buffer with ETM ignore packets upon disabling.
706
707 If unsure, say Y.
708
Suzuki K Poulosefa82d0b2021-10-19 17:31:41 +0100709config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
710 bool
711
712config ARM64_ERRATUM_2054223
713 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
714 default y
715 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
716 help
717 Enable workaround for ARM Cortex-A710 erratum 2054223
718
719 Affected cores may fail to flush the trace data on a TSB instruction, when
720 the PE is in trace prohibited state. This will cause losing a few bytes
721 of the trace cached.
722
723 Workaround is to issue two TSB consecutively on affected cores.
724
725 If unsure, say Y.
726
727config ARM64_ERRATUM_2067961
728 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
729 default y
730 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
731 help
732 Enable workaround for ARM Neoverse-N2 erratum 2067961
733
734 Affected cores may fail to flush the trace data on a TSB instruction, when
735 the PE is in trace prohibited state. This will cause losing a few bytes
736 of the trace cached.
737
738 Workaround is to issue two TSB consecutively on affected cores.
739
740 If unsure, say Y.
741
Suzuki K Poulose8d81b2a2021-10-19 17:31:42 +0100742config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
743 bool
744
745config ARM64_ERRATUM_2253138
746 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
Suzuki K Poulose8d81b2a2021-10-19 17:31:42 +0100747 depends on CORESIGHT_TRBE
748 default y
749 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
750 help
751 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
752
753 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
754 for TRBE. Under some conditions, the TRBE might generate a write to the next
755 virtually addressed page following the last page of the TRBE address space
756 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
757
758 Work around this in the driver by always making sure that there is a
759 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
760
761 If unsure, say Y.
762
763config ARM64_ERRATUM_2224489
764 bool "Cortex-A710: 2224489: workaround TRBE writing to address out-of-range"
Suzuki K Poulose8d81b2a2021-10-19 17:31:42 +0100765 depends on CORESIGHT_TRBE
766 default y
767 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
768 help
769 This option adds the workaround for ARM Cortex-A710 erratum 2224489.
770
771 Affected Cortex-A710 cores might write to an out-of-range address, not reserved
772 for TRBE. Under some conditions, the TRBE might generate a write to the next
773 virtually addressed page following the last page of the TRBE address space
774 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
775
776 Work around this in the driver by always making sure that there is a
777 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
778
779 If unsure, say Y.
780
Robert Richter94100972015-09-21 22:58:38 +0200781config CAVIUM_ERRATUM_22375
782 bool "Cavium erratum 22375, 24313"
783 default y
784 help
Will Deaconbc15cf72019-04-29 14:21:11 +0100785 Enable workaround for errata 22375 and 24313.
Robert Richter94100972015-09-21 22:58:38 +0200786
787 This implements two gicv3-its errata workarounds for ThunderX. Both
Will Deaconbc15cf72019-04-29 14:21:11 +0100788 with a small impact affecting only ITS table allocation.
Robert Richter94100972015-09-21 22:58:38 +0200789
790 erratum 22375: only alloc 8MB table size
791 erratum 24313: ignore memory access type
792
793 The fixes are in ITS initialization and basically ignore memory access
794 type and table size provided by the TYPER and BASER registers.
795
796 If unsure, say Y.
797
Ganapatrao Kulkarnifbf8f402016-05-25 15:29:20 +0200798config CAVIUM_ERRATUM_23144
799 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
800 depends on NUMA
801 default y
802 help
803 ITS SYNC command hang for cross node io and collections/cpu mapping.
804
805 If unsure, say Y.
806
Robert Richter6d4e11c2015-09-21 22:58:35 +0200807config CAVIUM_ERRATUM_23154
808 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
809 default y
810 help
811 The gicv3 of ThunderX requires a modified version for
812 reading the IAR status to ensure data synchronization
813 (access to icc_iar1_el1 is not sync'ed before and after).
814
815 If unsure, say Y.
816
Andrew Pinski104a0c02016-02-24 17:44:57 -0800817config CAVIUM_ERRATUM_27456
818 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
819 default y
820 help
821 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
822 instructions may cause the icache to become corrupted if it
823 contains data for a non-current ASID. The fix is to
824 invalidate the icache when changing the mm context.
825
826 If unsure, say Y.
827
David Daney690a3412017-06-09 12:49:48 +0100828config CAVIUM_ERRATUM_30115
829 bool "Cavium erratum 30115: Guest may disable interrupts in host"
830 default y
831 help
832 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
833 1.2, and T83 Pass 1.0, KVM guest execution may disable
834 interrupts in host. Trapping both GICv3 group-0 and group-1
835 accesses sidesteps the issue.
836
837 If unsure, say Y.
838
Marc Zyngier603afdc2019-09-13 10:57:50 +0100839config CAVIUM_TX2_ERRATUM_219
840 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
841 default y
842 help
843 On Cavium ThunderX2, a load, store or prefetch instruction between a
844 TTBR update and the corresponding context synchronizing operation can
845 cause a spurious Data Abort to be delivered to any hardware thread in
846 the CPU core.
847
848 Work around the issue by avoiding the problematic code sequence and
849 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
850 trap handler performs the corresponding register access, skips the
851 instruction and ensures context synchronization by virtue of the
852 exception return.
853
854 If unsure, say Y.
855
Geert Uytterhoevenebcea692020-04-16 13:56:57 +0200856config FUJITSU_ERRATUM_010001
857 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
858 default y
859 help
860 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
861 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
862 accesses may cause undefined fault (Data abort, DFSC=0b111111).
863 This fault occurs under a specific hardware condition when a
864 load/store instruction performs an address translation using:
865 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
866 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
867 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
868 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
869
870 The workaround is to ensure these bits are clear in TCR_ELx.
871 The workaround only affects the Fujitsu-A64FX.
872
873 If unsure, say Y.
874
875config HISILICON_ERRATUM_161600802
876 bool "Hip07 161600802: Erroneous redistributor VLPI base"
877 default y
878 help
879 The HiSilicon Hip07 SoC uses the wrong redistributor base
880 when issued ITS commands such as VMOVP and VMAPP, and requires
881 a 128kB offset to be applied to the target address in this commands.
882
883 If unsure, say Y.
884
Christopher Covington38fd94b2017-02-08 15:08:37 -0500885config QCOM_FALKOR_ERRATUM_1003
886 bool "Falkor E1003: Incorrect translation due to ASID change"
887 default y
Christopher Covington38fd94b2017-02-08 15:08:37 -0500888 help
889 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
Will Deacond1777e62017-11-14 14:29:19 +0000890 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
891 in TTBR1_EL1, this situation only occurs in the entry trampoline and
892 then only for entries in the walk cache, since the leaf translation
893 is unchanged. Work around the erratum by invalidating the walk cache
894 entries for the trampoline before entering the kernel proper.
Christopher Covington38fd94b2017-02-08 15:08:37 -0500895
Christopher Covingtond9ff80f2017-01-31 12:50:19 -0500896config QCOM_FALKOR_ERRATUM_1009
897 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
898 default y
Catalin Marinasce8c80c2018-11-19 11:27:28 +0000899 select ARM64_WORKAROUND_REPEAT_TLBI
Christopher Covingtond9ff80f2017-01-31 12:50:19 -0500900 help
901 On Falkor v1, the CPU may prematurely complete a DSB following a
902 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
903 one more time to fix the issue.
904
905 If unsure, say Y.
906
Shanker Donthineni90922a22017-03-07 08:20:38 -0600907config QCOM_QDF2400_ERRATUM_0065
908 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
909 default y
910 help
911 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
912 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
913 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
914
915 If unsure, say Y.
916
Shanker Donthineni932b50c2017-12-11 16:42:32 -0600917config QCOM_FALKOR_ERRATUM_E1041
918 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
919 default y
920 help
921 Falkor CPU may speculatively fetch instructions from an improper
922 memory location when MMU translation is changed from SCTLR_ELn[M]=1
923 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
924
925 If unsure, say Y.
926
Rich Wiley20109a82021-03-23 17:28:09 -0700927config NVIDIA_CARMEL_CNP_ERRATUM
928 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
929 default y
930 help
931 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
932 invalidate shared TLB entries installed by a different core, as it would
933 on standard ARM cores.
934
935 If unsure, say Y.
936
Geert Uytterhoevenebcea692020-04-16 13:56:57 +0200937config SOCIONEXT_SYNQUACER_PREITS
938 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
Zhang Lei3e321312019-02-26 18:43:41 +0000939 default y
940 help
Geert Uytterhoevenebcea692020-04-16 13:56:57 +0200941 Socionext Synquacer SoCs implement a separate h/w block to generate
942 MSI doorbell writes with non-zero values for the device ID.
Zhang Lei3e321312019-02-26 18:43:41 +0000943
944 If unsure, say Y.
945
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100946endmenu
947
948
949choice
950 prompt "Page size"
951 default ARM64_4K_PAGES
952 help
953 Page size (translation granule) configuration.
954
955config ARM64_4K_PAGES
956 bool "4KB"
957 help
958 This feature enables 4KB pages support.
959
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100960config ARM64_16K_PAGES
961 bool "16KB"
962 help
963 The system will use 16KB pages support. AArch32 emulation
964 requires applications compiled with 16K (or a multiple of 16K)
965 aligned segments.
966
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100967config ARM64_64K_PAGES
968 bool "64KB"
969 help
970 This feature enables 64KB pages support (4KB by default)
971 allowing only two levels of page tables and faster TLB
Suzuki K. Poulosedb488be2015-10-19 14:19:34 +0100972 look-up. AArch32 emulation requires applications compiled
973 with 64K aligned segments.
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100974
975endchoice
976
977choice
978 prompt "Virtual address space size"
979 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100980 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100981 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
982 help
983 Allows choosing one of multiple possible virtual address
984 space sizes. The level of translation table is determined by
985 a combination of page size and virtual address space size.
986
Suzuki K. Poulose21539932015-10-19 14:19:38 +0100987config ARM64_VA_BITS_36
Catalin Marinas56a3f302015-10-20 14:59:20 +0100988 bool "36-bit" if EXPERT
Suzuki K. Poulose21539932015-10-19 14:19:38 +0100989 depends on ARM64_16K_PAGES
990
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100991config ARM64_VA_BITS_39
992 bool "39-bit"
993 depends on ARM64_4K_PAGES
994
995config ARM64_VA_BITS_42
996 bool "42-bit"
997 depends on ARM64_64K_PAGES
998
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100999config ARM64_VA_BITS_47
1000 bool "47-bit"
1001 depends on ARM64_16K_PAGES
1002
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001003config ARM64_VA_BITS_48
1004 bool "48-bit"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001005
Steve Capperb6d00d42019-08-07 16:55:22 +01001006config ARM64_VA_BITS_52
1007 bool "52-bit"
Will Deacon68d23da2018-12-10 14:15:15 +00001008 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
1009 help
1010 Enable 52-bit virtual addressing for userspace when explicitly
Steve Capperb6d00d42019-08-07 16:55:22 +01001011 requested via a hint to mmap(). The kernel will also use 52-bit
1012 virtual addresses for its own mappings (provided HW support for
1013 this feature is available, otherwise it reverts to 48-bit).
Will Deacon68d23da2018-12-10 14:15:15 +00001014
1015 NOTE: Enabling 52-bit virtual addressing in conjunction with
1016 ARMv8.3 Pointer Authentication will result in the PAC being
1017 reduced from 7 bits to 3 bits, which may have a significant
1018 impact on its susceptibility to brute-force attacks.
1019
1020 If unsure, select 48-bit virtual addressing instead.
1021
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001022endchoice
1023
Will Deacon68d23da2018-12-10 14:15:15 +00001024config ARM64_FORCE_52BIT
1025 bool "Force 52-bit virtual addresses for userspace"
Steve Capperb6d00d42019-08-07 16:55:22 +01001026 depends on ARM64_VA_BITS_52 && EXPERT
Will Deacon68d23da2018-12-10 14:15:15 +00001027 help
1028 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1029 to maintain compatibility with older software by providing 48-bit VAs
1030 unless a hint is supplied to mmap.
1031
1032 This configuration option disables the 48-bit compatibility logic, and
1033 forces all userspace addresses to be 52-bit on HW that supports it. One
1034 should only enable this configuration option for stress testing userspace
1035 memory management code. If unsure say N here.
1036
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001037config ARM64_VA_BITS
1038 int
Suzuki K. Poulose21539932015-10-19 14:19:38 +01001039 default 36 if ARM64_VA_BITS_36
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001040 default 39 if ARM64_VA_BITS_39
1041 default 42 if ARM64_VA_BITS_42
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +01001042 default 47 if ARM64_VA_BITS_47
Steve Capperb6d00d42019-08-07 16:55:22 +01001043 default 48 if ARM64_VA_BITS_48
1044 default 52 if ARM64_VA_BITS_52
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001045
Kristina Martsenko982aa7c2017-12-13 17:07:16 +00001046choice
1047 prompt "Physical address space size"
1048 default ARM64_PA_BITS_48
1049 help
1050 Choose the maximum physical address range that the kernel will
1051 support.
1052
1053config ARM64_PA_BITS_48
1054 bool "48-bit"
1055
Kristina Martsenkof77d2812017-12-13 17:07:25 +00001056config ARM64_PA_BITS_52
1057 bool "52-bit (ARMv8.2)"
1058 depends on ARM64_64K_PAGES
1059 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1060 help
1061 Enable support for a 52-bit physical address space, introduced as
1062 part of the ARMv8.2-LPA extension.
1063
1064 With this enabled, the kernel will also continue to work on CPUs that
1065 do not support ARMv8.2-LPA, but with some added memory overhead (and
1066 minor performance overhead).
1067
Kristina Martsenko982aa7c2017-12-13 17:07:16 +00001068endchoice
1069
1070config ARM64_PA_BITS
1071 int
1072 default 48 if ARM64_PA_BITS_48
Kristina Martsenkof77d2812017-12-13 17:07:25 +00001073 default 52 if ARM64_PA_BITS_52
Kristina Martsenko982aa7c2017-12-13 17:07:16 +00001074
Anders Roxelld8e85e12019-11-13 10:26:52 +01001075choice
1076 prompt "Endianness"
1077 default CPU_LITTLE_ENDIAN
1078 help
1079 Select the endianness of data accesses performed by the CPU. Userspace
1080 applications will need to be compiled and linked for the endianness
1081 that is selected here.
1082
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001083config CPU_BIG_ENDIAN
Nathan Chancellore9c6dee2021-02-08 17:57:20 -07001084 bool "Build big-endian kernel"
1085 depends on !LD_IS_LLD || LLD_VERSION >= 130000
1086 help
Anders Roxelld8e85e12019-11-13 10:26:52 +01001087 Say Y if you plan on running a kernel with a big-endian userspace.
1088
1089config CPU_LITTLE_ENDIAN
1090 bool "Build little-endian kernel"
1091 help
1092 Say Y if you plan on running a kernel with a little-endian userspace.
1093 This is usually the case for distributions targeting arm64.
1094
1095endchoice
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001096
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001097config SCHED_MC
1098 bool "Multi-core scheduler support"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001099 help
1100 Multi-core scheduler support improves the CPU scheduler's decision
1101 making when dealing with multi-core CPU chips at a cost of slightly
1102 increased overhead in some places. If unsure say N here.
1103
Barry Song778c5582021-09-24 20:51:03 +12001104config SCHED_CLUSTER
1105 bool "Cluster scheduler support"
1106 help
1107 Cluster scheduler support improves the CPU scheduler's decision
1108 making when dealing with machines that have clusters of CPUs.
1109 Cluster usually means a couple of CPUs which are placed closely
1110 by sharing mid-level caches, last-level cache tags or internal
1111 busses.
1112
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001113config SCHED_SMT
1114 bool "SMT scheduler support"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001115 help
1116 Improves the CPU scheduler's decision making when dealing with
1117 MultiThreading at a cost of slightly increased overhead in some
1118 places. If unsure say N here.
1119
1120config NR_CPUS
Ganapatrao Kulkarni62aa9652015-03-18 11:01:18 +00001121 int "Maximum number of CPUs (2-4096)"
1122 range 2 4096
Mark Rutland846a4152019-01-14 11:41:25 +00001123 default "256"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001124
1125config HOTPLUG_CPU
1126 bool "Support for hot-pluggable CPUs"
Yang Yingliang217d4532015-09-24 17:32:14 +08001127 select GENERIC_IRQ_MIGRATION
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001128 help
1129 Say Y here to experiment with turning CPUs off and on. CPUs
1130 can be controlled through /sys/devices/system/cpu.
1131
Ganapatrao Kulkarni1a2db302016-04-08 15:50:27 -07001132# Common NUMA Features
1133config NUMA
Randy Dunlap4399e6c2020-01-31 17:51:06 -08001134 bool "NUMA Memory Allocation and Scheduler Support"
Atish Patraae3c1072020-11-18 16:38:26 -08001135 select GENERIC_ARCH_NUMA
Kefeng Wang0c2a6cc2016-09-26 15:36:50 +08001136 select ACPI_NUMA if ACPI
1137 select OF_NUMA
Ganapatrao Kulkarni1a2db302016-04-08 15:50:27 -07001138 help
Randy Dunlap4399e6c2020-01-31 17:51:06 -08001139 Enable NUMA (Non-Uniform Memory Access) support.
Ganapatrao Kulkarni1a2db302016-04-08 15:50:27 -07001140
1141 The kernel will try to allocate memory used by a CPU on the
1142 local memory of the CPU and add some more
1143 NUMA awareness to the kernel.
1144
1145config NODES_SHIFT
1146 int "Maximum NUMA Nodes (as a power of 2)"
1147 range 1 10
Vanshidhar Konda2a13c132020-10-30 10:30:50 -07001148 default "4"
Mike Rapoporta9ee6cf2021-06-28 19:43:01 -07001149 depends on NUMA
Ganapatrao Kulkarni1a2db302016-04-08 15:50:27 -07001150 help
1151 Specify the maximum number of NUMA Nodes available on the target
1152 system. Increases memory reserved to accommodate various tables.
1153
1154config USE_PERCPU_NUMA_NODE_ID
1155 def_bool y
1156 depends on NUMA
1157
Zhen Lei7af3a0a2016-09-01 14:55:00 +08001158config HAVE_SETUP_PER_CPU_AREA
1159 def_bool y
1160 depends on NUMA
1161
1162config NEED_PER_CPU_EMBED_FIRST_CHUNK
1163 def_bool y
1164 depends on NUMA
1165
Kefeng Wang09cea612021-11-05 13:39:44 -07001166config NEED_PER_CPU_PAGE_FIRST_CHUNK
1167 def_bool y
1168 depends on NUMA
1169
Masahiro Yamada8636a1f2018-12-11 20:01:04 +09001170source "kernel/Kconfig.hz"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001171
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001172config ARCH_SPARSEMEM_ENABLE
1173 def_bool y
1174 select SPARSEMEM_VMEMMAP_ENABLE
Catalin Marinas782276b2021-04-20 10:35:59 +01001175 select SPARSEMEM_VMEMMAP
Nikunj Kelae7d4bac2018-07-06 10:47:24 -07001176
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001177config HW_PERF_EVENTS
Mark Rutland6475b2d2015-10-02 10:55:03 +01001178 def_bool y
1179 depends on ARM_PMU
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001180
Vladimir Murzin18107f82021-03-12 17:38:10 +00001181config ARCH_HAS_FILTER_PGPROT
1182 def_bool y
1183
Sami Tolvanen52875692020-04-27 09:00:16 -07001184# Supported by clang >= 7.0
1185config CC_HAVE_SHADOW_CALL_STACK
1186 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1187
Stefano Stabellinidfd57bc2015-11-23 10:33:49 +00001188config PARAVIRT
1189 bool "Enable paravirtualization code"
1190 help
1191 This changes the kernel so it can modify itself when it is run
1192 under a hypervisor, potentially improving performance significantly
1193 over full virtualization.
1194
1195config PARAVIRT_TIME_ACCOUNTING
1196 bool "Paravirtual steal time accounting"
1197 select PARAVIRT
Stefano Stabellinidfd57bc2015-11-23 10:33:49 +00001198 help
1199 Select this option to enable fine granularity task steal time
1200 accounting. Time spent executing other tasks in parallel with
1201 the current vCPU is discounted from the vCPU power. To account for
1202 that, there can be a small performance impact.
1203
1204 If in doubt, say N here.
1205
Geoff Levandd28f6df2016-06-23 17:54:48 +00001206config KEXEC
1207 depends on PM_SLEEP_SMP
1208 select KEXEC_CORE
1209 bool "kexec system call"
Masahiro Yamadaa7f7f622020-06-14 01:50:22 +09001210 help
Geoff Levandd28f6df2016-06-23 17:54:48 +00001211 kexec is a system call that implements the ability to shutdown your
1212 current kernel, and to start another kernel. It is like a reboot
1213 but it is independent of the system firmware. And like a reboot
1214 you can start any kernel with it, not just Linux.
1215
AKASHI Takahiro3ddd9992018-11-15 14:52:48 +09001216config KEXEC_FILE
1217 bool "kexec file based system call"
1218 select KEXEC_CORE
Lakshmi Ramasubramaniandce92f62021-02-21 09:49:30 -08001219 select HAVE_IMA_KEXEC if IMA
AKASHI Takahiro3ddd9992018-11-15 14:52:48 +09001220 help
1221 This is new version of kexec system call. This system call is
1222 file based and takes file descriptors as system call argument
1223 for kernel and initramfs as opposed to list of segments as
1224 accepted by previous system call.
1225
Jiri Bohac99d5cadf2019-08-19 17:17:44 -07001226config KEXEC_SIG
AKASHI Takahiro732b7b92018-11-15 14:52:54 +09001227 bool "Verify kernel signature during kexec_file_load() syscall"
1228 depends on KEXEC_FILE
1229 help
1230 Select this option to verify a signature with loaded kernel
1231 image. If configured, any attempt of loading a image without
1232 valid signature will fail.
1233
1234 In addition to that option, you need to enable signature
1235 verification for the corresponding kernel image type being
1236 loaded in order for this to work.
1237
1238config KEXEC_IMAGE_VERIFY_SIG
1239 bool "Enable Image signature verification support"
1240 default y
Jiri Bohac99d5cadf2019-08-19 17:17:44 -07001241 depends on KEXEC_SIG
AKASHI Takahiro732b7b92018-11-15 14:52:54 +09001242 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1243 help
1244 Enable Image signature verification support.
1245
1246comment "Support for PE file signature verification disabled"
Jiri Bohac99d5cadf2019-08-19 17:17:44 -07001247 depends on KEXEC_SIG
AKASHI Takahiro732b7b92018-11-15 14:52:54 +09001248 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1249
AKASHI Takahiroe62aaea2017-04-03 11:24:38 +09001250config CRASH_DUMP
1251 bool "Build kdump crash kernel"
1252 help
1253 Generate crash dump after being started by kexec. This should
1254 be normally only set in special crash dump kernels which are
1255 loaded in the main kernel with kexec-tools into a specially
1256 reserved region and then later executed after a crash by
1257 kdump/kexec.
1258
Mauro Carvalho Chehab330d4812019-06-13 15:21:39 -03001259 For more details see Documentation/admin-guide/kdump/kdump.rst
AKASHI Takahiroe62aaea2017-04-03 11:24:38 +09001260
Pavel Tatashin072e3d92021-01-25 14:19:08 -05001261config TRANS_TABLE
1262 def_bool y
Pasha Tatashin08eae0e2021-09-30 14:31:06 +00001263 depends on HIBERNATION || KEXEC_CORE
Pavel Tatashin072e3d92021-01-25 14:19:08 -05001264
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +00001265config XEN_DOM0
1266 def_bool y
1267 depends on XEN
1268
1269config XEN
Julien Grallc2ba1f72014-09-17 14:07:06 -07001270 bool "Xen guest support on ARM64"
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +00001271 depends on ARM64 && OF
Stefano Stabellini83862cc2013-10-10 13:40:44 +00001272 select SWIOTLB_XEN
Stefano Stabellinidfd57bc2015-11-23 10:33:49 +00001273 select PARAVIRT
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +00001274 help
1275 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1276
Steve Capperd03bb142013-04-25 15:19:21 +01001277config FORCE_MAX_ZONEORDER
1278 int
Anshuman Khandual79cc2ed2021-03-01 16:55:14 +05301279 default "14" if ARM64_64K_PAGES
1280 default "12" if ARM64_16K_PAGES
Steve Capperd03bb142013-04-25 15:19:21 +01001281 default "11"
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +01001282 help
1283 The kernel memory allocator divides physically contiguous memory
1284 blocks into "zones", where each zone is a power of two number of
1285 pages. This option selects the largest power of two that the kernel
1286 keeps in the memory allocator. If you need to allocate very large
1287 blocks of physically contiguous memory, then you may need to
1288 increase this value.
1289
1290 This config option is actually maximum order plus one. For example,
1291 a value of 11 means that the largest free memory block is 2^10 pages.
1292
1293 We make sure that we can allocate upto a HugePage size for each configuration.
1294 Hence we have :
1295 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1296
1297 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1298 4M allocations matching the default size used by generic code.
Steve Capperd03bb142013-04-25 15:19:21 +01001299
Will Deacon084eb772017-11-14 14:41:01 +00001300config UNMAP_KERNEL_AT_EL0
Will Deacon06170522017-11-14 16:19:39 +00001301 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
Will Deacon084eb772017-11-14 14:41:01 +00001302 default y
1303 help
Will Deacon06170522017-11-14 16:19:39 +00001304 Speculation attacks against some high-performance processors can
1305 be used to bypass MMU permission checks and leak kernel data to
1306 userspace. This can be defended against by unmapping the kernel
1307 when running in userspace, mapping it back in on exception entry
1308 via a trampoline page in the vector table.
Will Deacon084eb772017-11-14 14:41:01 +00001309
1310 If unsure, say Y.
1311
Ard Biesheuvelc55191e2018-11-07 11:36:20 +01001312config RODATA_FULL_DEFAULT_ENABLED
1313 bool "Apply r/o permissions of VM areas also to their linear aliases"
1314 default y
1315 help
1316 Apply read-only attributes of VM areas to the linear alias of
1317 the backing pages as well. This prevents code or read-only data
1318 from being modified (inadvertently or intentionally) via another
1319 mapping of the same memory page. This additional enhancement can
1320 be turned off at runtime by passing rodata=[off|on] (and turned on
1321 with rodata=full if this option is set to 'n')
1322
1323 This requires the linear region to be mapped down to pages,
1324 which may adversely affect performance in some cases.
1325
Will Deacondd523792019-04-23 14:37:24 +01001326config ARM64_SW_TTBR0_PAN
1327 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1328 help
1329 Enabling this option prevents the kernel from accessing
1330 user-space memory directly by pointing TTBR0_EL1 to a reserved
1331 zeroed area and reserved ASID. The user access routines
1332 restore the valid TTBR0_EL1 temporarily.
1333
Catalin Marinas63f0c602019-07-23 19:58:39 +02001334config ARM64_TAGGED_ADDR_ABI
1335 bool "Enable the tagged user addresses syscall ABI"
1336 default y
1337 help
1338 When this option is enabled, user applications can opt in to a
1339 relaxed ABI via prctl() allowing tagged addresses to be passed
1340 to system calls as pointer arguments. For details, see
Jeremy Cline799c8512019-09-17 19:52:27 +00001341 Documentation/arm64/tagged-address-abi.rst.
Catalin Marinas63f0c602019-07-23 19:58:39 +02001342
Will Deacondd523792019-04-23 14:37:24 +01001343menuconfig COMPAT
1344 bool "Kernel support for 32-bit EL0"
1345 depends on ARM64_4K_PAGES || EXPERT
Will Deacondd523792019-04-23 14:37:24 +01001346 select HAVE_UID16
1347 select OLD_SIGSUSPEND3
1348 select COMPAT_OLD_SIGACTION
1349 help
1350 This option enables support for a 32-bit EL0 running under a 64-bit
1351 kernel at EL1. AArch32-specific components such as system calls,
1352 the user helper functions, VFP support and the ptrace interface are
1353 handled appropriately by the kernel.
1354
1355 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1356 that you will only be able to execute AArch32 binaries that were compiled
1357 with page size aligned segments.
1358
1359 If you want to execute 32-bit userspace applications, say Y.
1360
1361if COMPAT
1362
1363config KUSER_HELPERS
Will Deacon7c4791c2019-10-07 13:03:12 +01001364 bool "Enable kuser helpers page for 32-bit applications"
Will Deacondd523792019-04-23 14:37:24 +01001365 default y
1366 help
1367 Warning: disabling this option may break 32-bit user programs.
1368
1369 Provide kuser helpers to compat tasks. The kernel provides
1370 helper code to userspace in read only form at a fixed location
1371 to allow userspace to be independent of the CPU type fitted to
1372 the system. This permits binaries to be run on ARMv4 through
1373 to ARMv8 without modification.
1374
Mauro Carvalho Chehabdc7a12b2019-04-14 15:51:10 -03001375 See Documentation/arm/kernel_user_helpers.rst for details.
Will Deacondd523792019-04-23 14:37:24 +01001376
1377 However, the fixed address nature of these helpers can be used
1378 by ROP (return orientated programming) authors when creating
1379 exploits.
1380
1381 If all of the binaries and libraries which run on your platform
1382 are built specifically for your platform, and make no use of
1383 these helpers, then you can turn this option off to hinder
1384 such exploits. However, in that case, if a binary or library
1385 relying on those helpers is run, it will not function correctly.
1386
1387 Say N here only if you are absolutely certain that you do not
1388 need these helpers; otherwise, the safe option is to say Y.
1389
Will Deacon7c4791c2019-10-07 13:03:12 +01001390config COMPAT_VDSO
1391 bool "Enable vDSO for 32-bit applications"
Nick Desaulniers3e6f8d12021-10-19 15:36:46 -07001392 depends on !CPU_BIG_ENDIAN
1393 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
Will Deacon7c4791c2019-10-07 13:03:12 +01001394 select GENERIC_COMPAT_VDSO
1395 default y
1396 help
1397 Place in the process address space of 32-bit applications an
1398 ELF shared object providing fast implementations of gettimeofday
1399 and clock_gettime.
1400
1401 You must have a 32-bit build of glibc 2.22 or later for programs
1402 to seamlessly take advantage of this.
Will Deacondd523792019-04-23 14:37:24 +01001403
Nick Desaulniers625412c2020-06-08 13:57:08 -07001404config THUMB2_COMPAT_VDSO
1405 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1406 depends on COMPAT_VDSO
1407 default y
1408 help
1409 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1410 otherwise with '-marm'.
1411
Will Deacon1b907f42014-11-20 16:51:10 +00001412menuconfig ARMV8_DEPRECATED
1413 bool "Emulate deprecated/obsolete ARMv8 instructions"
Dave Martin6cfa7cc2017-11-06 18:07:11 +00001414 depends on SYSCTL
Will Deacon1b907f42014-11-20 16:51:10 +00001415 help
1416 Legacy software support may require certain instructions
1417 that have been deprecated or obsoleted in the architecture.
1418
1419 Enable this config to enable selective emulation of these
1420 features.
1421
1422 If unsure, say Y
1423
1424if ARMV8_DEPRECATED
1425
1426config SWP_EMULATION
1427 bool "Emulate SWP/SWPB instructions"
1428 help
1429 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1430 they are always undefined. Say Y here to enable software
1431 emulation of these instructions for userspace using LDXR/STXR.
Mark Browndd7207842020-06-25 14:15:07 +01001432 This feature can be controlled at runtime with the abi.swp
1433 sysctl which is disabled by default.
Will Deacon1b907f42014-11-20 16:51:10 +00001434
1435 In some older versions of glibc [<=2.8] SWP is used during futex
1436 trylock() operations with the assumption that the code will not
1437 be preempted. This invalid assumption may be more likely to fail
1438 with SWP emulation enabled, leading to deadlock of the user
1439 application.
1440
1441 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1442 on an external transaction monitoring block called a global
1443 monitor to maintain update atomicity. If your system does not
1444 implement a global monitor, this option can cause programs that
1445 perform SWP operations to uncached memory to deadlock.
1446
1447 If unsure, say Y
1448
1449config CP15_BARRIER_EMULATION
1450 bool "Emulate CP15 Barrier instructions"
1451 help
1452 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1453 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1454 strongly recommended to use the ISB, DSB, and DMB
1455 instructions instead.
1456
1457 Say Y here to enable software emulation of these
1458 instructions for AArch32 userspace code. When this option is
1459 enabled, CP15 barrier usage is traced which can help
Mark Browndd7207842020-06-25 14:15:07 +01001460 identify software that needs updating. This feature can be
1461 controlled at runtime with the abi.cp15_barrier sysctl.
Will Deacon1b907f42014-11-20 16:51:10 +00001462
1463 If unsure, say Y
1464
Suzuki K. Poulose2d888f42015-01-21 12:43:11 +00001465config SETEND_EMULATION
1466 bool "Emulate SETEND instruction"
1467 help
1468 The SETEND instruction alters the data-endianness of the
1469 AArch32 EL0, and is deprecated in ARMv8.
1470
1471 Say Y here to enable software emulation of the instruction
Mark Browndd7207842020-06-25 14:15:07 +01001472 for AArch32 userspace code. This feature can be controlled
1473 at runtime with the abi.setend sysctl.
Suzuki K. Poulose2d888f42015-01-21 12:43:11 +00001474
1475 Note: All the cpus on the system must have mixed endian support at EL0
1476 for this feature to be enabled. If a new CPU - which doesn't support mixed
1477 endian - is hotplugged in after this feature has been enabled, there could
1478 be unexpected results in the applications.
1479
1480 If unsure, say Y
Will Deacon1b907f42014-11-20 16:51:10 +00001481endif
1482
Will Deacondd523792019-04-23 14:37:24 +01001483endif
Catalin Marinasba428222016-07-01 18:25:31 +01001484
Will Deacon0e4a0702015-07-27 15:54:13 +01001485menu "ARMv8.1 architectural features"
1486
1487config ARM64_HW_AFDBM
1488 bool "Support for hardware updates of the Access and Dirty page flags"
1489 default y
1490 help
1491 The ARMv8.1 architecture extensions introduce support for
1492 hardware updates of the access and dirty information in page
1493 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1494 capable processors, accesses to pages with PTE_AF cleared will
1495 set this bit instead of raising an access flag fault.
1496 Similarly, writes to read-only pages with the DBM bit set will
1497 clear the read-only bit (AP[2]) instead of raising a
1498 permission fault.
1499
1500 Kernels built with this configuration option enabled continue
1501 to work on pre-ARMv8.1 hardware and the performance impact is
1502 minimal. If unsure, say Y.
1503
1504config ARM64_PAN
1505 bool "Enable support for Privileged Access Never (PAN)"
1506 default y
1507 help
1508 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1509 prevents the kernel or hypervisor from accessing user-space (EL0)
1510 memory directly.
1511
1512 Choosing this option will cause any unprotected (not using
1513 copy_to_user et al) memory access to fail with a permission fault.
1514
1515 The feature is detected at runtime, and will remain as a 'nop'
1516 instruction if the cpu does not implement the feature.
1517
Will Deacon364a5a82020-06-30 14:02:22 +01001518config AS_HAS_LDAPR
1519 def_bool $(as-instr,.arch_extension rcpc)
1520
Catalin Marinas2decad92021-04-09 18:37:10 +01001521config AS_HAS_LSE_ATOMICS
1522 def_bool $(as-instr,.arch_extension lse)
1523
Will Deacon0e4a0702015-07-27 15:54:13 +01001524config ARM64_LSE_ATOMICS
Catalin Marinas395af862020-01-15 11:30:08 +00001525 bool
1526 default ARM64_USE_LSE_ATOMICS
Catalin Marinas2decad92021-04-09 18:37:10 +01001527 depends on AS_HAS_LSE_ATOMICS
Catalin Marinas395af862020-01-15 11:30:08 +00001528
1529config ARM64_USE_LSE_ATOMICS
Will Deacon0e4a0702015-07-27 15:54:13 +01001530 bool "Atomic instructions"
Will Deaconb32baf92019-08-29 11:52:47 +01001531 depends on JUMP_LABEL
Will Deacon7bd99b42018-05-21 19:14:22 +01001532 default y
Will Deacon0e4a0702015-07-27 15:54:13 +01001533 help
1534 As part of the Large System Extensions, ARMv8.1 introduces new
1535 atomic instructions that are designed specifically to scale in
1536 very large systems.
1537
1538 Say Y here to make use of these instructions for the in-kernel
1539 atomic routines. This incurs a small overhead on CPUs that do
1540 not support these instructions and requires the kernel to be
Will Deacon7bd99b42018-05-21 19:14:22 +01001541 built with binutils >= 2.25 in order for the new instructions
1542 to be used.
Will Deacon0e4a0702015-07-27 15:54:13 +01001543
1544endmenu
1545
Will Deaconf9933182016-02-26 16:30:14 +00001546menu "ARMv8.2 architectural features"
1547
Robin Murphyd50e0712017-07-25 11:55:42 +01001548config ARM64_PMEM
1549 bool "Enable support for persistent memory"
1550 select ARCH_HAS_PMEM_API
Robin Murphy5d7bdeb2017-07-25 11:55:43 +01001551 select ARCH_HAS_UACCESS_FLUSHCACHE
Robin Murphyd50e0712017-07-25 11:55:42 +01001552 help
1553 Say Y to enable support for the persistent memory API based on the
1554 ARMv8.2 DCPoP feature.
1555
1556 The feature is detected at runtime, and the kernel will use DC CVAC
1557 operations if DC CVAP is not supported (following the behaviour of
1558 DC CVAP itself if the system does not define a point of persistence).
1559
Xie XiuQi64c02722018-01-15 19:38:56 +00001560config ARM64_RAS_EXTN
1561 bool "Enable support for RAS CPU Extensions"
1562 default y
1563 help
1564 CPUs that support the Reliability, Availability and Serviceability
1565 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1566 errors, classify them and report them to software.
1567
1568 On CPUs with these extensions system software can use additional
1569 barriers to determine if faults are pending and read the
1570 classification from a new set of registers.
1571
1572 Selecting this feature will allow the kernel to use these barriers
1573 and access the new registers if the system supports the extension.
1574 Platform RAS features may additionally depend on firmware support.
1575
Vladimir Murzin5ffdfae2018-07-31 14:08:56 +01001576config ARM64_CNP
1577 bool "Enable support for Common Not Private (CNP) translations"
1578 default y
1579 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1580 help
1581 Common Not Private (CNP) allows translation table entries to
1582 be shared between different PEs in the same inner shareable
1583 domain, so the hardware can use this fact to optimise the
1584 caching of such entries in the TLB.
1585
1586 Selecting this option allows the CNP feature to be detected
1587 at runtime, and does not affect PEs that do not implement
1588 this feature.
1589
Will Deaconf9933182016-02-26 16:30:14 +00001590endmenu
1591
Mark Rutland04ca3202018-12-07 18:39:30 +00001592menu "ARMv8.3 architectural features"
1593
1594config ARM64_PTR_AUTH
1595 bool "Enable support for pointer authentication"
1596 default y
1597 help
1598 Pointer authentication (part of the ARMv8.3 Extensions) provides
1599 instructions for signing and authenticating pointers against secret
1600 keys, which can be used to mitigate Return Oriented Programming (ROP)
1601 and other attacks.
1602
1603 This option enables these instructions at EL0 (i.e. for userspace).
Mark Rutland04ca3202018-12-07 18:39:30 +00001604 Choosing this option will cause the kernel to initialise secret keys
1605 for each process at exec() time, with these keys being
1606 context-switched along with the process.
1607
1608 The feature is detected at runtime. If the feature is not present in
Mark Rutland384b40c2019-04-23 10:12:35 +05301609 hardware it will not be advertised to userspace/KVM guest nor will it
Marc Zyngierdfb05892020-06-11 12:18:58 +01001610 be enabled.
Mark Rutland04ca3202018-12-07 18:39:30 +00001611
Kristina Martsenko69829342020-03-13 14:34:55 +05301612 If the feature is present on the boot CPU but not on a late CPU, then
1613 the late CPU will be parked. Also, if the boot CPU does not have
1614 address auth and the late CPU has then the late CPU will still boot
1615 but with the feature disabled. On such a system, this option should
1616 not be selected.
1617
Daniel Kissb27a9f42021-06-13 11:26:31 +02001618config ARM64_PTR_AUTH_KERNEL
Daniel Kissd053e712021-06-13 11:26:32 +02001619 bool "Use pointer authentication for kernel"
Daniel Kissb27a9f42021-06-13 11:26:31 +02001620 default y
1621 depends on ARM64_PTR_AUTH
1622 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1623 # Modern compilers insert a .note.gnu.property section note for PAC
1624 # which is only understood by binutils starting with version 2.33.1.
1625 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1626 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1627 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1628 help
1629 If the compiler supports the -mbranch-protection or
1630 -msign-return-address flag (e.g. GCC 7 or later), then this option
1631 will cause the kernel itself to be compiled with return address
1632 protection. In this case, and if the target hardware is known to
1633 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1634 disabled with minimal loss of protection.
1635
Kristina Martsenko74afda42020-03-13 14:35:03 +05301636 This feature works with FUNCTION_GRAPH_TRACER option only if
1637 DYNAMIC_FTRACE_WITH_REGS is enabled.
1638
1639config CC_HAS_BRANCH_PROT_PAC_RET
1640 # GCC 9 or later, clang 8 or later
1641 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1642
1643config CC_HAS_SIGN_RETURN_ADDRESS
1644 # GCC 7, 8
1645 def_bool $(cc-option,-msign-return-address=all)
1646
1647config AS_HAS_PAC
Masahiro Yamada4d0831e2020-06-14 23:43:41 +09001648 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
Kristina Martsenko74afda42020-03-13 14:35:03 +05301649
Nick Desaulniers3b446c72020-03-19 11:19:51 -07001650config AS_HAS_CFI_NEGATE_RA_STATE
1651 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1652
Mark Rutland04ca3202018-12-07 18:39:30 +00001653endmenu
1654
Ionela Voinescu2c9d45b2020-03-05 09:06:21 +00001655menu "ARMv8.4 architectural features"
1656
1657config ARM64_AMU_EXTN
1658 bool "Enable support for the Activity Monitors Unit CPU extension"
1659 default y
1660 help
1661 The activity monitors extension is an optional extension introduced
1662 by the ARMv8.4 CPU architecture. This enables support for version 1
1663 of the activity monitors architecture, AMUv1.
1664
1665 To enable the use of this extension on CPUs that implement it, say Y.
1666
1667 Note that for architectural reasons, firmware _must_ implement AMU
1668 support when running on CPUs that present the activity monitors
1669 extension. The required support is present in:
1670 * Version 1.5 and later of the ARM Trusted Firmware
1671
1672 For kernels that have this configuration enabled but boot with broken
1673 firmware, you may need to say N here until the firmware is fixed.
1674 Otherwise you may experience firmware panics or lockups when
1675 accessing the counter registers. Even if you are not observing these
1676 symptoms, the values returned by the register reads might not
1677 correctly reflect reality. Most commonly, the value read will be 0,
1678 indicating that the counter is not enabled.
1679
Zhenyu Ye7c78f672020-07-15 15:19:44 +08001680config AS_HAS_ARMV8_4
1681 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1682
1683config ARM64_TLB_RANGE
1684 bool "Enable support for tlbi range feature"
1685 default y
1686 depends on AS_HAS_ARMV8_4
1687 help
1688 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1689 range of input addresses.
1690
1691 The feature introduces new assembly instructions, and they were
1692 support when binutils >= 2.30.
1693
Ard Biesheuvelfd045f62015-11-24 12:37:35 +01001694endmenu
1695
Mark Brown3e6c69a2019-12-09 18:12:14 +00001696menu "ARMv8.5 architectural features"
1697
Vincenzo Frascinof469c032020-12-22 12:01:24 -08001698config AS_HAS_ARMV8_5
1699 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1700
Dave Martin383499f2020-03-16 16:50:55 +00001701config ARM64_BTI
1702 bool "Branch Target Identification support"
1703 default y
1704 help
1705 Branch Target Identification (part of the ARMv8.5 Extensions)
1706 provides a mechanism to limit the set of locations to which computed
1707 branch instructions such as BR or BLR can jump.
1708
1709 To make use of BTI on CPUs that support it, say Y.
1710
1711 BTI is intended to provide complementary protection to other control
1712 flow integrity protection mechanisms, such as the Pointer
1713 authentication mechanism provided as part of the ARMv8.3 Extensions.
1714 For this reason, it does not make sense to enable this option without
1715 also enabling support for pointer authentication. Thus, when
1716 enabling this option you should also select ARM64_PTR_AUTH=y.
1717
1718 Userspace binaries must also be specifically compiled to make use of
1719 this mechanism. If you say N here or the hardware does not support
1720 BTI, such binaries can still run, but you get no additional
1721 enforcement of branch destinations.
1722
Mark Brown97fed772020-05-06 20:51:34 +01001723config ARM64_BTI_KERNEL
1724 bool "Use Branch Target Identification for kernel"
1725 default y
1726 depends on ARM64_BTI
Daniel Kissb27a9f42021-06-13 11:26:31 +02001727 depends on ARM64_PTR_AUTH_KERNEL
Mark Brown97fed772020-05-06 20:51:34 +01001728 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
Will Deacon3a88d7c2020-05-12 12:45:40 +01001729 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1730 depends on !CC_IS_GCC || GCC_VERSION >= 100100
Nathan Chancellor8cdd23c2021-07-12 14:46:37 -07001731 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1732 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
Mark Brown97fed772020-05-06 20:51:34 +01001733 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1734 help
1735 Build the kernel with Branch Target Identification annotations
1736 and enable enforcement of this for kernel code. When this option
1737 is enabled and the system supports BTI all kernel code including
1738 modular code must have BTI enabled.
1739
1740config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1741 # GCC 9 or later, clang 8 or later
1742 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1743
Mark Brown3e6c69a2019-12-09 18:12:14 +00001744config ARM64_E0PD
1745 bool "Enable support for E0PD"
1746 default y
1747 help
Will Deacone717d932020-01-22 11:23:54 +00001748 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1749 that EL0 accesses made via TTBR1 always fault in constant time,
1750 providing similar benefits to KASLR as those provided by KPTI, but
1751 with lower overhead and without disrupting legitimate access to
1752 kernel memory such as SPE.
Mark Brown3e6c69a2019-12-09 18:12:14 +00001753
Will Deacone717d932020-01-22 11:23:54 +00001754 This option enables E0PD for TTBR1 where available.
Mark Brown3e6c69a2019-12-09 18:12:14 +00001755
Richard Henderson1a50ec02020-01-21 12:58:52 +00001756config ARCH_RANDOM
1757 bool "Enable support for random number generation"
1758 default y
1759 help
1760 Random number generation (part of the ARMv8.5 Extensions)
1761 provides a high bandwidth, cryptographically secure
1762 hardware random number generator.
1763
Vincenzo Frascino89b94df2019-09-06 11:08:29 +01001764config ARM64_AS_HAS_MTE
1765 # Initial support for MTE went in binutils 2.32.0, checked with
1766 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1767 # as a late addition to the final architecture spec (LDGM/STGM)
1768 # is only supported in the newer 2.32.x and 2.33 binutils
1769 # versions, hence the extra "stgm" instruction check below.
1770 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1771
1772config ARM64_MTE
1773 bool "Memory Tagging Extension support"
1774 default y
1775 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
Vincenzo Frascinof469c032020-12-22 12:01:24 -08001776 depends on AS_HAS_ARMV8_5
Catalin Marinas2decad92021-04-09 18:37:10 +01001777 depends on AS_HAS_LSE_ATOMICS
Vincenzo Frascino98c970d2020-12-22 12:01:35 -08001778 # Required for tag checking in the uaccess routines
1779 depends on ARM64_PAN
Vincenzo Frascino89b94df2019-09-06 11:08:29 +01001780 select ARCH_USES_HIGH_VMA_FLAGS
1781 help
1782 Memory Tagging (part of the ARMv8.5 Extensions) provides
1783 architectural support for run-time, always-on detection of
1784 various classes of memory error to aid with software debugging
1785 to eliminate vulnerabilities arising from memory-unsafe
1786 languages.
1787
1788 This option enables the support for the Memory Tagging
1789 Extension at EL0 (i.e. for userspace).
1790
1791 Selecting this option allows the feature to be detected at
1792 runtime. Any secondary CPU not implementing this feature will
1793 not be allowed a late bring-up.
1794
1795 Userspace binaries that want to use this feature must
1796 explicitly opt in. The mechanism for the userspace is
1797 described in:
1798
1799 Documentation/arm64/memory-tagging-extension.rst.
1800
Mark Brown3e6c69a2019-12-09 18:12:14 +00001801endmenu
1802
Vladimir Murzin18107f82021-03-12 17:38:10 +00001803menu "ARMv8.7 architectural features"
1804
1805config ARM64_EPAN
1806 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
1807 default y
1808 depends on ARM64_PAN
1809 help
1810 Enhanced Privileged Access Never (EPAN) allows Privileged
1811 Access Never to be used with Execute-only mappings.
1812
1813 The feature is detected at runtime, and will remain disabled
1814 if the cpu does not implement the feature.
1815endmenu
1816
Dave Martinddd25ad2017-10-31 15:51:02 +00001817config ARM64_SVE
1818 bool "ARM Scalable Vector Extension support"
1819 default y
1820 help
1821 The Scalable Vector Extension (SVE) is an extension to the AArch64
1822 execution state which complements and extends the SIMD functionality
1823 of the base architecture to support much larger vectors and to enable
1824 additional vectorisation opportunities.
1825
1826 To enable use of this extension on CPUs that implement it, say Y.
1827
Dave Martin06a916f2019-04-18 18:41:38 +01001828 On CPUs that support the SVE2 extensions, this option will enable
1829 those too.
1830
Dave Martin50436942018-03-23 18:08:31 +00001831 Note that for architectural reasons, firmware _must_ implement SVE
1832 support when running on SVE capable hardware. The required support
1833 is present in:
1834
1835 * version 1.5 and later of the ARM Trusted Firmware
1836 * the AArch64 boot wrapper since commit 5e1261e08abf
1837 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1838
1839 For other firmware implementations, consult the firmware documentation
1840 or vendor.
1841
1842 If you need the kernel to boot on SVE-capable hardware with broken
1843 firmware, you may need to say N here until you get your firmware
1844 fixed. Otherwise, you may experience firmware panics or lockups when
1845 booting the kernel. If unsure and you are not observing these
1846 symptoms, you should assume that it is safe to say Y.
Ard Biesheuvelfd045f62015-11-24 12:37:35 +01001847
1848config ARM64_MODULE_PLTS
Florian Fainelli58557e42019-06-17 15:29:59 -07001849 bool "Use PLTs to allow module memory to spill over into vmalloc area"
Catalin Marinasfaaa73b2019-06-25 09:32:11 +01001850 depends on MODULES
Ard Biesheuvelfd045f62015-11-24 12:37:35 +01001851 select HAVE_MOD_ARCH_SPECIFIC
Florian Fainelli58557e42019-06-17 15:29:59 -07001852 help
1853 Allocate PLTs when loading modules so that jumps and calls whose
1854 targets are too far away for their relative offsets to be encoded
1855 in the instructions themselves can be bounced via veneers in the
1856 module's PLT. This allows modules to be allocated in the generic
1857 vmalloc area after the dedicated module memory area has been
1858 exhausted.
1859
1860 When running with address space randomization (KASLR), the module
1861 region itself may be too far away for ordinary relative jumps and
1862 calls, and so in that case, module PLTs are required and cannot be
1863 disabled.
1864
1865 Specific errata workaround(s) might also force module PLTs to be
1866 enabled (ARM64_ERRATUM_843419).
Ard Biesheuvelfd045f62015-11-24 12:37:35 +01001867
Julien Thierrybc3c03c2019-01-31 14:59:03 +00001868config ARM64_PSEUDO_NMI
1869 bool "Support for NMI-like interrupts"
Joe Perches3c9c1dc2019-12-31 01:54:57 -08001870 select ARM_GIC_V3
Julien Thierrybc3c03c2019-01-31 14:59:03 +00001871 help
1872 Adds support for mimicking Non-Maskable Interrupts through the use of
1873 GIC interrupt priority. This support requires version 3 or later of
Will Deaconbc15cf72019-04-29 14:21:11 +01001874 ARM GIC.
Julien Thierrybc3c03c2019-01-31 14:59:03 +00001875
1876 This high priority configuration for interrupts needs to be
1877 explicitly enabled by setting the kernel parameter
1878 "irqchip.gicv3_pseudo_nmi" to 1.
1879
1880 If unsure, say N
1881
Julien Thierry48ce8f82019-06-11 10:38:11 +01001882if ARM64_PSEUDO_NMI
1883config ARM64_DEBUG_PRIORITY_MASKING
1884 bool "Debug interrupt priority masking"
1885 help
1886 This adds runtime checks to functions enabling/disabling
1887 interrupts when using priority masking. The additional checks verify
1888 the validity of ICC_PMR_EL1 when calling concerned functions.
1889
1890 If unsure, say N
1891endif
1892
Ard Biesheuvel1e48ef72016-01-26 09:13:44 +01001893config RELOCATABLE
Ard Biesheuveldd4bc602020-06-11 14:43:30 +02001894 bool "Build a relocatable kernel image" if EXPERT
Peter Collingbourne5cf896fb62019-07-31 18:18:42 -07001895 select ARCH_HAS_RELR
Ard Biesheuveldd4bc602020-06-11 14:43:30 +02001896 default y
Ard Biesheuvel1e48ef72016-01-26 09:13:44 +01001897 help
1898 This builds the kernel as a Position Independent Executable (PIE),
1899 which retains all relocation metadata required to relocate the
1900 kernel binary at runtime to a different virtual address than the
1901 address it was linked at.
1902 Since AArch64 uses the RELA relocation format, this requires a
1903 relocation pass at runtime even if the kernel is loaded at the
1904 same address it was linked at.
1905
Ard Biesheuvelf80fb3a2016-01-26 14:12:01 +01001906config RANDOMIZE_BASE
1907 bool "Randomize the address of the kernel image"
Catalin Marinasb9c220b2016-07-26 10:16:55 -07001908 select ARM64_MODULE_PLTS if MODULES
Ard Biesheuvelf80fb3a2016-01-26 14:12:01 +01001909 select RELOCATABLE
1910 help
1911 Randomizes the virtual address at which the kernel image is
1912 loaded, as a security feature that deters exploit attempts
1913 relying on knowledge of the location of kernel internals.
1914
1915 It is the bootloader's job to provide entropy, by passing a
1916 random u64 value in /chosen/kaslr-seed at kernel entry.
1917
Ard Biesheuvel2b5fe072016-01-26 14:48:29 +01001918 When booting via the UEFI stub, it will invoke the firmware's
1919 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1920 to the kernel proper. In addition, it will randomise the physical
1921 location of the kernel Image as well.
1922
Ard Biesheuvelf80fb3a2016-01-26 14:12:01 +01001923 If unsure, say N.
1924
1925config RANDOMIZE_MODULE_REGION_FULL
Barry Songf9c4ff22021-07-31 00:51:31 +12001926 bool "Randomize the module region over a 2 GB range"
Ard Biesheuvele71a4e1b2017-06-06 17:00:22 +00001927 depends on RANDOMIZE_BASE
Ard Biesheuvelf80fb3a2016-01-26 14:12:01 +01001928 default y
1929 help
Barry Songf9c4ff22021-07-31 00:51:31 +12001930 Randomizes the location of the module region inside a 2 GB window
Ard Biesheuvelf2b9ba82018-03-06 17:15:32 +00001931 covering the core kernel. This way, it is less likely for modules
Ard Biesheuvelf80fb3a2016-01-26 14:12:01 +01001932 to leak information about the location of core kernel data structures
1933 but it does imply that function calls between modules and the core
1934 kernel will need to be resolved via veneers in the module PLT.
1935
1936 When this option is not set, the module region will be randomized over
1937 a limited range that contains the [_stext, _etext] interval of the
Barry Songf9c4ff22021-07-31 00:51:31 +12001938 core kernel, so branch relocations are almost always in range unless
1939 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
1940 particular case of region exhaustion, modules might be able to fall
1941 back to a larger 2GB area.
Ard Biesheuvelf80fb3a2016-01-26 14:12:01 +01001942
Ard Biesheuvel0a1213f2018-12-12 13:08:44 +01001943config CC_HAVE_STACKPROTECTOR_SYSREG
1944 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1945
1946config STACKPROTECTOR_PER_TASK
1947 def_bool y
1948 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1949
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001950endmenu
1951
1952menu "Boot options"
1953
Lorenzo Pieralisi5e89c552016-01-26 11:10:38 +00001954config ARM64_ACPI_PARKING_PROTOCOL
1955 bool "Enable support for the ARM64 ACPI parking protocol"
1956 depends on ACPI
1957 help
1958 Enable support for the ARM64 ACPI parking protocol. If disabled
1959 the kernel will not allow booting through the ARM64 ACPI parking
1960 protocol even if the corresponding data is present in the ACPI
1961 MADT table.
1962
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001963config CMDLINE
1964 string "Default kernel command string"
1965 default ""
1966 help
1967 Provide a set of default command-line options at build time by
1968 entering them here. As a minimum, you should specify the the
1969 root device (e.g. root=/dev/nfs).
1970
Tyler Hicks1e40d102020-09-21 14:15:57 -05001971choice
1972 prompt "Kernel command line type" if CMDLINE != ""
1973 default CMDLINE_FROM_BOOTLOADER
1974 help
1975 Choose how the kernel will handle the provided default kernel
1976 command line string.
1977
1978config CMDLINE_FROM_BOOTLOADER
1979 bool "Use bootloader kernel arguments if available"
1980 help
1981 Uses the command-line options passed by the boot loader. If
1982 the boot loader doesn't provide any, the default kernel command
1983 string provided in CMDLINE will be used.
1984
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001985config CMDLINE_FORCE
1986 bool "Always use the default kernel command string"
1987 help
1988 Always use the default kernel command string, even if the boot
1989 loader passes other arguments to the kernel.
1990 This is useful if you cannot or don't want to change the
1991 command-line options your boot loader passes to the kernel.
1992
Tyler Hicks1e40d102020-09-21 14:15:57 -05001993endchoice
1994
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +02001995config EFI_STUB
1996 bool
1997
Mark Salterf84d0272014-04-15 21:59:30 -04001998config EFI
1999 bool "UEFI runtime support"
2000 depends on OF && !CPU_BIG_ENDIAN
Dave Martinb472db62017-10-31 15:50:57 +00002001 depends on KERNEL_MODE_NEON
Arnd Bergmann2c870e62018-07-24 11:48:45 +02002002 select ARCH_SUPPORTS_ACPI
Mark Salterf84d0272014-04-15 21:59:30 -04002003 select LIBFDT
2004 select UCS2_STRING
2005 select EFI_PARAMS_FROM_FDT
Ard Biesheuvele15dd492014-07-04 19:41:53 +02002006 select EFI_RUNTIME_WRAPPERS
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +02002007 select EFI_STUB
Atish Patra2e0eb482020-04-15 12:54:18 -07002008 select EFI_GENERIC_STUB
Chester Lin8d39cee2020-10-30 14:08:40 +08002009 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
Mark Salterf84d0272014-04-15 21:59:30 -04002010 default y
2011 help
2012 This option provides support for runtime services provided
2013 by UEFI firmware (such as non-volatile variables, realtime
Mark Salter3c7f2552014-04-15 22:47:52 -04002014 clock, and platform reset). A UEFI stub is also provided to
2015 allow the kernel to be booted as an EFI application. This
2016 is only useful on systems that have UEFI firmware.
Mark Salterf84d0272014-04-15 21:59:30 -04002017
Yi Lid1ae8c02014-10-04 23:46:43 +08002018config DMI
2019 bool "Enable support for SMBIOS (DMI) tables"
2020 depends on EFI
2021 default y
2022 help
2023 This enables SMBIOS/DMI feature for systems.
2024
2025 This option is only useful on systems that have UEFI firmware.
2026 However, even with this option, the resultant kernel should
2027 continue to boot on existing non-UEFI platforms.
2028
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01002029endmenu
2030
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01002031config SYSVIPC_COMPAT
2032 def_bool y
2033 depends on COMPAT && SYSVIPC
2034
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +00002035menu "Power management options"
2036
2037source "kernel/power/Kconfig"
2038
James Morse82869ac2016-04-27 17:47:12 +01002039config ARCH_HIBERNATION_POSSIBLE
2040 def_bool y
2041 depends on CPU_PM
2042
2043config ARCH_HIBERNATION_HEADER
2044 def_bool y
2045 depends on HIBERNATION
2046
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +00002047config ARCH_SUSPEND_POSSIBLE
2048 def_bool y
2049
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +00002050endmenu
2051
Lorenzo Pieralisi13072202013-07-17 14:54:21 +01002052menu "CPU Power Management"
2053
2054source "drivers/cpuidle/Kconfig"
2055
Rob Herring52e7e812014-02-24 11:27:57 +09002056source "drivers/cpufreq/Kconfig"
2057
2058endmenu
2059
Graeme Gregoryb6a02172015-03-24 14:02:53 +00002060source "drivers/acpi/Kconfig"
2061
Marc Zyngierc3eb5b12013-07-04 13:34:32 +01002062source "arch/arm64/kvm/Kconfig"
2063
Ard Biesheuvel2c988332014-03-06 16:23:33 +08002064if CRYPTO
2065source "arch/arm64/crypto/Kconfig"
2066endif