blob: 237cc706b0fb4a9ef3ba66c48ae1eaeb21360beb [file] [log] [blame]
Jason Robertsce082592010-05-13 15:57:33 +01001/*
2 * NAND Flash Controller Device Driver
3 * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19
Masahiro Yamadaa81b4702014-08-29 20:00:51 +090020#ifndef __DENALI_H__
21#define __DENALI_H__
22
Masahiro Yamada24715c72017-03-30 15:45:52 +090023#include <linux/bitops.h>
Dong, Chuanxiao6ea9ad22010-07-22 01:32:26 +080024#include <linux/mtd/nand.h>
Jason Robertsce082592010-05-13 15:57:33 +010025
26#define DEVICE_RESET 0x0
Masahiro Yamadadf8b9702017-06-06 08:21:41 +090027#define DEVICE_RESET__BANK(bank) BIT(bank)
Jason Robertsce082592010-05-13 15:57:33 +010028
29#define TRANSFER_SPARE_REG 0x10
Masahiro Yamadadf8b9702017-06-06 08:21:41 +090030#define TRANSFER_SPARE_REG__FLAG BIT(0)
Jason Robertsce082592010-05-13 15:57:33 +010031
32#define LOAD_WAIT_CNT 0x20
Masahiro Yamadadf8b9702017-06-06 08:21:41 +090033#define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
Jason Robertsce082592010-05-13 15:57:33 +010034
35#define PROGRAM_WAIT_CNT 0x30
Masahiro Yamadadf8b9702017-06-06 08:21:41 +090036#define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
Jason Robertsce082592010-05-13 15:57:33 +010037
38#define ERASE_WAIT_CNT 0x40
Masahiro Yamadadf8b9702017-06-06 08:21:41 +090039#define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
Jason Robertsce082592010-05-13 15:57:33 +010040
41#define INT_MON_CYCCNT 0x50
Masahiro Yamadadf8b9702017-06-06 08:21:41 +090042#define INT_MON_CYCCNT__VALUE GENMASK(15, 0)
Jason Robertsce082592010-05-13 15:57:33 +010043
44#define RB_PIN_ENABLED 0x60
Masahiro Yamadadf8b9702017-06-06 08:21:41 +090045#define RB_PIN_ENABLED__BANK(bank) BIT(bank)
Jason Robertsce082592010-05-13 15:57:33 +010046
47#define MULTIPLANE_OPERATION 0x70
Masahiro Yamadadf8b9702017-06-06 08:21:41 +090048#define MULTIPLANE_OPERATION__FLAG BIT(0)
Jason Robertsce082592010-05-13 15:57:33 +010049
50#define MULTIPLANE_READ_ENABLE 0x80
Masahiro Yamadadf8b9702017-06-06 08:21:41 +090051#define MULTIPLANE_READ_ENABLE__FLAG BIT(0)
Jason Robertsce082592010-05-13 15:57:33 +010052
53#define COPYBACK_DISABLE 0x90
Masahiro Yamadadf8b9702017-06-06 08:21:41 +090054#define COPYBACK_DISABLE__FLAG BIT(0)
Jason Robertsce082592010-05-13 15:57:33 +010055
56#define CACHE_WRITE_ENABLE 0xa0
Masahiro Yamadadf8b9702017-06-06 08:21:41 +090057#define CACHE_WRITE_ENABLE__FLAG BIT(0)
Jason Robertsce082592010-05-13 15:57:33 +010058
59#define CACHE_READ_ENABLE 0xb0
Masahiro Yamadadf8b9702017-06-06 08:21:41 +090060#define CACHE_READ_ENABLE__FLAG BIT(0)
Jason Robertsce082592010-05-13 15:57:33 +010061
62#define PREFETCH_MODE 0xc0
Masahiro Yamadadf8b9702017-06-06 08:21:41 +090063#define PREFETCH_MODE__PREFETCH_EN BIT(0)
64#define PREFETCH_MODE__PREFETCH_BURST_LENGTH GENMASK(15, 4)
Jason Robertsce082592010-05-13 15:57:33 +010065
66#define CHIP_ENABLE_DONT_CARE 0xd0
Masahiro Yamadadf8b9702017-06-06 08:21:41 +090067#define CHIP_EN_DONT_CARE__FLAG BIT(0)
Jason Robertsce082592010-05-13 15:57:33 +010068
69#define ECC_ENABLE 0xe0
Masahiro Yamadadf8b9702017-06-06 08:21:41 +090070#define ECC_ENABLE__FLAG BIT(0)
Jason Robertsce082592010-05-13 15:57:33 +010071
72#define GLOBAL_INT_ENABLE 0xf0
Masahiro Yamadadf8b9702017-06-06 08:21:41 +090073#define GLOBAL_INT_EN_FLAG BIT(0)
Jason Robertsce082592010-05-13 15:57:33 +010074
Masahiro Yamada1bb88662017-06-13 22:45:37 +090075#define TWHR2_AND_WE_2_RE 0x100
76#define TWHR2_AND_WE_2_RE__WE_2_RE GENMASK(5, 0)
77#define TWHR2_AND_WE_2_RE__TWHR2 GENMASK(13, 8)
Jason Robertsce082592010-05-13 15:57:33 +010078
Masahiro Yamada1bb88662017-06-13 22:45:37 +090079#define TCWAW_AND_ADDR_2_DATA 0x110
80/* The width of ADDR_2_DATA is 6 bit for old IP, 7 bit for new IP */
81#define TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA GENMASK(6, 0)
82#define TCWAW_AND_ADDR_2_DATA__TCWAW GENMASK(13, 8)
Jason Robertsce082592010-05-13 15:57:33 +010083
84#define RE_2_WE 0x120
Masahiro Yamadadf8b9702017-06-06 08:21:41 +090085#define RE_2_WE__VALUE GENMASK(5, 0)
Jason Robertsce082592010-05-13 15:57:33 +010086
Dong, Chuanxiao6ea9ad22010-07-22 01:32:26 +080087#define ACC_CLKS 0x130
Masahiro Yamadadf8b9702017-06-06 08:21:41 +090088#define ACC_CLKS__VALUE GENMASK(3, 0)
Jason Robertsce082592010-05-13 15:57:33 +010089
90#define NUMBER_OF_PLANES 0x140
Masahiro Yamadadf8b9702017-06-06 08:21:41 +090091#define NUMBER_OF_PLANES__VALUE GENMASK(2, 0)
Jason Robertsce082592010-05-13 15:57:33 +010092
93#define PAGES_PER_BLOCK 0x150
Masahiro Yamadadf8b9702017-06-06 08:21:41 +090094#define PAGES_PER_BLOCK__VALUE GENMASK(15, 0)
Jason Robertsce082592010-05-13 15:57:33 +010095
96#define DEVICE_WIDTH 0x160
Masahiro Yamadadf8b9702017-06-06 08:21:41 +090097#define DEVICE_WIDTH__VALUE GENMASK(1, 0)
Jason Robertsce082592010-05-13 15:57:33 +010098
99#define DEVICE_MAIN_AREA_SIZE 0x170
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900100#define DEVICE_MAIN_AREA_SIZE__VALUE GENMASK(15, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100101
102#define DEVICE_SPARE_AREA_SIZE 0x180
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900103#define DEVICE_SPARE_AREA_SIZE__VALUE GENMASK(15, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100104
105#define TWO_ROW_ADDR_CYCLES 0x190
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900106#define TWO_ROW_ADDR_CYCLES__FLAG BIT(0)
Jason Robertsce082592010-05-13 15:57:33 +0100107
108#define MULTIPLANE_ADDR_RESTRICT 0x1a0
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900109#define MULTIPLANE_ADDR_RESTRICT__FLAG BIT(0)
Jason Robertsce082592010-05-13 15:57:33 +0100110
111#define ECC_CORRECTION 0x1b0
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900112#define ECC_CORRECTION__VALUE GENMASK(4, 0)
Masahiro Yamada57a4d8b2017-06-13 22:45:46 +0900113#define ECC_CORRECTION__ERASE_THRESHOLD GENMASK(31, 16)
114#define MAKE_ECC_CORRECTION(val, thresh) \
115 (((val) & (ECC_CORRECTION__VALUE)) | \
116 (((thresh) << 16) & (ECC_CORRECTION__ERASE_THRESHOLD)))
Jason Robertsce082592010-05-13 15:57:33 +0100117
118#define READ_MODE 0x1c0
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900119#define READ_MODE__VALUE GENMASK(3, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100120
121#define WRITE_MODE 0x1d0
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900122#define WRITE_MODE__VALUE GENMASK(3, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100123
124#define COPYBACK_MODE 0x1e0
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900125#define COPYBACK_MODE__VALUE GENMASK(3, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100126
127#define RDWR_EN_LO_CNT 0x1f0
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900128#define RDWR_EN_LO_CNT__VALUE GENMASK(4, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100129
130#define RDWR_EN_HI_CNT 0x200
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900131#define RDWR_EN_HI_CNT__VALUE GENMASK(4, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100132
133#define MAX_RD_DELAY 0x210
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900134#define MAX_RD_DELAY__VALUE GENMASK(3, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100135
136#define CS_SETUP_CNT 0x220
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900137#define CS_SETUP_CNT__VALUE GENMASK(4, 0)
Masahiro Yamada1bb88662017-06-13 22:45:37 +0900138#define CS_SETUP_CNT__TWB GENMASK(17, 12)
Jason Robertsce082592010-05-13 15:57:33 +0100139
140#define SPARE_AREA_SKIP_BYTES 0x230
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900141#define SPARE_AREA_SKIP_BYTES__VALUE GENMASK(5, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100142
143#define SPARE_AREA_MARKER 0x240
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900144#define SPARE_AREA_MARKER__VALUE GENMASK(15, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100145
146#define DEVICES_CONNECTED 0x250
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900147#define DEVICES_CONNECTED__VALUE GENMASK(2, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100148
Dong, Chuanxiao6ea9ad22010-07-22 01:32:26 +0800149#define DIE_MASK 0x260
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900150#define DIE_MASK__VALUE GENMASK(7, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100151
152#define FIRST_BLOCK_OF_NEXT_PLANE 0x270
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900153#define FIRST_BLOCK_OF_NEXT_PLANE__VALUE GENMASK(15, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100154
155#define WRITE_PROTECT 0x280
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900156#define WRITE_PROTECT__FLAG BIT(0)
Jason Robertsce082592010-05-13 15:57:33 +0100157
158#define RE_2_RE 0x290
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900159#define RE_2_RE__VALUE GENMASK(5, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100160
Dong, Chuanxiao6ea9ad22010-07-22 01:32:26 +0800161#define MANUFACTURER_ID 0x300
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900162#define MANUFACTURER_ID__VALUE GENMASK(7, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100163
164#define DEVICE_ID 0x310
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900165#define DEVICE_ID__VALUE GENMASK(7, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100166
167#define DEVICE_PARAM_0 0x320
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900168#define DEVICE_PARAM_0__VALUE GENMASK(7, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100169
170#define DEVICE_PARAM_1 0x330
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900171#define DEVICE_PARAM_1__VALUE GENMASK(7, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100172
173#define DEVICE_PARAM_2 0x340
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900174#define DEVICE_PARAM_2__VALUE GENMASK(7, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100175
176#define LOGICAL_PAGE_DATA_SIZE 0x350
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900177#define LOGICAL_PAGE_DATA_SIZE__VALUE GENMASK(15, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100178
179#define LOGICAL_PAGE_SPARE_SIZE 0x360
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900180#define LOGICAL_PAGE_SPARE_SIZE__VALUE GENMASK(15, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100181
Dong, Chuanxiao6ea9ad22010-07-22 01:32:26 +0800182#define REVISION 0x370
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900183#define REVISION__VALUE GENMASK(15, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100184
185#define ONFI_DEVICE_FEATURES 0x380
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900186#define ONFI_DEVICE_FEATURES__VALUE GENMASK(5, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100187
Dong, Chuanxiao6ea9ad22010-07-22 01:32:26 +0800188#define ONFI_OPTIONAL_COMMANDS 0x390
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900189#define ONFI_OPTIONAL_COMMANDS__VALUE GENMASK(5, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100190
191#define ONFI_TIMING_MODE 0x3a0
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900192#define ONFI_TIMING_MODE__VALUE GENMASK(5, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100193
194#define ONFI_PGM_CACHE_TIMING_MODE 0x3b0
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900195#define ONFI_PGM_CACHE_TIMING_MODE__VALUE GENMASK(5, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100196
197#define ONFI_DEVICE_NO_OF_LUNS 0x3c0
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900198#define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS GENMASK(7, 0)
199#define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE BIT(8)
Jason Robertsce082592010-05-13 15:57:33 +0100200
201#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900202#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE GENMASK(15, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100203
204#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900205#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE GENMASK(15, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100206
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900207#define FEATURES 0x3f0
208#define FEATURES__N_BANKS GENMASK(1, 0)
209#define FEATURES__ECC_MAX_ERR GENMASK(5, 2)
210#define FEATURES__DMA BIT(6)
211#define FEATURES__CMD_DMA BIT(7)
212#define FEATURES__PARTITION BIT(8)
213#define FEATURES__XDMA_SIDEBAND BIT(9)
214#define FEATURES__GPREG BIT(10)
215#define FEATURES__INDEX_ADDR BIT(11)
Jason Robertsce082592010-05-13 15:57:33 +0100216
217#define TRANSFER_MODE 0x400
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900218#define TRANSFER_MODE__VALUE GENMASK(1, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100219
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900220#define INTR_STATUS(bank) (0x410 + (bank) * 0x50)
221#define INTR_EN(bank) (0x420 + (bank) * 0x50)
Masahiro Yamada24715c72017-03-30 15:45:52 +0900222/* bit[1:0] is used differently depending on IP version */
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900223#define INTR__ECC_UNCOR_ERR BIT(0) /* new IP */
224#define INTR__ECC_TRANSACTION_DONE BIT(0) /* old IP */
225#define INTR__ECC_ERR BIT(1) /* old IP */
226#define INTR__DMA_CMD_COMP BIT(2)
227#define INTR__TIME_OUT BIT(3)
228#define INTR__PROGRAM_FAIL BIT(4)
229#define INTR__ERASE_FAIL BIT(5)
230#define INTR__LOAD_COMP BIT(6)
231#define INTR__PROGRAM_COMP BIT(7)
232#define INTR__ERASE_COMP BIT(8)
233#define INTR__PIPE_CPYBCK_CMD_COMP BIT(9)
234#define INTR__LOCKED_BLK BIT(10)
235#define INTR__UNSUP_CMD BIT(11)
236#define INTR__INT_ACT BIT(12)
237#define INTR__RST_COMP BIT(13)
238#define INTR__PIPE_CMD_ERR BIT(14)
239#define INTR__PAGE_XFER_INC BIT(15)
Masahiro Yamada57a4d8b2017-06-13 22:45:46 +0900240#define INTR__ERASED_PAGE BIT(16)
Jason Robertsce082592010-05-13 15:57:33 +0100241
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900242#define PAGE_CNT(bank) (0x430 + (bank) * 0x50)
243#define ERR_PAGE_ADDR(bank) (0x440 + (bank) * 0x50)
244#define ERR_BLOCK_ADDR(bank) (0x450 + (bank) * 0x50)
Jason Robertsce082592010-05-13 15:57:33 +0100245
Jason Robertsce082592010-05-13 15:57:33 +0100246#define ECC_THRESHOLD 0x600
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900247#define ECC_THRESHOLD__VALUE GENMASK(9, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100248
Dong, Chuanxiao6ea9ad22010-07-22 01:32:26 +0800249#define ECC_ERROR_BLOCK_ADDRESS 0x610
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900250#define ECC_ERROR_BLOCK_ADDRESS__VALUE GENMASK(15, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100251
252#define ECC_ERROR_PAGE_ADDRESS 0x620
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900253#define ECC_ERROR_PAGE_ADDRESS__VALUE GENMASK(11, 0)
254#define ECC_ERROR_PAGE_ADDRESS__BANK GENMASK(15, 12)
Jason Robertsce082592010-05-13 15:57:33 +0100255
256#define ECC_ERROR_ADDRESS 0x630
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900257#define ECC_ERROR_ADDRESS__OFFSET GENMASK(11, 0)
258#define ECC_ERROR_ADDRESS__SECTOR_NR GENMASK(15, 12)
Jason Robertsce082592010-05-13 15:57:33 +0100259
260#define ERR_CORRECTION_INFO 0x640
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900261#define ERR_CORRECTION_INFO__BYTEMASK GENMASK(7, 0)
262#define ERR_CORRECTION_INFO__DEVICE_NR GENMASK(11, 8)
263#define ERR_CORRECTION_INFO__ERROR_TYPE BIT(14)
264#define ERR_CORRECTION_INFO__LAST_ERR_INFO BIT(15)
Jason Robertsce082592010-05-13 15:57:33 +0100265
Masahiro Yamada24715c72017-03-30 15:45:52 +0900266#define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10)
267#define ECC_COR_INFO__SHIFT(bank) ((bank) % 2 * 8)
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900268#define ECC_COR_INFO__MAX_ERRORS GENMASK(6, 0)
269#define ECC_COR_INFO__UNCOR_ERR BIT(7)
Masahiro Yamada24715c72017-03-30 15:45:52 +0900270
Masahiro Yamada7de117f2017-06-07 20:52:12 +0900271#define CFG_DATA_BLOCK_SIZE 0x6b0
272
273#define CFG_LAST_DATA_BLOCK_SIZE 0x6c0
274
275#define CFG_NUM_DATA_BLOCKS 0x6d0
276
277#define CFG_META_DATA_SIZE 0x6e0
278
Jason Robertsce082592010-05-13 15:57:33 +0100279#define DMA_ENABLE 0x700
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900280#define DMA_ENABLE__FLAG BIT(0)
Jason Robertsce082592010-05-13 15:57:33 +0100281
282#define IGNORE_ECC_DONE 0x710
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900283#define IGNORE_ECC_DONE__FLAG BIT(0)
Jason Robertsce082592010-05-13 15:57:33 +0100284
285#define DMA_INTR 0x720
Masahiro Yamada1aded582017-03-23 05:07:06 +0900286#define DMA_INTR_EN 0x730
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900287#define DMA_INTR__TARGET_ERROR BIT(0)
288#define DMA_INTR__DESC_COMP_CHANNEL0 BIT(1)
289#define DMA_INTR__DESC_COMP_CHANNEL1 BIT(2)
290#define DMA_INTR__DESC_COMP_CHANNEL2 BIT(3)
291#define DMA_INTR__DESC_COMP_CHANNEL3 BIT(4)
292#define DMA_INTR__MEMCOPY_DESC_COMP BIT(5)
Jason Robertsce082592010-05-13 15:57:33 +0100293
294#define TARGET_ERR_ADDR_LO 0x740
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900295#define TARGET_ERR_ADDR_LO__VALUE GENMASK(15, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100296
297#define TARGET_ERR_ADDR_HI 0x750
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900298#define TARGET_ERR_ADDR_HI__VALUE GENMASK(15, 0)
Jason Robertsce082592010-05-13 15:57:33 +0100299
300#define CHNL_ACTIVE 0x760
Masahiro Yamadadf8b9702017-06-06 08:21:41 +0900301#define CHNL_ACTIVE__CHANNEL0 BIT(0)
302#define CHNL_ACTIVE__CHANNEL1 BIT(1)
303#define CHNL_ACTIVE__CHANNEL2 BIT(2)
304#define CHNL_ACTIVE__CHANNEL3 BIT(3)
Jason Robertsce082592010-05-13 15:57:33 +0100305
Jason Robertsce082592010-05-13 15:57:33 +0100306struct denali_nand_info {
Jason Robertsce082592010-05-13 15:57:33 +0100307 struct nand_chip nand;
Masahiro Yamada1bb88662017-06-13 22:45:37 +0900308 unsigned long clk_x_rate; /* bus interface clock rate */
Masahiro Yamada0d3a9662017-06-16 14:36:39 +0900309 int active_bank; /* currently selected bank */
Jamie Iles84457942011-05-06 15:28:55 +0100310 struct device *dev;
Masahiro Yamada0d3a9662017-06-16 14:36:39 +0900311 void __iomem *reg; /* Register Interface */
312 void __iomem *host; /* Host Data/Command Interface */
Jason Robertsce082592010-05-13 15:57:33 +0100313
314 /* elements used by ISR */
315 struct completion complete;
316 spinlock_t irq_lock;
Masahiro Yamadac19e31d2017-06-13 22:45:38 +0900317 uint32_t irq_mask;
Jason Robertsce082592010-05-13 15:57:33 +0100318 uint32_t irq_status;
Dinh Nguyen2a0a2882012-09-27 10:58:05 -0600319 int irq;
Chuanxiao.Dong664065242010-08-06 18:48:21 +0800320
Masahiro Yamada00fc6152017-06-13 22:45:43 +0900321 void *buf;
322 dma_addr_t dma_addr;
Masahiro Yamada26d266e2017-06-13 22:45:45 +0900323 int dma_avail;
Masahiro Yamada0d3a9662017-06-16 14:36:39 +0900324 int devs_per_cs; /* devices connected in parallel */
325 int oob_skip_bytes;
Masahiro Yamadae30b4692017-03-23 05:07:08 +0900326 int max_banks;
Masahiro Yamadae7beeee2017-03-30 15:45:57 +0900327 unsigned int revision;
Masahiro Yamadabe72a4a2017-03-23 05:07:07 +0900328 unsigned int caps;
Masahiro Yamada7de117f2017-06-07 20:52:12 +0900329 const struct nand_ecc_caps *ecc_caps;
Jason Robertsce082592010-05-13 15:57:33 +0100330};
331
Masahiro Yamada24715c72017-03-30 15:45:52 +0900332#define DENALI_CAP_HW_ECC_FIXUP BIT(0)
Masahiro Yamada210a2c82017-03-30 15:45:54 +0900333#define DENALI_CAP_DMA_64BIT BIT(1)
Masahiro Yamada24715c72017-03-30 15:45:52 +0900334
Masahiro Yamada7de117f2017-06-07 20:52:12 +0900335int denali_calc_ecc_bytes(int step_size, int strength);
Dinh Nguyen2a0a2882012-09-27 10:58:05 -0600336extern int denali_init(struct denali_nand_info *denali);
337extern void denali_remove(struct denali_nand_info *denali);
338
Masahiro Yamadaa81b4702014-08-29 20:00:51 +0900339#endif /* __DENALI_H__ */